1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the Atmel USBA high speed USB device controller 4 * 5 * Copyright (C) 2005-2007 Atmel Corporation 6 */ 7#include <linux/clk.h> 8#include <linux/clk/at91_pmc.h> 9#include <linux/module.h> 10#include <linux/init.h> 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/slab.h> 14#include <linux/device.h> 15#include <linux/dma-mapping.h> 16#include <linux/list.h> 17#include <linux/mfd/syscon.h> 18#include <linux/platform_device.h> 19#include <linux/regmap.h> 20#include <linux/ctype.h> 21#include <linux/usb.h> 22#include <linux/usb/ch9.h> 23#include <linux/usb/gadget.h> 24#include <linux/delay.h> 25#include <linux/of.h> 26#include <linux/irq.h> 27#include <linux/gpio/consumer.h> 28 29#include "atmel_usba_udc.h" 30#define USBA_VBUS_IRQFLAGS (IRQF_ONESHOT \ 31 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING) 32 33#ifdef CONFIG_USB_GADGET_DEBUG_FS 34#include <linux/debugfs.h> 35#include <linux/uaccess.h> 36 37static int queue_dbg_open(struct inode *inode, struct file *file) 38{ 39 struct usba_ep *ep = inode->i_private; 40 struct usba_request *req, *req_copy; 41 struct list_head *queue_data; 42 43 queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL); 44 if (!queue_data) 45 return -ENOMEM; 46 INIT_LIST_HEAD(queue_data); 47 48 spin_lock_irq(&ep->udc->lock); 49 list_for_each_entry(req, &ep->queue, queue) { 50 req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC); 51 if (!req_copy) 52 goto fail; 53 list_add_tail(&req_copy->queue, queue_data); 54 } 55 spin_unlock_irq(&ep->udc->lock); 56 57 file->private_data = queue_data; 58 return 0; 59 60fail: 61 spin_unlock_irq(&ep->udc->lock); 62 list_for_each_entry_safe(req, req_copy, queue_data, queue) { 63 list_del(&req->queue); 64 kfree(req); 65 } 66 kfree(queue_data); 67 return -ENOMEM; 68} 69 70/* 71 * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0 72 * 73 * b: buffer address 74 * l: buffer length 75 * I/i: interrupt/no interrupt 76 * Z/z: zero/no zero 77 * S/s: short ok/short not ok 78 * s: status 79 * n: nr_packets 80 * F/f: submitted/not submitted to FIFO 81 * D/d: using/not using DMA 82 * L/l: last transaction/not last transaction 83 */ 84static ssize_t queue_dbg_read(struct file *file, char __user *buf, 85 size_t nbytes, loff_t *ppos) 86{ 87 struct list_head *queue = file->private_data; 88 struct usba_request *req, *tmp_req; 89 size_t len, remaining, actual = 0; 90 char tmpbuf[38]; 91 92 if (!access_ok(buf, nbytes)) 93 return -EFAULT; 94 95 inode_lock(file_inode(file)); 96 list_for_each_entry_safe(req, tmp_req, queue, queue) { 97 len = scnprintf(tmpbuf, sizeof(tmpbuf), 98 "%8p %08x %c%c%c %5d %c%c%c\n", 99 req->req.buf, req->req.length, 100 req->req.no_interrupt ? 'i' : 'I', 101 req->req.zero ? 'Z' : 'z', 102 req->req.short_not_ok ? 's' : 'S', 103 req->req.status, 104 req->submitted ? 'F' : 'f', 105 req->using_dma ? 'D' : 'd', 106 req->last_transaction ? 'L' : 'l'); 107 if (len > nbytes) 108 break; 109 110 list_del(&req->queue); 111 kfree(req); 112 113 remaining = __copy_to_user(buf, tmpbuf, len); 114 actual += len - remaining; 115 if (remaining) 116 break; 117 118 nbytes -= len; 119 buf += len; 120 } 121 inode_unlock(file_inode(file)); 122 123 return actual; 124} 125 126static int queue_dbg_release(struct inode *inode, struct file *file) 127{ 128 struct list_head *queue_data = file->private_data; 129 struct usba_request *req, *tmp_req; 130 131 list_for_each_entry_safe(req, tmp_req, queue_data, queue) { 132 list_del(&req->queue); 133 kfree(req); 134 } 135 kfree(queue_data); 136 return 0; 137} 138 139static int regs_dbg_open(struct inode *inode, struct file *file) 140{ 141 struct usba_udc *udc; 142 unsigned int i; 143 u32 *data; 144 int ret = -ENOMEM; 145 146 inode_lock(inode); 147 udc = inode->i_private; 148 data = kmalloc(inode->i_size, GFP_KERNEL); 149 if (!data) 150 goto out; 151 152 spin_lock_irq(&udc->lock); 153 for (i = 0; i < inode->i_size / 4; i++) 154 data[i] = readl_relaxed(udc->regs + i * 4); 155 spin_unlock_irq(&udc->lock); 156 157 file->private_data = data; 158 ret = 0; 159 160out: 161 inode_unlock(inode); 162 163 return ret; 164} 165 166static ssize_t regs_dbg_read(struct file *file, char __user *buf, 167 size_t nbytes, loff_t *ppos) 168{ 169 struct inode *inode = file_inode(file); 170 int ret; 171 172 inode_lock(inode); 173 ret = simple_read_from_buffer(buf, nbytes, ppos, 174 file->private_data, 175 file_inode(file)->i_size); 176 inode_unlock(inode); 177 178 return ret; 179} 180 181static int regs_dbg_release(struct inode *inode, struct file *file) 182{ 183 kfree(file->private_data); 184 return 0; 185} 186 187static const struct file_operations queue_dbg_fops = { 188 .owner = THIS_MODULE, 189 .open = queue_dbg_open, 190 .llseek = no_llseek, 191 .read = queue_dbg_read, 192 .release = queue_dbg_release, 193}; 194 195static const struct file_operations regs_dbg_fops = { 196 .owner = THIS_MODULE, 197 .open = regs_dbg_open, 198 .llseek = generic_file_llseek, 199 .read = regs_dbg_read, 200 .release = regs_dbg_release, 201}; 202 203static void usba_ep_init_debugfs(struct usba_udc *udc, 204 struct usba_ep *ep) 205{ 206 struct dentry *ep_root; 207 208 ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root); 209 ep->debugfs_dir = ep_root; 210 211 debugfs_create_file("queue", 0400, ep_root, ep, &queue_dbg_fops); 212 if (ep->can_dma) 213 debugfs_create_u32("dma_status", 0400, ep_root, 214 &ep->last_dma_status); 215 if (ep_is_control(ep)) 216 debugfs_create_u32("state", 0400, ep_root, &ep->state); 217} 218 219static void usba_ep_cleanup_debugfs(struct usba_ep *ep) 220{ 221 debugfs_remove_recursive(ep->debugfs_dir); 222} 223 224static void usba_init_debugfs(struct usba_udc *udc) 225{ 226 struct dentry *root; 227 struct resource *regs_resource; 228 229 root = debugfs_create_dir(udc->gadget.name, usb_debug_root); 230 udc->debugfs_root = root; 231 232 regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM, 233 CTRL_IOMEM_ID); 234 235 if (regs_resource) { 236 debugfs_create_file_size("regs", 0400, root, udc, 237 ®s_dbg_fops, 238 resource_size(regs_resource)); 239 } 240 241 usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0)); 242} 243 244static void usba_cleanup_debugfs(struct usba_udc *udc) 245{ 246 usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0)); 247 debugfs_remove_recursive(udc->debugfs_root); 248} 249#else 250static inline void usba_ep_init_debugfs(struct usba_udc *udc, 251 struct usba_ep *ep) 252{ 253 254} 255 256static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep) 257{ 258 259} 260 261static inline void usba_init_debugfs(struct usba_udc *udc) 262{ 263 264} 265 266static inline void usba_cleanup_debugfs(struct usba_udc *udc) 267{ 268 269} 270#endif 271 272static ushort fifo_mode; 273 274module_param(fifo_mode, ushort, 0x0); 275MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode"); 276 277/* mode 0 - uses autoconfig */ 278 279/* mode 1 - fits in 8KB, generic max fifo configuration */ 280static struct usba_fifo_cfg mode_1_cfg[] = { 281{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 282{ .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, }, 283{ .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, }, 284{ .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, }, 285{ .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, }, 286{ .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, }, 287{ .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, }, 288}; 289 290/* mode 2 - fits in 8KB, performance max fifo configuration */ 291static struct usba_fifo_cfg mode_2_cfg[] = { 292{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 293{ .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, }, 294{ .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, }, 295{ .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, }, 296}; 297 298/* mode 3 - fits in 8KB, mixed fifo configuration */ 299static struct usba_fifo_cfg mode_3_cfg[] = { 300{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 301{ .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, }, 302{ .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, }, 303{ .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, }, 304{ .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, }, 305{ .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, }, 306{ .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, }, 307}; 308 309/* mode 4 - fits in 8KB, custom fifo configuration */ 310static struct usba_fifo_cfg mode_4_cfg[] = { 311{ .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 312{ .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, }, 313{ .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, }, 314{ .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, }, 315{ .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, }, 316{ .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, }, 317{ .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, }, 318{ .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, }, 319{ .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, }, 320}; 321/* Add additional configurations here */ 322 323static int usba_config_fifo_table(struct usba_udc *udc) 324{ 325 int n; 326 327 switch (fifo_mode) { 328 default: 329 fifo_mode = 0; 330 fallthrough; 331 case 0: 332 udc->fifo_cfg = NULL; 333 n = 0; 334 break; 335 case 1: 336 udc->fifo_cfg = mode_1_cfg; 337 n = ARRAY_SIZE(mode_1_cfg); 338 break; 339 case 2: 340 udc->fifo_cfg = mode_2_cfg; 341 n = ARRAY_SIZE(mode_2_cfg); 342 break; 343 case 3: 344 udc->fifo_cfg = mode_3_cfg; 345 n = ARRAY_SIZE(mode_3_cfg); 346 break; 347 case 4: 348 udc->fifo_cfg = mode_4_cfg; 349 n = ARRAY_SIZE(mode_4_cfg); 350 break; 351 } 352 DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode); 353 354 return n; 355} 356 357static inline u32 usba_int_enb_get(struct usba_udc *udc) 358{ 359 return udc->int_enb_cache; 360} 361 362static inline void usba_int_enb_set(struct usba_udc *udc, u32 mask) 363{ 364 u32 val; 365 366 val = udc->int_enb_cache | mask; 367 usba_writel(udc, INT_ENB, val); 368 udc->int_enb_cache = val; 369} 370 371static inline void usba_int_enb_clear(struct usba_udc *udc, u32 mask) 372{ 373 u32 val; 374 375 val = udc->int_enb_cache & ~mask; 376 usba_writel(udc, INT_ENB, val); 377 udc->int_enb_cache = val; 378} 379 380static int vbus_is_present(struct usba_udc *udc) 381{ 382 if (udc->vbus_pin) 383 return gpiod_get_value(udc->vbus_pin); 384 385 /* No Vbus detection: Assume always present */ 386 return 1; 387} 388 389static void toggle_bias(struct usba_udc *udc, int is_on) 390{ 391 if (udc->errata && udc->errata->toggle_bias) 392 udc->errata->toggle_bias(udc, is_on); 393} 394 395static void generate_bias_pulse(struct usba_udc *udc) 396{ 397 if (!udc->bias_pulse_needed) 398 return; 399 400 if (udc->errata && udc->errata->pulse_bias) 401 udc->errata->pulse_bias(udc); 402 403 udc->bias_pulse_needed = false; 404} 405 406static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req) 407{ 408 unsigned int transaction_len; 409 410 transaction_len = req->req.length - req->req.actual; 411 req->last_transaction = 1; 412 if (transaction_len > ep->ep.maxpacket) { 413 transaction_len = ep->ep.maxpacket; 414 req->last_transaction = 0; 415 } else if (transaction_len == ep->ep.maxpacket && req->req.zero) 416 req->last_transaction = 0; 417 418 DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n", 419 ep->ep.name, req, transaction_len, 420 req->last_transaction ? ", done" : ""); 421 422 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len); 423 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 424 req->req.actual += transaction_len; 425} 426 427static void submit_request(struct usba_ep *ep, struct usba_request *req) 428{ 429 DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n", 430 ep->ep.name, req, req->req.length); 431 432 req->req.actual = 0; 433 req->submitted = 1; 434 435 if (req->using_dma) { 436 if (req->req.length == 0) { 437 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); 438 return; 439 } 440 441 if (req->req.zero) 442 usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET); 443 else 444 usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET); 445 446 usba_dma_writel(ep, ADDRESS, req->req.dma); 447 usba_dma_writel(ep, CONTROL, req->ctrl); 448 } else { 449 next_fifo_transaction(ep, req); 450 if (req->last_transaction) { 451 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); 452 if (ep_is_control(ep)) 453 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); 454 } else { 455 if (ep_is_control(ep)) 456 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 457 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); 458 } 459 } 460} 461 462static void submit_next_request(struct usba_ep *ep) 463{ 464 struct usba_request *req; 465 466 if (list_empty(&ep->queue)) { 467 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY); 468 return; 469 } 470 471 req = list_entry(ep->queue.next, struct usba_request, queue); 472 if (!req->submitted) 473 submit_request(ep, req); 474} 475 476static void send_status(struct usba_udc *udc, struct usba_ep *ep) 477{ 478 ep->state = STATUS_STAGE_IN; 479 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 480 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); 481} 482 483static void receive_data(struct usba_ep *ep) 484{ 485 struct usba_udc *udc = ep->udc; 486 struct usba_request *req; 487 unsigned long status; 488 unsigned int bytecount, nr_busy; 489 int is_complete = 0; 490 491 status = usba_ep_readl(ep, STA); 492 nr_busy = USBA_BFEXT(BUSY_BANKS, status); 493 494 DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy); 495 496 while (nr_busy > 0) { 497 if (list_empty(&ep->queue)) { 498 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 499 break; 500 } 501 req = list_entry(ep->queue.next, 502 struct usba_request, queue); 503 504 bytecount = USBA_BFEXT(BYTE_COUNT, status); 505 506 if (status & (1 << 31)) 507 is_complete = 1; 508 if (req->req.actual + bytecount >= req->req.length) { 509 is_complete = 1; 510 bytecount = req->req.length - req->req.actual; 511 } 512 513 memcpy_fromio(req->req.buf + req->req.actual, 514 ep->fifo, bytecount); 515 req->req.actual += bytecount; 516 517 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); 518 519 if (is_complete) { 520 DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name); 521 req->req.status = 0; 522 list_del_init(&req->queue); 523 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 524 spin_unlock(&udc->lock); 525 usb_gadget_giveback_request(&ep->ep, &req->req); 526 spin_lock(&udc->lock); 527 } 528 529 status = usba_ep_readl(ep, STA); 530 nr_busy = USBA_BFEXT(BUSY_BANKS, status); 531 532 if (is_complete && ep_is_control(ep)) { 533 send_status(udc, ep); 534 break; 535 } 536 } 537} 538 539static void 540request_complete(struct usba_ep *ep, struct usba_request *req, int status) 541{ 542 struct usba_udc *udc = ep->udc; 543 544 WARN_ON(!list_empty(&req->queue)); 545 546 if (req->req.status == -EINPROGRESS) 547 req->req.status = status; 548 549 if (req->using_dma) 550 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); 551 552 DBG(DBG_GADGET | DBG_REQ, 553 "%s: req %p complete: status %d, actual %u\n", 554 ep->ep.name, req, req->req.status, req->req.actual); 555 556 spin_unlock(&udc->lock); 557 usb_gadget_giveback_request(&ep->ep, &req->req); 558 spin_lock(&udc->lock); 559} 560 561static void 562request_complete_list(struct usba_ep *ep, struct list_head *list, int status) 563{ 564 struct usba_request *req, *tmp_req; 565 566 list_for_each_entry_safe(req, tmp_req, list, queue) { 567 list_del_init(&req->queue); 568 request_complete(ep, req, status); 569 } 570} 571 572static int 573usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) 574{ 575 struct usba_ep *ep = to_usba_ep(_ep); 576 struct usba_udc *udc = ep->udc; 577 unsigned long flags, maxpacket; 578 unsigned int nr_trans; 579 580 DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc); 581 582 maxpacket = usb_endpoint_maxp(desc); 583 584 if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index) 585 || ep->index == 0 586 || desc->bDescriptorType != USB_DT_ENDPOINT 587 || maxpacket == 0 588 || maxpacket > ep->fifo_size) { 589 DBG(DBG_ERR, "ep_enable: Invalid argument"); 590 return -EINVAL; 591 } 592 593 ep->is_isoc = 0; 594 ep->is_in = 0; 595 596 DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n", 597 ep->ep.name, ep->ept_cfg, maxpacket); 598 599 if (usb_endpoint_dir_in(desc)) { 600 ep->is_in = 1; 601 ep->ept_cfg |= USBA_EPT_DIR_IN; 602 } 603 604 switch (usb_endpoint_type(desc)) { 605 case USB_ENDPOINT_XFER_CONTROL: 606 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL); 607 break; 608 case USB_ENDPOINT_XFER_ISOC: 609 if (!ep->can_isoc) { 610 DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n", 611 ep->ep.name); 612 return -EINVAL; 613 } 614 615 /* 616 * Bits 11:12 specify number of _additional_ 617 * transactions per microframe. 618 */ 619 nr_trans = usb_endpoint_maxp_mult(desc); 620 if (nr_trans > 3) 621 return -EINVAL; 622 623 ep->is_isoc = 1; 624 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO); 625 ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans); 626 627 break; 628 case USB_ENDPOINT_XFER_BULK: 629 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK); 630 break; 631 case USB_ENDPOINT_XFER_INT: 632 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT); 633 break; 634 } 635 636 spin_lock_irqsave(&ep->udc->lock, flags); 637 638 ep->ep.desc = desc; 639 ep->ep.maxpacket = maxpacket; 640 641 usba_ep_writel(ep, CFG, ep->ept_cfg); 642 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 643 644 if (ep->can_dma) { 645 u32 ctrl; 646 647 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index) | 648 USBA_BF(DMA_INT, 1 << ep->index)); 649 ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA; 650 usba_ep_writel(ep, CTL_ENB, ctrl); 651 } else { 652 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index)); 653 } 654 655 spin_unlock_irqrestore(&udc->lock, flags); 656 657 DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index, 658 (unsigned long)usba_ep_readl(ep, CFG)); 659 DBG(DBG_HW, "INT_ENB after init: %#08lx\n", 660 (unsigned long)usba_int_enb_get(udc)); 661 662 return 0; 663} 664 665static int usba_ep_disable(struct usb_ep *_ep) 666{ 667 struct usba_ep *ep = to_usba_ep(_ep); 668 struct usba_udc *udc = ep->udc; 669 LIST_HEAD(req_list); 670 unsigned long flags; 671 672 DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name); 673 674 spin_lock_irqsave(&udc->lock, flags); 675 676 if (!ep->ep.desc) { 677 spin_unlock_irqrestore(&udc->lock, flags); 678 DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name); 679 return -EINVAL; 680 } 681 ep->ep.desc = NULL; 682 683 list_splice_init(&ep->queue, &req_list); 684 if (ep->can_dma) { 685 usba_dma_writel(ep, CONTROL, 0); 686 usba_dma_writel(ep, ADDRESS, 0); 687 usba_dma_readl(ep, STATUS); 688 } 689 usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE); 690 usba_int_enb_clear(udc, USBA_BF(EPT_INT, 1 << ep->index)); 691 692 request_complete_list(ep, &req_list, -ESHUTDOWN); 693 694 spin_unlock_irqrestore(&udc->lock, flags); 695 696 return 0; 697} 698 699static struct usb_request * 700usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 701{ 702 struct usba_request *req; 703 704 DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags); 705 706 req = kzalloc(sizeof(*req), gfp_flags); 707 if (!req) 708 return NULL; 709 710 INIT_LIST_HEAD(&req->queue); 711 712 return &req->req; 713} 714 715static void 716usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 717{ 718 struct usba_request *req = to_usba_req(_req); 719 720 DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req); 721 722 kfree(req); 723} 724 725static int queue_dma(struct usba_udc *udc, struct usba_ep *ep, 726 struct usba_request *req, gfp_t gfp_flags) 727{ 728 unsigned long flags; 729 int ret; 730 731 DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n", 732 ep->ep.name, req->req.length, &req->req.dma, 733 req->req.zero ? 'Z' : 'z', 734 req->req.short_not_ok ? 'S' : 's', 735 req->req.no_interrupt ? 'I' : 'i'); 736 737 if (req->req.length > 0x10000) { 738 /* Lengths from 0 to 65536 (inclusive) are supported */ 739 DBG(DBG_ERR, "invalid request length %u\n", req->req.length); 740 return -EINVAL; 741 } 742 743 ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in); 744 if (ret) 745 return ret; 746 747 req->using_dma = 1; 748 req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length) 749 | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE 750 | USBA_DMA_END_BUF_EN; 751 752 if (!ep->is_in) 753 req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE; 754 755 /* 756 * Add this request to the queue and submit for DMA if 757 * possible. Check if we're still alive first -- we may have 758 * received a reset since last time we checked. 759 */ 760 ret = -ESHUTDOWN; 761 spin_lock_irqsave(&udc->lock, flags); 762 if (ep->ep.desc) { 763 if (list_empty(&ep->queue)) 764 submit_request(ep, req); 765 766 list_add_tail(&req->queue, &ep->queue); 767 ret = 0; 768 } 769 spin_unlock_irqrestore(&udc->lock, flags); 770 771 return ret; 772} 773 774static int 775usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 776{ 777 struct usba_request *req = to_usba_req(_req); 778 struct usba_ep *ep = to_usba_ep(_ep); 779 struct usba_udc *udc = ep->udc; 780 unsigned long flags; 781 int ret; 782 783 DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n", 784 ep->ep.name, req, _req->length); 785 786 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || 787 !ep->ep.desc) 788 return -ESHUTDOWN; 789 790 req->submitted = 0; 791 req->using_dma = 0; 792 req->last_transaction = 0; 793 794 _req->status = -EINPROGRESS; 795 _req->actual = 0; 796 797 if (ep->can_dma) 798 return queue_dma(udc, ep, req, gfp_flags); 799 800 /* May have received a reset since last time we checked */ 801 ret = -ESHUTDOWN; 802 spin_lock_irqsave(&udc->lock, flags); 803 if (ep->ep.desc) { 804 list_add_tail(&req->queue, &ep->queue); 805 806 if ((!ep_is_control(ep) && ep->is_in) || 807 (ep_is_control(ep) 808 && (ep->state == DATA_STAGE_IN 809 || ep->state == STATUS_STAGE_IN))) 810 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); 811 else 812 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY); 813 ret = 0; 814 } 815 spin_unlock_irqrestore(&udc->lock, flags); 816 817 return ret; 818} 819 820static void 821usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status) 822{ 823 req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status); 824} 825 826static int stop_dma(struct usba_ep *ep, u32 *pstatus) 827{ 828 unsigned int timeout; 829 u32 status; 830 831 /* 832 * Stop the DMA controller. When writing both CH_EN 833 * and LINK to 0, the other bits are not affected. 834 */ 835 usba_dma_writel(ep, CONTROL, 0); 836 837 /* Wait for the FIFO to empty */ 838 for (timeout = 40; timeout; --timeout) { 839 status = usba_dma_readl(ep, STATUS); 840 if (!(status & USBA_DMA_CH_EN)) 841 break; 842 udelay(1); 843 } 844 845 if (pstatus) 846 *pstatus = status; 847 848 if (timeout == 0) { 849 dev_err(&ep->udc->pdev->dev, 850 "%s: timed out waiting for DMA FIFO to empty\n", 851 ep->ep.name); 852 return -ETIMEDOUT; 853 } 854 855 return 0; 856} 857 858static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 859{ 860 struct usba_ep *ep = to_usba_ep(_ep); 861 struct usba_udc *udc = ep->udc; 862 struct usba_request *req = NULL; 863 struct usba_request *iter; 864 unsigned long flags; 865 u32 status; 866 867 DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n", 868 ep->ep.name, _req); 869 870 spin_lock_irqsave(&udc->lock, flags); 871 872 list_for_each_entry(iter, &ep->queue, queue) { 873 if (&iter->req != _req) 874 continue; 875 req = iter; 876 break; 877 } 878 879 if (!req) { 880 spin_unlock_irqrestore(&udc->lock, flags); 881 return -EINVAL; 882 } 883 884 if (req->using_dma) { 885 /* 886 * If this request is currently being transferred, 887 * stop the DMA controller and reset the FIFO. 888 */ 889 if (ep->queue.next == &req->queue) { 890 status = usba_dma_readl(ep, STATUS); 891 if (status & USBA_DMA_CH_EN) 892 stop_dma(ep, &status); 893 894#ifdef CONFIG_USB_GADGET_DEBUG_FS 895 ep->last_dma_status = status; 896#endif 897 898 usba_writel(udc, EPT_RST, 1 << ep->index); 899 900 usba_update_req(ep, req, status); 901 } 902 } 903 904 /* 905 * Errors should stop the queue from advancing until the 906 * completion function returns. 907 */ 908 list_del_init(&req->queue); 909 910 request_complete(ep, req, -ECONNRESET); 911 912 /* Process the next request if any */ 913 submit_next_request(ep); 914 spin_unlock_irqrestore(&udc->lock, flags); 915 916 return 0; 917} 918 919static int usba_ep_set_halt(struct usb_ep *_ep, int value) 920{ 921 struct usba_ep *ep = to_usba_ep(_ep); 922 struct usba_udc *udc = ep->udc; 923 unsigned long flags; 924 int ret = 0; 925 926 DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name, 927 value ? "set" : "clear"); 928 929 if (!ep->ep.desc) { 930 DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n", 931 ep->ep.name); 932 return -ENODEV; 933 } 934 if (ep->is_isoc) { 935 DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n", 936 ep->ep.name); 937 return -ENOTTY; 938 } 939 940 spin_lock_irqsave(&udc->lock, flags); 941 942 /* 943 * We can't halt IN endpoints while there are still data to be 944 * transferred 945 */ 946 if (!list_empty(&ep->queue) 947 || ((value && ep->is_in && (usba_ep_readl(ep, STA) 948 & USBA_BF(BUSY_BANKS, -1L))))) { 949 ret = -EAGAIN; 950 } else { 951 if (value) 952 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL); 953 else 954 usba_ep_writel(ep, CLR_STA, 955 USBA_FORCE_STALL | USBA_TOGGLE_CLR); 956 usba_ep_readl(ep, STA); 957 } 958 959 spin_unlock_irqrestore(&udc->lock, flags); 960 961 return ret; 962} 963 964static int usba_ep_fifo_status(struct usb_ep *_ep) 965{ 966 struct usba_ep *ep = to_usba_ep(_ep); 967 968 return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA)); 969} 970 971static void usba_ep_fifo_flush(struct usb_ep *_ep) 972{ 973 struct usba_ep *ep = to_usba_ep(_ep); 974 struct usba_udc *udc = ep->udc; 975 976 usba_writel(udc, EPT_RST, 1 << ep->index); 977} 978 979static const struct usb_ep_ops usba_ep_ops = { 980 .enable = usba_ep_enable, 981 .disable = usba_ep_disable, 982 .alloc_request = usba_ep_alloc_request, 983 .free_request = usba_ep_free_request, 984 .queue = usba_ep_queue, 985 .dequeue = usba_ep_dequeue, 986 .set_halt = usba_ep_set_halt, 987 .fifo_status = usba_ep_fifo_status, 988 .fifo_flush = usba_ep_fifo_flush, 989}; 990 991static int usba_udc_get_frame(struct usb_gadget *gadget) 992{ 993 struct usba_udc *udc = to_usba_udc(gadget); 994 995 return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM)); 996} 997 998static int usba_udc_wakeup(struct usb_gadget *gadget) 999{ 1000 struct usba_udc *udc = to_usba_udc(gadget); 1001 unsigned long flags; 1002 u32 ctrl; 1003 int ret = -EINVAL; 1004 1005 spin_lock_irqsave(&udc->lock, flags); 1006 if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) { 1007 ctrl = usba_readl(udc, CTRL); 1008 usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP); 1009 ret = 0; 1010 } 1011 spin_unlock_irqrestore(&udc->lock, flags); 1012 1013 return ret; 1014} 1015 1016static int 1017usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) 1018{ 1019 struct usba_udc *udc = to_usba_udc(gadget); 1020 unsigned long flags; 1021 1022 gadget->is_selfpowered = (is_selfpowered != 0); 1023 spin_lock_irqsave(&udc->lock, flags); 1024 if (is_selfpowered) 1025 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED; 1026 else 1027 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED); 1028 spin_unlock_irqrestore(&udc->lock, flags); 1029 1030 return 0; 1031} 1032 1033static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on); 1034static int atmel_usba_start(struct usb_gadget *gadget, 1035 struct usb_gadget_driver *driver); 1036static int atmel_usba_stop(struct usb_gadget *gadget); 1037 1038static struct usb_ep *atmel_usba_match_ep(struct usb_gadget *gadget, 1039 struct usb_endpoint_descriptor *desc, 1040 struct usb_ss_ep_comp_descriptor *ep_comp) 1041{ 1042 struct usb_ep *_ep; 1043 struct usba_ep *ep; 1044 1045 /* Look at endpoints until an unclaimed one looks usable */ 1046 list_for_each_entry(_ep, &gadget->ep_list, ep_list) { 1047 if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp)) 1048 goto found_ep; 1049 } 1050 /* Fail */ 1051 return NULL; 1052 1053found_ep: 1054 1055 if (fifo_mode == 0) { 1056 /* Optimize hw fifo size based on ep type and other info */ 1057 ep = to_usba_ep(_ep); 1058 1059 switch (usb_endpoint_type(desc)) { 1060 case USB_ENDPOINT_XFER_CONTROL: 1061 ep->nr_banks = 1; 1062 break; 1063 1064 case USB_ENDPOINT_XFER_ISOC: 1065 ep->fifo_size = 1024; 1066 if (ep->udc->ep_prealloc) 1067 ep->nr_banks = 2; 1068 break; 1069 1070 case USB_ENDPOINT_XFER_BULK: 1071 ep->fifo_size = 512; 1072 if (ep->udc->ep_prealloc) 1073 ep->nr_banks = 1; 1074 break; 1075 1076 case USB_ENDPOINT_XFER_INT: 1077 if (desc->wMaxPacketSize == 0) 1078 ep->fifo_size = 1079 roundup_pow_of_two(_ep->maxpacket_limit); 1080 else 1081 ep->fifo_size = 1082 roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize)); 1083 if (ep->udc->ep_prealloc) 1084 ep->nr_banks = 1; 1085 break; 1086 } 1087 1088 /* It might be a little bit late to set this */ 1089 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size); 1090 1091 /* Generate ept_cfg basd on FIFO size and number of banks */ 1092 if (ep->fifo_size <= 8) 1093 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8); 1094 else 1095 /* LSB is bit 1, not 0 */ 1096 ep->ept_cfg = 1097 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3); 1098 1099 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks); 1100 } 1101 1102 return _ep; 1103} 1104 1105static const struct usb_gadget_ops usba_udc_ops = { 1106 .get_frame = usba_udc_get_frame, 1107 .wakeup = usba_udc_wakeup, 1108 .set_selfpowered = usba_udc_set_selfpowered, 1109 .pullup = atmel_usba_pullup, 1110 .udc_start = atmel_usba_start, 1111 .udc_stop = atmel_usba_stop, 1112 .match_ep = atmel_usba_match_ep, 1113}; 1114 1115static struct usb_endpoint_descriptor usba_ep0_desc = { 1116 .bLength = USB_DT_ENDPOINT_SIZE, 1117 .bDescriptorType = USB_DT_ENDPOINT, 1118 .bEndpointAddress = 0, 1119 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1120 .wMaxPacketSize = cpu_to_le16(64), 1121 /* FIXME: I have no idea what to put here */ 1122 .bInterval = 1, 1123}; 1124 1125static const struct usb_gadget usba_gadget_template = { 1126 .ops = &usba_udc_ops, 1127 .max_speed = USB_SPEED_HIGH, 1128 .name = "atmel_usba_udc", 1129}; 1130 1131/* 1132 * Called with interrupts disabled and udc->lock held. 1133 */ 1134static void reset_all_endpoints(struct usba_udc *udc) 1135{ 1136 struct usba_ep *ep; 1137 struct usba_request *req, *tmp_req; 1138 1139 usba_writel(udc, EPT_RST, ~0UL); 1140 1141 ep = to_usba_ep(udc->gadget.ep0); 1142 list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) { 1143 list_del_init(&req->queue); 1144 request_complete(ep, req, -ECONNRESET); 1145 } 1146} 1147 1148static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex) 1149{ 1150 struct usba_ep *ep; 1151 1152 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) 1153 return to_usba_ep(udc->gadget.ep0); 1154 1155 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { 1156 u8 bEndpointAddress; 1157 1158 if (!ep->ep.desc) 1159 continue; 1160 bEndpointAddress = ep->ep.desc->bEndpointAddress; 1161 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN) 1162 continue; 1163 if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) 1164 == (wIndex & USB_ENDPOINT_NUMBER_MASK)) 1165 return ep; 1166 } 1167 1168 return NULL; 1169} 1170 1171/* Called with interrupts disabled and udc->lock held */ 1172static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep) 1173{ 1174 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL); 1175 ep->state = WAIT_FOR_SETUP; 1176} 1177 1178static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep) 1179{ 1180 if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL) 1181 return 1; 1182 return 0; 1183} 1184 1185static inline void set_address(struct usba_udc *udc, unsigned int addr) 1186{ 1187 u32 regval; 1188 1189 DBG(DBG_BUS, "setting address %u...\n", addr); 1190 regval = usba_readl(udc, CTRL); 1191 regval = USBA_BFINS(DEV_ADDR, addr, regval); 1192 usba_writel(udc, CTRL, regval); 1193} 1194 1195static int do_test_mode(struct usba_udc *udc) 1196{ 1197 static const char test_packet_buffer[] = { 1198 /* JKJKJKJK * 9 */ 1199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1200 /* JJKKJJKK * 8 */ 1201 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 1202 /* JJKKJJKK * 8 */ 1203 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 1204 /* JJJJJJJKKKKKKK * 8 */ 1205 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1206 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1207 /* JJJJJJJK * 8 */ 1208 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 1209 /* {JKKKKKKK * 10}, JK */ 1210 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E 1211 }; 1212 struct usba_ep *ep; 1213 struct device *dev = &udc->pdev->dev; 1214 int test_mode; 1215 1216 test_mode = udc->test_mode; 1217 1218 /* Start from a clean slate */ 1219 reset_all_endpoints(udc); 1220 1221 switch (test_mode) { 1222 case 0x0100: 1223 /* Test_J */ 1224 usba_writel(udc, TST, USBA_TST_J_MODE); 1225 dev_info(dev, "Entering Test_J mode...\n"); 1226 break; 1227 case 0x0200: 1228 /* Test_K */ 1229 usba_writel(udc, TST, USBA_TST_K_MODE); 1230 dev_info(dev, "Entering Test_K mode...\n"); 1231 break; 1232 case 0x0300: 1233 /* 1234 * Test_SE0_NAK: Force high-speed mode and set up ep0 1235 * for Bulk IN transfers 1236 */ 1237 ep = &udc->usba_ep[0]; 1238 usba_writel(udc, TST, 1239 USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH)); 1240 usba_ep_writel(ep, CFG, 1241 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) 1242 | USBA_EPT_DIR_IN 1243 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK) 1244 | USBA_BF(BK_NUMBER, 1)); 1245 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { 1246 set_protocol_stall(udc, ep); 1247 dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n"); 1248 } else { 1249 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 1250 dev_info(dev, "Entering Test_SE0_NAK mode...\n"); 1251 } 1252 break; 1253 case 0x0400: 1254 /* Test_Packet */ 1255 ep = &udc->usba_ep[0]; 1256 usba_ep_writel(ep, CFG, 1257 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) 1258 | USBA_EPT_DIR_IN 1259 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK) 1260 | USBA_BF(BK_NUMBER, 1)); 1261 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { 1262 set_protocol_stall(udc, ep); 1263 dev_err(dev, "Test_Packet: ep0 not mapped\n"); 1264 } else { 1265 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 1266 usba_writel(udc, TST, USBA_TST_PKT_MODE); 1267 memcpy_toio(ep->fifo, test_packet_buffer, 1268 sizeof(test_packet_buffer)); 1269 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 1270 dev_info(dev, "Entering Test_Packet mode...\n"); 1271 } 1272 break; 1273 default: 1274 dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode); 1275 return -EINVAL; 1276 } 1277 1278 return 0; 1279} 1280 1281/* Avoid overly long expressions */ 1282static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq) 1283{ 1284 if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP)) 1285 return true; 1286 return false; 1287} 1288 1289static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq) 1290{ 1291 if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE)) 1292 return true; 1293 return false; 1294} 1295 1296static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq) 1297{ 1298 if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT)) 1299 return true; 1300 return false; 1301} 1302 1303static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep, 1304 struct usb_ctrlrequest *crq) 1305{ 1306 int retval = 0; 1307 1308 switch (crq->bRequest) { 1309 case USB_REQ_GET_STATUS: { 1310 u16 status; 1311 1312 if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) { 1313 status = cpu_to_le16(udc->devstatus); 1314 } else if (crq->bRequestType 1315 == (USB_DIR_IN | USB_RECIP_INTERFACE)) { 1316 status = cpu_to_le16(0); 1317 } else if (crq->bRequestType 1318 == (USB_DIR_IN | USB_RECIP_ENDPOINT)) { 1319 struct usba_ep *target; 1320 1321 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); 1322 if (!target) 1323 goto stall; 1324 1325 status = 0; 1326 if (is_stalled(udc, target)) 1327 status |= cpu_to_le16(1); 1328 } else 1329 goto delegate; 1330 1331 /* Write directly to the FIFO. No queueing is done. */ 1332 if (crq->wLength != cpu_to_le16(sizeof(status))) 1333 goto stall; 1334 ep->state = DATA_STAGE_IN; 1335 writew_relaxed(status, ep->fifo); 1336 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 1337 break; 1338 } 1339 1340 case USB_REQ_CLEAR_FEATURE: { 1341 if (crq->bRequestType == USB_RECIP_DEVICE) { 1342 if (feature_is_dev_remote_wakeup(crq)) 1343 udc->devstatus 1344 &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); 1345 else 1346 /* Can't CLEAR_FEATURE TEST_MODE */ 1347 goto stall; 1348 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) { 1349 struct usba_ep *target; 1350 1351 if (crq->wLength != cpu_to_le16(0) 1352 || !feature_is_ep_halt(crq)) 1353 goto stall; 1354 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); 1355 if (!target) 1356 goto stall; 1357 1358 usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL); 1359 if (target->index != 0) 1360 usba_ep_writel(target, CLR_STA, 1361 USBA_TOGGLE_CLR); 1362 } else { 1363 goto delegate; 1364 } 1365 1366 send_status(udc, ep); 1367 break; 1368 } 1369 1370 case USB_REQ_SET_FEATURE: { 1371 if (crq->bRequestType == USB_RECIP_DEVICE) { 1372 if (feature_is_dev_test_mode(crq)) { 1373 send_status(udc, ep); 1374 ep->state = STATUS_STAGE_TEST; 1375 udc->test_mode = le16_to_cpu(crq->wIndex); 1376 return 0; 1377 } else if (feature_is_dev_remote_wakeup(crq)) { 1378 udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP; 1379 } else { 1380 goto stall; 1381 } 1382 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) { 1383 struct usba_ep *target; 1384 1385 if (crq->wLength != cpu_to_le16(0) 1386 || !feature_is_ep_halt(crq)) 1387 goto stall; 1388 1389 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); 1390 if (!target) 1391 goto stall; 1392 1393 usba_ep_writel(target, SET_STA, USBA_FORCE_STALL); 1394 } else 1395 goto delegate; 1396 1397 send_status(udc, ep); 1398 break; 1399 } 1400 1401 case USB_REQ_SET_ADDRESS: 1402 if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE)) 1403 goto delegate; 1404 1405 set_address(udc, le16_to_cpu(crq->wValue)); 1406 send_status(udc, ep); 1407 ep->state = STATUS_STAGE_ADDR; 1408 break; 1409 1410 default: 1411delegate: 1412 spin_unlock(&udc->lock); 1413 retval = udc->driver->setup(&udc->gadget, crq); 1414 spin_lock(&udc->lock); 1415 } 1416 1417 return retval; 1418 1419stall: 1420 pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, " 1421 "halting endpoint...\n", 1422 ep->ep.name, crq->bRequestType, crq->bRequest, 1423 le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex), 1424 le16_to_cpu(crq->wLength)); 1425 set_protocol_stall(udc, ep); 1426 return -1; 1427} 1428 1429static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep) 1430{ 1431 struct usba_request *req; 1432 u32 epstatus; 1433 u32 epctrl; 1434 1435restart: 1436 epstatus = usba_ep_readl(ep, STA); 1437 epctrl = usba_ep_readl(ep, CTL); 1438 1439 DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n", 1440 ep->ep.name, ep->state, epstatus, epctrl); 1441 1442 req = NULL; 1443 if (!list_empty(&ep->queue)) 1444 req = list_entry(ep->queue.next, 1445 struct usba_request, queue); 1446 1447 if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) { 1448 if (req->submitted) 1449 next_fifo_transaction(ep, req); 1450 else 1451 submit_request(ep, req); 1452 1453 if (req->last_transaction) { 1454 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); 1455 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); 1456 } 1457 goto restart; 1458 } 1459 if ((epstatus & epctrl) & USBA_TX_COMPLETE) { 1460 usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE); 1461 1462 switch (ep->state) { 1463 case DATA_STAGE_IN: 1464 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY); 1465 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1466 ep->state = STATUS_STAGE_OUT; 1467 break; 1468 case STATUS_STAGE_ADDR: 1469 /* Activate our new address */ 1470 usba_writel(udc, CTRL, (usba_readl(udc, CTRL) 1471 | USBA_FADDR_EN)); 1472 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1473 ep->state = WAIT_FOR_SETUP; 1474 break; 1475 case STATUS_STAGE_IN: 1476 if (req) { 1477 list_del_init(&req->queue); 1478 request_complete(ep, req, 0); 1479 submit_next_request(ep); 1480 } 1481 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1482 ep->state = WAIT_FOR_SETUP; 1483 break; 1484 case STATUS_STAGE_TEST: 1485 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1486 ep->state = WAIT_FOR_SETUP; 1487 if (do_test_mode(udc)) 1488 set_protocol_stall(udc, ep); 1489 break; 1490 default: 1491 pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, " 1492 "halting endpoint...\n", 1493 ep->ep.name, ep->state); 1494 set_protocol_stall(udc, ep); 1495 break; 1496 } 1497 1498 goto restart; 1499 } 1500 if ((epstatus & epctrl) & USBA_RX_BK_RDY) { 1501 switch (ep->state) { 1502 case STATUS_STAGE_OUT: 1503 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); 1504 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 1505 1506 if (req) { 1507 list_del_init(&req->queue); 1508 request_complete(ep, req, 0); 1509 } 1510 ep->state = WAIT_FOR_SETUP; 1511 break; 1512 1513 case DATA_STAGE_OUT: 1514 receive_data(ep); 1515 break; 1516 1517 default: 1518 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); 1519 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 1520 pr_err("udc: %s: RXRDY: Invalid endpoint state %d, " 1521 "halting endpoint...\n", 1522 ep->ep.name, ep->state); 1523 set_protocol_stall(udc, ep); 1524 break; 1525 } 1526 1527 goto restart; 1528 } 1529 if (epstatus & USBA_RX_SETUP) { 1530 union { 1531 struct usb_ctrlrequest crq; 1532 unsigned long data[2]; 1533 } crq; 1534 unsigned int pkt_len; 1535 int ret; 1536 1537 if (ep->state != WAIT_FOR_SETUP) { 1538 /* 1539 * Didn't expect a SETUP packet at this 1540 * point. Clean up any pending requests (which 1541 * may be successful). 1542 */ 1543 int status = -EPROTO; 1544 1545 /* 1546 * RXRDY and TXCOMP are dropped when SETUP 1547 * packets arrive. Just pretend we received 1548 * the status packet. 1549 */ 1550 if (ep->state == STATUS_STAGE_OUT 1551 || ep->state == STATUS_STAGE_IN) { 1552 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 1553 status = 0; 1554 } 1555 1556 if (req) { 1557 list_del_init(&req->queue); 1558 request_complete(ep, req, status); 1559 } 1560 } 1561 1562 pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA)); 1563 DBG(DBG_HW, "Packet length: %u\n", pkt_len); 1564 if (pkt_len != sizeof(crq)) { 1565 pr_warn("udc: Invalid packet length %u (expected %zu)\n", 1566 pkt_len, sizeof(crq)); 1567 set_protocol_stall(udc, ep); 1568 return; 1569 } 1570 1571 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo); 1572 memcpy_fromio(crq.data, ep->fifo, sizeof(crq)); 1573 1574 /* Free up one bank in the FIFO so that we can 1575 * generate or receive a reply right away. */ 1576 usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP); 1577 1578 /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n", 1579 ep->state, crq.crq.bRequestType, 1580 crq.crq.bRequest); */ 1581 1582 if (crq.crq.bRequestType & USB_DIR_IN) { 1583 /* 1584 * The USB 2.0 spec states that "if wLength is 1585 * zero, there is no data transfer phase." 1586 * However, testusb #14 seems to actually 1587 * expect a data phase even if wLength = 0... 1588 */ 1589 ep->state = DATA_STAGE_IN; 1590 } else { 1591 if (crq.crq.wLength != cpu_to_le16(0)) 1592 ep->state = DATA_STAGE_OUT; 1593 else 1594 ep->state = STATUS_STAGE_IN; 1595 } 1596 1597 ret = -1; 1598 if (ep->index == 0) 1599 ret = handle_ep0_setup(udc, ep, &crq.crq); 1600 else { 1601 spin_unlock(&udc->lock); 1602 ret = udc->driver->setup(&udc->gadget, &crq.crq); 1603 spin_lock(&udc->lock); 1604 } 1605 1606 DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n", 1607 crq.crq.bRequestType, crq.crq.bRequest, 1608 le16_to_cpu(crq.crq.wLength), ep->state, ret); 1609 1610 if (ret < 0) { 1611 /* Let the host know that we failed */ 1612 set_protocol_stall(udc, ep); 1613 } 1614 } 1615} 1616 1617static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep) 1618{ 1619 struct usba_request *req; 1620 u32 epstatus; 1621 u32 epctrl; 1622 1623 epstatus = usba_ep_readl(ep, STA); 1624 epctrl = usba_ep_readl(ep, CTL); 1625 1626 DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus); 1627 1628 while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) { 1629 DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name); 1630 1631 if (list_empty(&ep->queue)) { 1632 dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n"); 1633 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); 1634 return; 1635 } 1636 1637 req = list_entry(ep->queue.next, struct usba_request, queue); 1638 1639 if (req->using_dma) { 1640 /* Send a zero-length packet */ 1641 usba_ep_writel(ep, SET_STA, 1642 USBA_TX_PK_RDY); 1643 usba_ep_writel(ep, CTL_DIS, 1644 USBA_TX_PK_RDY); 1645 list_del_init(&req->queue); 1646 submit_next_request(ep); 1647 request_complete(ep, req, 0); 1648 } else { 1649 if (req->submitted) 1650 next_fifo_transaction(ep, req); 1651 else 1652 submit_request(ep, req); 1653 1654 if (req->last_transaction) { 1655 list_del_init(&req->queue); 1656 submit_next_request(ep); 1657 request_complete(ep, req, 0); 1658 } 1659 } 1660 1661 epstatus = usba_ep_readl(ep, STA); 1662 epctrl = usba_ep_readl(ep, CTL); 1663 } 1664 if ((epstatus & epctrl) & USBA_RX_BK_RDY) { 1665 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name); 1666 receive_data(ep); 1667 } 1668} 1669 1670static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep) 1671{ 1672 struct usba_request *req; 1673 u32 status, control, pending; 1674 1675 status = usba_dma_readl(ep, STATUS); 1676 control = usba_dma_readl(ep, CONTROL); 1677#ifdef CONFIG_USB_GADGET_DEBUG_FS 1678 ep->last_dma_status = status; 1679#endif 1680 pending = status & control; 1681 DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control); 1682 1683 if (status & USBA_DMA_CH_EN) { 1684 dev_err(&udc->pdev->dev, 1685 "DMA_CH_EN is set after transfer is finished!\n"); 1686 dev_err(&udc->pdev->dev, 1687 "status=%#08x, pending=%#08x, control=%#08x\n", 1688 status, pending, control); 1689 1690 /* 1691 * try to pretend nothing happened. We might have to 1692 * do something here... 1693 */ 1694 } 1695 1696 if (list_empty(&ep->queue)) 1697 /* Might happen if a reset comes along at the right moment */ 1698 return; 1699 1700 if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) { 1701 req = list_entry(ep->queue.next, struct usba_request, queue); 1702 usba_update_req(ep, req, status); 1703 1704 list_del_init(&req->queue); 1705 submit_next_request(ep); 1706 request_complete(ep, req, 0); 1707 } 1708} 1709 1710static int start_clock(struct usba_udc *udc); 1711static void stop_clock(struct usba_udc *udc); 1712 1713static irqreturn_t usba_udc_irq(int irq, void *devid) 1714{ 1715 struct usba_udc *udc = devid; 1716 u32 status, int_enb; 1717 u32 dma_status; 1718 u32 ep_status; 1719 1720 spin_lock(&udc->lock); 1721 1722 int_enb = usba_int_enb_get(udc); 1723 status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED); 1724 DBG(DBG_INT, "irq, status=%#08x\n", status); 1725 1726 if (status & USBA_DET_SUSPEND) { 1727 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND|USBA_WAKE_UP); 1728 usba_int_enb_set(udc, USBA_WAKE_UP); 1729 usba_int_enb_clear(udc, USBA_DET_SUSPEND); 1730 udc->suspended = true; 1731 toggle_bias(udc, 0); 1732 udc->bias_pulse_needed = true; 1733 stop_clock(udc); 1734 DBG(DBG_BUS, "Suspend detected\n"); 1735 if (udc->gadget.speed != USB_SPEED_UNKNOWN 1736 && udc->driver && udc->driver->suspend) { 1737 spin_unlock(&udc->lock); 1738 udc->driver->suspend(&udc->gadget); 1739 spin_lock(&udc->lock); 1740 } 1741 } 1742 1743 if (status & USBA_WAKE_UP) { 1744 start_clock(udc); 1745 toggle_bias(udc, 1); 1746 usba_writel(udc, INT_CLR, USBA_WAKE_UP); 1747 DBG(DBG_BUS, "Wake Up CPU detected\n"); 1748 } 1749 1750 if (status & USBA_END_OF_RESUME) { 1751 udc->suspended = false; 1752 usba_writel(udc, INT_CLR, USBA_END_OF_RESUME); 1753 usba_int_enb_clear(udc, USBA_WAKE_UP); 1754 usba_int_enb_set(udc, USBA_DET_SUSPEND); 1755 generate_bias_pulse(udc); 1756 DBG(DBG_BUS, "Resume detected\n"); 1757 if (udc->gadget.speed != USB_SPEED_UNKNOWN 1758 && udc->driver && udc->driver->resume) { 1759 spin_unlock(&udc->lock); 1760 udc->driver->resume(&udc->gadget); 1761 spin_lock(&udc->lock); 1762 } 1763 } 1764 1765 dma_status = USBA_BFEXT(DMA_INT, status); 1766 if (dma_status) { 1767 int i; 1768 1769 usba_int_enb_set(udc, USBA_DET_SUSPEND); 1770 1771 for (i = 1; i <= USBA_NR_DMAS; i++) 1772 if (dma_status & (1 << i)) 1773 usba_dma_irq(udc, &udc->usba_ep[i]); 1774 } 1775 1776 ep_status = USBA_BFEXT(EPT_INT, status); 1777 if (ep_status) { 1778 int i; 1779 1780 usba_int_enb_set(udc, USBA_DET_SUSPEND); 1781 1782 for (i = 0; i < udc->num_ep; i++) 1783 if (ep_status & (1 << i)) { 1784 if (ep_is_control(&udc->usba_ep[i])) 1785 usba_control_irq(udc, &udc->usba_ep[i]); 1786 else 1787 usba_ep_irq(udc, &udc->usba_ep[i]); 1788 } 1789 } 1790 1791 if (status & USBA_END_OF_RESET) { 1792 struct usba_ep *ep0, *ep; 1793 int i; 1794 1795 usba_writel(udc, INT_CLR, 1796 USBA_END_OF_RESET|USBA_END_OF_RESUME 1797 |USBA_DET_SUSPEND|USBA_WAKE_UP); 1798 generate_bias_pulse(udc); 1799 reset_all_endpoints(udc); 1800 1801 if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) { 1802 udc->gadget.speed = USB_SPEED_UNKNOWN; 1803 spin_unlock(&udc->lock); 1804 usb_gadget_udc_reset(&udc->gadget, udc->driver); 1805 spin_lock(&udc->lock); 1806 } 1807 1808 if (status & USBA_HIGH_SPEED) 1809 udc->gadget.speed = USB_SPEED_HIGH; 1810 else 1811 udc->gadget.speed = USB_SPEED_FULL; 1812 DBG(DBG_BUS, "%s bus reset detected\n", 1813 usb_speed_string(udc->gadget.speed)); 1814 1815 ep0 = &udc->usba_ep[0]; 1816 ep0->ep.desc = &usba_ep0_desc; 1817 ep0->state = WAIT_FOR_SETUP; 1818 usba_ep_writel(ep0, CFG, 1819 (USBA_BF(EPT_SIZE, EP0_EPT_SIZE) 1820 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL) 1821 | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE))); 1822 usba_ep_writel(ep0, CTL_ENB, 1823 USBA_EPT_ENABLE | USBA_RX_SETUP); 1824 1825 /* If we get reset while suspended... */ 1826 udc->suspended = false; 1827 usba_int_enb_clear(udc, USBA_WAKE_UP); 1828 1829 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1) | 1830 USBA_DET_SUSPEND | USBA_END_OF_RESUME); 1831 1832 /* 1833 * Unclear why we hit this irregularly, e.g. in usbtest, 1834 * but it's clearly harmless... 1835 */ 1836 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED)) 1837 dev_err(&udc->pdev->dev, 1838 "ODD: EP0 configuration is invalid!\n"); 1839 1840 /* Preallocate other endpoints */ 1841 for (i = 1; i < udc->num_ep; i++) { 1842 ep = &udc->usba_ep[i]; 1843 if (ep->ep.claimed) { 1844 usba_ep_writel(ep, CFG, ep->ept_cfg); 1845 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) 1846 dev_err(&udc->pdev->dev, 1847 "ODD: EP%d configuration is invalid!\n", i); 1848 } 1849 } 1850 } 1851 1852 spin_unlock(&udc->lock); 1853 1854 return IRQ_HANDLED; 1855} 1856 1857static int start_clock(struct usba_udc *udc) 1858{ 1859 int ret; 1860 1861 if (udc->clocked) 1862 return 0; 1863 1864 pm_stay_awake(&udc->pdev->dev); 1865 1866 ret = clk_prepare_enable(udc->pclk); 1867 if (ret) 1868 return ret; 1869 ret = clk_prepare_enable(udc->hclk); 1870 if (ret) { 1871 clk_disable_unprepare(udc->pclk); 1872 return ret; 1873 } 1874 1875 udc->clocked = true; 1876 return 0; 1877} 1878 1879static void stop_clock(struct usba_udc *udc) 1880{ 1881 if (!udc->clocked) 1882 return; 1883 1884 clk_disable_unprepare(udc->hclk); 1885 clk_disable_unprepare(udc->pclk); 1886 1887 udc->clocked = false; 1888 1889 pm_relax(&udc->pdev->dev); 1890} 1891 1892static int usba_start(struct usba_udc *udc) 1893{ 1894 unsigned long flags; 1895 int ret; 1896 1897 ret = start_clock(udc); 1898 if (ret) 1899 return ret; 1900 1901 if (udc->suspended) 1902 return 0; 1903 1904 spin_lock_irqsave(&udc->lock, flags); 1905 toggle_bias(udc, 1); 1906 usba_writel(udc, CTRL, USBA_ENABLE_MASK); 1907 /* Clear all requested and pending interrupts... */ 1908 usba_writel(udc, INT_ENB, 0); 1909 udc->int_enb_cache = 0; 1910 usba_writel(udc, INT_CLR, 1911 USBA_END_OF_RESET|USBA_END_OF_RESUME 1912 |USBA_DET_SUSPEND|USBA_WAKE_UP); 1913 /* ...and enable just 'reset' IRQ to get us started */ 1914 usba_int_enb_set(udc, USBA_END_OF_RESET); 1915 spin_unlock_irqrestore(&udc->lock, flags); 1916 1917 return 0; 1918} 1919 1920static void usba_stop(struct usba_udc *udc) 1921{ 1922 unsigned long flags; 1923 1924 if (udc->suspended) 1925 return; 1926 1927 spin_lock_irqsave(&udc->lock, flags); 1928 udc->gadget.speed = USB_SPEED_UNKNOWN; 1929 reset_all_endpoints(udc); 1930 1931 /* This will also disable the DP pullup */ 1932 toggle_bias(udc, 0); 1933 usba_writel(udc, CTRL, USBA_DISABLE_MASK); 1934 spin_unlock_irqrestore(&udc->lock, flags); 1935 1936 stop_clock(udc); 1937} 1938 1939static irqreturn_t usba_vbus_irq_thread(int irq, void *devid) 1940{ 1941 struct usba_udc *udc = devid; 1942 int vbus; 1943 1944 /* debounce */ 1945 udelay(10); 1946 1947 mutex_lock(&udc->vbus_mutex); 1948 1949 vbus = vbus_is_present(udc); 1950 if (vbus != udc->vbus_prev) { 1951 if (vbus) { 1952 usba_start(udc); 1953 } else { 1954 udc->suspended = false; 1955 if (udc->driver->disconnect) 1956 udc->driver->disconnect(&udc->gadget); 1957 1958 usba_stop(udc); 1959 } 1960 udc->vbus_prev = vbus; 1961 } 1962 1963 mutex_unlock(&udc->vbus_mutex); 1964 return IRQ_HANDLED; 1965} 1966 1967static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on) 1968{ 1969 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget); 1970 unsigned long flags; 1971 u32 ctrl; 1972 1973 spin_lock_irqsave(&udc->lock, flags); 1974 ctrl = usba_readl(udc, CTRL); 1975 if (is_on) 1976 ctrl &= ~USBA_DETACH; 1977 else 1978 ctrl |= USBA_DETACH; 1979 usba_writel(udc, CTRL, ctrl); 1980 spin_unlock_irqrestore(&udc->lock, flags); 1981 1982 return 0; 1983} 1984 1985static int atmel_usba_start(struct usb_gadget *gadget, 1986 struct usb_gadget_driver *driver) 1987{ 1988 int ret; 1989 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget); 1990 unsigned long flags; 1991 1992 spin_lock_irqsave(&udc->lock, flags); 1993 udc->devstatus = 1 << USB_DEVICE_SELF_POWERED; 1994 udc->driver = driver; 1995 spin_unlock_irqrestore(&udc->lock, flags); 1996 1997 mutex_lock(&udc->vbus_mutex); 1998 1999 if (udc->vbus_pin) 2000 enable_irq(gpiod_to_irq(udc->vbus_pin)); 2001 2002 /* If Vbus is present, enable the controller and wait for reset */ 2003 udc->vbus_prev = vbus_is_present(udc); 2004 if (udc->vbus_prev) { 2005 ret = usba_start(udc); 2006 if (ret) 2007 goto err; 2008 } 2009 2010 mutex_unlock(&udc->vbus_mutex); 2011 return 0; 2012 2013err: 2014 if (udc->vbus_pin) 2015 disable_irq(gpiod_to_irq(udc->vbus_pin)); 2016 2017 mutex_unlock(&udc->vbus_mutex); 2018 2019 spin_lock_irqsave(&udc->lock, flags); 2020 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED); 2021 udc->driver = NULL; 2022 spin_unlock_irqrestore(&udc->lock, flags); 2023 return ret; 2024} 2025 2026static int atmel_usba_stop(struct usb_gadget *gadget) 2027{ 2028 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget); 2029 2030 if (udc->vbus_pin) 2031 disable_irq(gpiod_to_irq(udc->vbus_pin)); 2032 2033 udc->suspended = false; 2034 usba_stop(udc); 2035 2036 udc->driver = NULL; 2037 2038 return 0; 2039} 2040 2041static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on) 2042{ 2043 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 2044 is_on ? AT91_PMC_BIASEN : 0); 2045} 2046 2047static void at91sam9g45_pulse_bias(struct usba_udc *udc) 2048{ 2049 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0); 2050 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 2051 AT91_PMC_BIASEN); 2052} 2053 2054static const struct usba_udc_errata at91sam9rl_errata = { 2055 .toggle_bias = at91sam9rl_toggle_bias, 2056}; 2057 2058static const struct usba_udc_errata at91sam9g45_errata = { 2059 .pulse_bias = at91sam9g45_pulse_bias, 2060}; 2061 2062static const struct usba_ep_config ep_config_sam9[] = { 2063 { .nr_banks = 1 }, /* ep 0 */ 2064 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */ 2065 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */ 2066 { .nr_banks = 3, .can_dma = 1 }, /* ep 3 */ 2067 { .nr_banks = 3, .can_dma = 1 }, /* ep 4 */ 2068 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */ 2069 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */ 2070}; 2071 2072static const struct usba_ep_config ep_config_sama5[] = { 2073 { .nr_banks = 1 }, /* ep 0 */ 2074 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */ 2075 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */ 2076 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 3 */ 2077 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 4 */ 2078 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */ 2079 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */ 2080 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 7 */ 2081 { .nr_banks = 2, .can_isoc = 1 }, /* ep 8 */ 2082 { .nr_banks = 2, .can_isoc = 1 }, /* ep 9 */ 2083 { .nr_banks = 2, .can_isoc = 1 }, /* ep 10 */ 2084 { .nr_banks = 2, .can_isoc = 1 }, /* ep 11 */ 2085 { .nr_banks = 2, .can_isoc = 1 }, /* ep 12 */ 2086 { .nr_banks = 2, .can_isoc = 1 }, /* ep 13 */ 2087 { .nr_banks = 2, .can_isoc = 1 }, /* ep 14 */ 2088 { .nr_banks = 2, .can_isoc = 1 }, /* ep 15 */ 2089}; 2090 2091static const struct usba_udc_config udc_at91sam9rl_cfg = { 2092 .errata = &at91sam9rl_errata, 2093 .config = ep_config_sam9, 2094 .num_ep = ARRAY_SIZE(ep_config_sam9), 2095 .ep_prealloc = true, 2096}; 2097 2098static const struct usba_udc_config udc_at91sam9g45_cfg = { 2099 .errata = &at91sam9g45_errata, 2100 .config = ep_config_sam9, 2101 .num_ep = ARRAY_SIZE(ep_config_sam9), 2102 .ep_prealloc = true, 2103}; 2104 2105static const struct usba_udc_config udc_sama5d3_cfg = { 2106 .config = ep_config_sama5, 2107 .num_ep = ARRAY_SIZE(ep_config_sama5), 2108 .ep_prealloc = true, 2109}; 2110 2111static const struct usba_udc_config udc_sam9x60_cfg = { 2112 .num_ep = ARRAY_SIZE(ep_config_sam9), 2113 .config = ep_config_sam9, 2114 .ep_prealloc = false, 2115}; 2116 2117static const struct of_device_id atmel_udc_dt_ids[] = { 2118 { .compatible = "atmel,at91sam9rl-udc", .data = &udc_at91sam9rl_cfg }, 2119 { .compatible = "atmel,at91sam9g45-udc", .data = &udc_at91sam9g45_cfg }, 2120 { .compatible = "atmel,sama5d3-udc", .data = &udc_sama5d3_cfg }, 2121 { .compatible = "microchip,sam9x60-udc", .data = &udc_sam9x60_cfg }, 2122 { /* sentinel */ } 2123}; 2124 2125MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids); 2126 2127static const struct of_device_id atmel_pmc_dt_ids[] = { 2128 { .compatible = "atmel,at91sam9g45-pmc" }, 2129 { .compatible = "atmel,at91sam9rl-pmc" }, 2130 { .compatible = "atmel,at91sam9x5-pmc" }, 2131 { /* sentinel */ } 2132}; 2133 2134static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev, 2135 struct usba_udc *udc) 2136{ 2137 struct device_node *np = pdev->dev.of_node; 2138 const struct of_device_id *match; 2139 struct device_node *pp; 2140 int i, ret; 2141 struct usba_ep *eps, *ep; 2142 const struct usba_udc_config *udc_config; 2143 2144 match = of_match_node(atmel_udc_dt_ids, np); 2145 if (!match) 2146 return ERR_PTR(-EINVAL); 2147 2148 udc_config = match->data; 2149 udc->ep_prealloc = udc_config->ep_prealloc; 2150 udc->errata = udc_config->errata; 2151 if (udc->errata) { 2152 pp = of_find_matching_node_and_match(NULL, atmel_pmc_dt_ids, 2153 NULL); 2154 if (!pp) 2155 return ERR_PTR(-ENODEV); 2156 2157 udc->pmc = syscon_node_to_regmap(pp); 2158 of_node_put(pp); 2159 if (IS_ERR(udc->pmc)) 2160 return ERR_CAST(udc->pmc); 2161 } 2162 2163 udc->num_ep = 0; 2164 2165 udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus", 2166 GPIOD_IN); 2167 if (IS_ERR(udc->vbus_pin)) 2168 return ERR_CAST(udc->vbus_pin); 2169 2170 if (fifo_mode == 0) { 2171 udc->num_ep = udc_config->num_ep; 2172 } else { 2173 udc->num_ep = usba_config_fifo_table(udc); 2174 } 2175 2176 eps = devm_kcalloc(&pdev->dev, udc->num_ep, sizeof(struct usba_ep), 2177 GFP_KERNEL); 2178 if (!eps) 2179 return ERR_PTR(-ENOMEM); 2180 2181 udc->gadget.ep0 = &eps[0].ep; 2182 2183 INIT_LIST_HEAD(&eps[0].ep.ep_list); 2184 2185 i = 0; 2186 while (i < udc->num_ep) { 2187 const struct usba_ep_config *ep_cfg = &udc_config->config[i]; 2188 2189 ep = &eps[i]; 2190 2191 ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : i; 2192 2193 /* Only the first EP is 64 bytes */ 2194 if (ep->index == 0) 2195 ep->fifo_size = 64; 2196 else 2197 ep->fifo_size = 1024; 2198 2199 if (fifo_mode) { 2200 if (ep->fifo_size < udc->fifo_cfg[i].fifo_size) 2201 dev_warn(&pdev->dev, 2202 "Using default max fifo-size value\n"); 2203 else 2204 ep->fifo_size = udc->fifo_cfg[i].fifo_size; 2205 } 2206 2207 ep->nr_banks = ep_cfg->nr_banks; 2208 if (fifo_mode) { 2209 if (ep->nr_banks < udc->fifo_cfg[i].nr_banks) 2210 dev_warn(&pdev->dev, 2211 "Using default max nb-banks value\n"); 2212 else 2213 ep->nr_banks = udc->fifo_cfg[i].nr_banks; 2214 } 2215 2216 ep->can_dma = ep_cfg->can_dma; 2217 ep->can_isoc = ep_cfg->can_isoc; 2218 2219 sprintf(ep->name, "ep%d", ep->index); 2220 ep->ep.name = ep->name; 2221 2222 ep->ep_regs = udc->regs + USBA_EPT_BASE(i); 2223 ep->dma_regs = udc->regs + USBA_DMA_BASE(i); 2224 ep->fifo = udc->fifo + USBA_FIFO_BASE(i); 2225 ep->ep.ops = &usba_ep_ops; 2226 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size); 2227 ep->udc = udc; 2228 INIT_LIST_HEAD(&ep->queue); 2229 2230 if (ep->index == 0) { 2231 ep->ep.caps.type_control = true; 2232 } else { 2233 ep->ep.caps.type_iso = ep->can_isoc; 2234 ep->ep.caps.type_bulk = true; 2235 ep->ep.caps.type_int = true; 2236 } 2237 2238 ep->ep.caps.dir_in = true; 2239 ep->ep.caps.dir_out = true; 2240 2241 if (fifo_mode != 0) { 2242 /* 2243 * Generate ept_cfg based on FIFO size and 2244 * banks number 2245 */ 2246 if (ep->fifo_size <= 8) 2247 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8); 2248 else 2249 /* LSB is bit 1, not 0 */ 2250 ep->ept_cfg = 2251 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3); 2252 2253 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks); 2254 } 2255 2256 if (i) 2257 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 2258 2259 i++; 2260 } 2261 2262 if (i == 0) { 2263 dev_err(&pdev->dev, "of_probe: no endpoint specified\n"); 2264 ret = -EINVAL; 2265 goto err; 2266 } 2267 2268 return eps; 2269err: 2270 return ERR_PTR(ret); 2271} 2272 2273static int usba_udc_probe(struct platform_device *pdev) 2274{ 2275 struct resource *res; 2276 struct clk *pclk, *hclk; 2277 struct usba_udc *udc; 2278 int irq, ret, i; 2279 2280 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); 2281 if (!udc) 2282 return -ENOMEM; 2283 2284 udc->gadget = usba_gadget_template; 2285 INIT_LIST_HEAD(&udc->gadget.ep_list); 2286 2287 udc->regs = devm_platform_get_and_ioremap_resource(pdev, CTRL_IOMEM_ID, &res); 2288 if (IS_ERR(udc->regs)) 2289 return PTR_ERR(udc->regs); 2290 dev_info(&pdev->dev, "MMIO registers at %pR mapped at %p\n", 2291 res, udc->regs); 2292 2293 udc->fifo = devm_platform_get_and_ioremap_resource(pdev, FIFO_IOMEM_ID, &res); 2294 if (IS_ERR(udc->fifo)) 2295 return PTR_ERR(udc->fifo); 2296 dev_info(&pdev->dev, "FIFO at %pR mapped at %p\n", res, udc->fifo); 2297 2298 irq = platform_get_irq(pdev, 0); 2299 if (irq < 0) 2300 return irq; 2301 2302 pclk = devm_clk_get(&pdev->dev, "pclk"); 2303 if (IS_ERR(pclk)) 2304 return PTR_ERR(pclk); 2305 hclk = devm_clk_get(&pdev->dev, "hclk"); 2306 if (IS_ERR(hclk)) 2307 return PTR_ERR(hclk); 2308 2309 spin_lock_init(&udc->lock); 2310 mutex_init(&udc->vbus_mutex); 2311 udc->pdev = pdev; 2312 udc->pclk = pclk; 2313 udc->hclk = hclk; 2314 2315 platform_set_drvdata(pdev, udc); 2316 2317 /* Make sure we start from a clean slate */ 2318 ret = clk_prepare_enable(pclk); 2319 if (ret) { 2320 dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n"); 2321 return ret; 2322 } 2323 2324 usba_writel(udc, CTRL, USBA_DISABLE_MASK); 2325 clk_disable_unprepare(pclk); 2326 2327 udc->usba_ep = atmel_udc_of_init(pdev, udc); 2328 2329 toggle_bias(udc, 0); 2330 2331 if (IS_ERR(udc->usba_ep)) 2332 return PTR_ERR(udc->usba_ep); 2333 2334 ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0, 2335 "atmel_usba_udc", udc); 2336 if (ret) { 2337 dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n", 2338 irq, ret); 2339 return ret; 2340 } 2341 udc->irq = irq; 2342 2343 if (udc->vbus_pin) { 2344 irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN); 2345 ret = devm_request_threaded_irq(&pdev->dev, 2346 gpiod_to_irq(udc->vbus_pin), NULL, 2347 usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS, 2348 "atmel_usba_udc", udc); 2349 if (ret) { 2350 udc->vbus_pin = NULL; 2351 dev_warn(&udc->pdev->dev, 2352 "failed to request vbus irq; " 2353 "assuming always on\n"); 2354 } 2355 } 2356 2357 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2358 if (ret) 2359 return ret; 2360 device_init_wakeup(&pdev->dev, 1); 2361 2362 usba_init_debugfs(udc); 2363 for (i = 1; i < udc->num_ep; i++) 2364 usba_ep_init_debugfs(udc, &udc->usba_ep[i]); 2365 2366 return 0; 2367} 2368 2369static void usba_udc_remove(struct platform_device *pdev) 2370{ 2371 struct usba_udc *udc; 2372 int i; 2373 2374 udc = platform_get_drvdata(pdev); 2375 2376 device_init_wakeup(&pdev->dev, 0); 2377 usb_del_gadget_udc(&udc->gadget); 2378 2379 for (i = 1; i < udc->num_ep; i++) 2380 usba_ep_cleanup_debugfs(&udc->usba_ep[i]); 2381 usba_cleanup_debugfs(udc); 2382} 2383 2384#ifdef CONFIG_PM_SLEEP 2385static int usba_udc_suspend(struct device *dev) 2386{ 2387 struct usba_udc *udc = dev_get_drvdata(dev); 2388 2389 /* Not started */ 2390 if (!udc->driver) 2391 return 0; 2392 2393 mutex_lock(&udc->vbus_mutex); 2394 2395 if (!device_may_wakeup(dev)) { 2396 udc->suspended = false; 2397 usba_stop(udc); 2398 goto out; 2399 } 2400 2401 /* 2402 * Device may wake up. We stay clocked if we failed 2403 * to request vbus irq, assuming always on. 2404 */ 2405 if (udc->vbus_pin) { 2406 /* FIXME: right to stop here...??? */ 2407 usba_stop(udc); 2408 enable_irq_wake(gpiod_to_irq(udc->vbus_pin)); 2409 } 2410 2411 enable_irq_wake(udc->irq); 2412 2413out: 2414 mutex_unlock(&udc->vbus_mutex); 2415 return 0; 2416} 2417 2418static int usba_udc_resume(struct device *dev) 2419{ 2420 struct usba_udc *udc = dev_get_drvdata(dev); 2421 2422 /* Not started */ 2423 if (!udc->driver) 2424 return 0; 2425 2426 if (device_may_wakeup(dev)) { 2427 if (udc->vbus_pin) 2428 disable_irq_wake(gpiod_to_irq(udc->vbus_pin)); 2429 2430 disable_irq_wake(udc->irq); 2431 } 2432 2433 /* If Vbus is present, enable the controller and wait for reset */ 2434 mutex_lock(&udc->vbus_mutex); 2435 udc->vbus_prev = vbus_is_present(udc); 2436 if (udc->vbus_prev) 2437 usba_start(udc); 2438 mutex_unlock(&udc->vbus_mutex); 2439 2440 return 0; 2441} 2442#endif 2443 2444static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume); 2445 2446static struct platform_driver udc_driver = { 2447 .probe = usba_udc_probe, 2448 .remove_new = usba_udc_remove, 2449 .driver = { 2450 .name = "atmel_usba_udc", 2451 .pm = &usba_udc_pm_ops, 2452 .of_match_table = atmel_udc_dt_ids, 2453 }, 2454}; 2455module_platform_driver(udc_driver); 2456 2457MODULE_DESCRIPTION("Atmel USBA UDC driver"); 2458MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2459MODULE_LICENSE("GPL"); 2460MODULE_ALIAS("platform:atmel_usba_udc"); 2461