1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * core.h - DesignWare USB3 DRD Core Header 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11#ifndef __DRIVERS_USB_DWC3_CORE_H 12#define __DRIVERS_USB_DWC3_CORE_H 13 14#include <linux/device.h> 15#include <linux/spinlock.h> 16#include <linux/mutex.h> 17#include <linux/ioport.h> 18#include <linux/list.h> 19#include <linux/bitops.h> 20#include <linux/dma-mapping.h> 21#include <linux/mm.h> 22#include <linux/debugfs.h> 23#include <linux/wait.h> 24#include <linux/workqueue.h> 25 26#include <linux/usb/ch9.h> 27#include <linux/usb/gadget.h> 28#include <linux/usb/otg.h> 29#include <linux/usb/role.h> 30#include <linux/ulpi/interface.h> 31 32#include <linux/phy/phy.h> 33 34#include <linux/power_supply.h> 35 36#define DWC3_MSG_MAX 500 37 38/* Global constants */ 39#define DWC3_PULL_UP_TIMEOUT 500 /* ms */ 40#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ 41#define DWC3_EP0_SETUP_SIZE 512 42#define DWC3_ENDPOINTS_NUM 32 43#define DWC3_XHCI_RESOURCES_NUM 2 44#define DWC3_ISOC_MAX_RETRIES 5 45 46#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ 47#define DWC3_EVENT_BUFFERS_SIZE 4096 48#define DWC3_EVENT_TYPE_MASK 0xfe 49 50#define DWC3_EVENT_TYPE_DEV 0 51#define DWC3_EVENT_TYPE_CARKIT 3 52#define DWC3_EVENT_TYPE_I2C 4 53 54#define DWC3_DEVICE_EVENT_DISCONNECT 0 55#define DWC3_DEVICE_EVENT_RESET 1 56#define DWC3_DEVICE_EVENT_CONNECT_DONE 2 57#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 58#define DWC3_DEVICE_EVENT_WAKEUP 4 59#define DWC3_DEVICE_EVENT_HIBER_REQ 5 60#define DWC3_DEVICE_EVENT_SUSPEND 6 61#define DWC3_DEVICE_EVENT_SOF 7 62#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 63#define DWC3_DEVICE_EVENT_CMD_CMPL 10 64#define DWC3_DEVICE_EVENT_OVERFLOW 11 65 66/* Controller's role while using the OTG block */ 67#define DWC3_OTG_ROLE_IDLE 0 68#define DWC3_OTG_ROLE_HOST 1 69#define DWC3_OTG_ROLE_DEVICE 2 70 71#define DWC3_GEVNTCOUNT_MASK 0xfffc 72#define DWC3_GEVNTCOUNT_EHB BIT(31) 73#define DWC3_GSNPSID_MASK 0xffff0000 74#define DWC3_GSNPSREV_MASK 0xffff 75#define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16) 76 77/* DWC3 registers memory space boundries */ 78#define DWC3_XHCI_REGS_START 0x0 79#define DWC3_XHCI_REGS_END 0x7fff 80#define DWC3_GLOBALS_REGS_START 0xc100 81#define DWC3_GLOBALS_REGS_END 0xc6ff 82#define DWC3_DEVICE_REGS_START 0xc700 83#define DWC3_DEVICE_REGS_END 0xcbff 84#define DWC3_OTG_REGS_START 0xcc00 85#define DWC3_OTG_REGS_END 0xccff 86 87#define DWC3_RTK_RTD_GLOBALS_REGS_START 0x8100 88 89/* Global Registers */ 90#define DWC3_GSBUSCFG0 0xc100 91#define DWC3_GSBUSCFG1 0xc104 92#define DWC3_GTXTHRCFG 0xc108 93#define DWC3_GRXTHRCFG 0xc10c 94#define DWC3_GCTL 0xc110 95#define DWC3_GEVTEN 0xc114 96#define DWC3_GSTS 0xc118 97#define DWC3_GUCTL1 0xc11c 98#define DWC3_GSNPSID 0xc120 99#define DWC3_GGPIO 0xc124 100#define DWC3_GUID 0xc128 101#define DWC3_GUCTL 0xc12c 102#define DWC3_GBUSERRADDR0 0xc130 103#define DWC3_GBUSERRADDR1 0xc134 104#define DWC3_GPRTBIMAP0 0xc138 105#define DWC3_GPRTBIMAP1 0xc13c 106#define DWC3_GHWPARAMS0 0xc140 107#define DWC3_GHWPARAMS1 0xc144 108#define DWC3_GHWPARAMS2 0xc148 109#define DWC3_GHWPARAMS3 0xc14c 110#define DWC3_GHWPARAMS4 0xc150 111#define DWC3_GHWPARAMS5 0xc154 112#define DWC3_GHWPARAMS6 0xc158 113#define DWC3_GHWPARAMS7 0xc15c 114#define DWC3_GDBGFIFOSPACE 0xc160 115#define DWC3_GDBGLTSSM 0xc164 116#define DWC3_GDBGBMU 0xc16c 117#define DWC3_GDBGLSPMUX 0xc170 118#define DWC3_GDBGLSP 0xc174 119#define DWC3_GDBGEPINFO0 0xc178 120#define DWC3_GDBGEPINFO1 0xc17c 121#define DWC3_GPRTBIMAP_HS0 0xc180 122#define DWC3_GPRTBIMAP_HS1 0xc184 123#define DWC3_GPRTBIMAP_FS0 0xc188 124#define DWC3_GPRTBIMAP_FS1 0xc18c 125#define DWC3_GUCTL2 0xc19c 126 127#define DWC3_VER_NUMBER 0xc1a0 128#define DWC3_VER_TYPE 0xc1a4 129 130#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 131#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) 132 133#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) 134 135#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 136 137#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) 138#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) 139 140#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) 141#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) 142#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) 143#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) 144 145#define DWC3_GHWPARAMS8 0xc600 146#define DWC3_GUCTL3 0xc60c 147#define DWC3_GFLADJ 0xc630 148#define DWC3_GHWPARAMS9 0xc6e0 149 150/* Device Registers */ 151#define DWC3_DCFG 0xc700 152#define DWC3_DCTL 0xc704 153#define DWC3_DEVTEN 0xc708 154#define DWC3_DSTS 0xc70c 155#define DWC3_DGCMDPAR 0xc710 156#define DWC3_DGCMD 0xc714 157#define DWC3_DALEPENA 0xc720 158#define DWC3_DCFG1 0xc740 /* DWC_usb32 only */ 159 160#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) 161#define DWC3_DEPCMDPAR2 0x00 162#define DWC3_DEPCMDPAR1 0x04 163#define DWC3_DEPCMDPAR0 0x08 164#define DWC3_DEPCMD 0x0c 165 166#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) 167 168/* OTG Registers */ 169#define DWC3_OCFG 0xcc00 170#define DWC3_OCTL 0xcc04 171#define DWC3_OEVT 0xcc08 172#define DWC3_OEVTEN 0xcc0C 173#define DWC3_OSTS 0xcc10 174 175#define DWC3_LLUCTL 0xd024 176 177/* Bit fields */ 178 179/* Global SoC Bus Configuration INCRx Register 0 */ 180#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ 181#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ 182#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ 183#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ 184#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ 185#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ 186#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ 187#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ 188#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff 189 190/* Global Debug LSP MUX Select */ 191#define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */ 192#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff) 193#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4) 194#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf) 195 196/* Global Debug Queue/FIFO Space Available Register */ 197#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) 198#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) 199#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) 200 201#define DWC3_TXFIFO 0 202#define DWC3_RXFIFO 1 203#define DWC3_TXREQQ 2 204#define DWC3_RXREQQ 3 205#define DWC3_RXINFOQ 4 206#define DWC3_PSTATQ 5 207#define DWC3_DESCFETCHQ 6 208#define DWC3_EVENTQ 7 209#define DWC3_AUXEVENTQ 8 210 211/* Global RX Threshold Configuration Register */ 212#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) 213#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) 214#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29) 215 216/* Global TX Threshold Configuration Register */ 217#define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16) 218#define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24) 219#define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29) 220 221/* Global RX Threshold Configuration Register for DWC_usb31 only */ 222#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16) 223#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21) 224#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26) 225#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15) 226#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 227#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10) 228#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 229#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f) 230 231/* Global TX Threshold Configuration Register for DWC_usb31 only */ 232#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16) 233#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21) 234#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26) 235#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15) 236#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13) 237#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10) 238#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5) 239#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f) 240 241/* Global Configuration Register */ 242#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 243#define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19) 244#define DWC3_GCTL_U2RSTECN BIT(16) 245#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 246#define DWC3_GCTL_CLK_BUS (0) 247#define DWC3_GCTL_CLK_PIPE (1) 248#define DWC3_GCTL_CLK_PIPEHALF (2) 249#define DWC3_GCTL_CLK_MASK (3) 250 251#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 252#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 253#define DWC3_GCTL_PRTCAP_HOST 1 254#define DWC3_GCTL_PRTCAP_DEVICE 2 255#define DWC3_GCTL_PRTCAP_OTG 3 256 257#define DWC3_GCTL_CORESOFTRESET BIT(11) 258#define DWC3_GCTL_SOFITPSYNC BIT(10) 259#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 260#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 261#define DWC3_GCTL_DISSCRAMBLE BIT(3) 262#define DWC3_GCTL_U2EXIT_LFPS BIT(2) 263#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) 264#define DWC3_GCTL_DSBLCLKGTNG BIT(0) 265 266/* Global User Control 1 Register */ 267#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) 268#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) 269#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) 270#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) 271#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) 272#define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16) 273#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10) 274 275/* Global Status Register */ 276#define DWC3_GSTS_OTG_IP BIT(10) 277#define DWC3_GSTS_BC_IP BIT(9) 278#define DWC3_GSTS_ADP_IP BIT(8) 279#define DWC3_GSTS_HOST_IP BIT(7) 280#define DWC3_GSTS_DEVICE_IP BIT(6) 281#define DWC3_GSTS_CSR_TIMEOUT BIT(5) 282#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4) 283#define DWC3_GSTS_CURMOD(n) ((n) & 0x3) 284#define DWC3_GSTS_CURMOD_DEVICE 0 285#define DWC3_GSTS_CURMOD_HOST 1 286 287/* Global USB2 PHY Configuration Register */ 288#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31) 289#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30) 290#define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17) 291#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6) 292#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4) 293#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8) 294#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) 295#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) 296#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) 297#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) 298#define USBTRDTIM_UTMI_8_BIT 9 299#define USBTRDTIM_UTMI_16_BIT 5 300#define UTMI_PHYIF_16_BIT 1 301#define UTMI_PHYIF_8_BIT 0 302 303/* Global USB2 PHY Vendor Control Register */ 304#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25) 305#define DWC3_GUSB2PHYACC_DONE BIT(24) 306#define DWC3_GUSB2PHYACC_BUSY BIT(23) 307#define DWC3_GUSB2PHYACC_WRITE BIT(22) 308#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) 309#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) 310#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) 311 312/* Global USB3 PIPE Control Register */ 313#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31) 314#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29) 315#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28) 316#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27) 317#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24) 318#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) 319#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) 320#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) 321#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18) 322#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17) 323#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9) 324#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8) 325#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) 326#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) 327 328/* Global TX Fifo Size Register */ 329#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */ 330#define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 331#define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff) 332#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 333 334/* Global RX Fifo Size Register */ 335#define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */ 336#define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff) 337 338/* Global Event Size Registers */ 339#define DWC3_GEVNTSIZ_INTMASK BIT(31) 340#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) 341 342/* Global HWPARAMS0 Register */ 343#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) 344#define DWC3_GHWPARAMS0_MODE_GADGET 0 345#define DWC3_GHWPARAMS0_MODE_HOST 1 346#define DWC3_GHWPARAMS0_MODE_DRD 2 347#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) 348#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) 349#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) 350#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) 351#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) 352 353/* Global HWPARAMS1 Register */ 354#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 355#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 356#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 357#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 358#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) 359#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) 360#define DWC3_GHWPARAMS1_ENDBC BIT(31) 361 362/* Global HWPARAMS3 Register */ 363#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) 364#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 365#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 366#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ 367#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) 368#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 369#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 370#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 371#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 372#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) 373#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 374#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 375 376/* Global HWPARAMS4 Register */ 377#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) 378#define DWC3_MAX_HIBER_SCRATCHBUFS 15 379 380/* Global HWPARAMS6 Register */ 381#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14) 382#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13) 383#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12) 384#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11) 385#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10) 386#define DWC3_GHWPARAMS6_EN_FPGA BIT(7) 387 388/* DWC_usb32 only */ 389#define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8)) 390 391/* Global HWPARAMS7 Register */ 392#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) 393#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) 394 395/* Global HWPARAMS9 Register */ 396#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0) 397#define DWC3_GHWPARAMS9_DEV_MST BIT(1) 398 399/* Global Frame Length Adjustment Register */ 400#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) 401#define DWC3_GFLADJ_30MHZ_MASK 0x3f 402#define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) 403#define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23) 404#define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) 405#define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) 406 407/* Global User Control Register*/ 408#define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 409#define DWC3_GUCTL_REFCLKPER_SEL 22 410 411/* Global User Control Register 2 */ 412#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14) 413 414/* Global User Control Register 3 */ 415#define DWC3_GUCTL3_SPLITDISABLE BIT(14) 416 417/* Device Configuration Register */ 418#define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */ 419 420#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 421#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 422 423#define DWC3_DCFG_SPEED_MASK (7 << 0) 424#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 425#define DWC3_DCFG_SUPERSPEED (4 << 0) 426#define DWC3_DCFG_HIGHSPEED (0 << 0) 427#define DWC3_DCFG_FULLSPEED BIT(0) 428 429#define DWC3_DCFG_NUMP_SHIFT 17 430#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) 431#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) 432#define DWC3_DCFG_LPM_CAP BIT(22) 433#define DWC3_DCFG_IGNSTRMPP BIT(23) 434 435/* Device Control Register */ 436#define DWC3_DCTL_RUN_STOP BIT(31) 437#define DWC3_DCTL_CSFTRST BIT(30) 438#define DWC3_DCTL_LSFTRST BIT(29) 439 440#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 441#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) 442 443#define DWC3_DCTL_APPL1RES BIT(23) 444 445/* These apply for core versions 1.87a and earlier */ 446#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 447#define DWC3_DCTL_TRGTULST(n) ((n) << 17) 448#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 449#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 450#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 451#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 452#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 453 454/* These apply for core versions 1.94a and later */ 455#define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20) 456 457#define DWC3_DCTL_KEEP_CONNECT BIT(19) 458#define DWC3_DCTL_L1_HIBER_EN BIT(18) 459#define DWC3_DCTL_CRS BIT(17) 460#define DWC3_DCTL_CSS BIT(16) 461 462#define DWC3_DCTL_INITU2ENA BIT(12) 463#define DWC3_DCTL_ACCEPTU2ENA BIT(11) 464#define DWC3_DCTL_INITU1ENA BIT(10) 465#define DWC3_DCTL_ACCEPTU1ENA BIT(9) 466#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 467 468#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 469#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 470 471#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 472#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 473#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 474#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 475#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 476#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 477#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 478 479/* Device Event Enable Register */ 480#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12) 481#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11) 482#define DWC3_DEVTEN_CMDCMPLTEN BIT(10) 483#define DWC3_DEVTEN_ERRTICERREN BIT(9) 484#define DWC3_DEVTEN_SOFEN BIT(7) 485#define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6) 486#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5) 487#define DWC3_DEVTEN_WKUPEVTEN BIT(4) 488#define DWC3_DEVTEN_ULSTCNGEN BIT(3) 489#define DWC3_DEVTEN_CONNECTDONEEN BIT(2) 490#define DWC3_DEVTEN_USBRSTEN BIT(1) 491#define DWC3_DEVTEN_DISCONNEVTEN BIT(0) 492 493#define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */ 494 495/* Device Status Register */ 496#define DWC3_DSTS_DCNRD BIT(29) 497 498/* This applies for core versions 1.87a and earlier */ 499#define DWC3_DSTS_PWRUPREQ BIT(24) 500 501/* These apply for core versions 1.94a and later */ 502#define DWC3_DSTS_RSS BIT(25) 503#define DWC3_DSTS_SSS BIT(24) 504 505#define DWC3_DSTS_COREIDLE BIT(23) 506#define DWC3_DSTS_DEVCTRLHLT BIT(22) 507 508#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 509#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 510 511#define DWC3_DSTS_RXFIFOEMPTY BIT(17) 512 513#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) 514#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 515 516#define DWC3_DSTS_CONNECTSPD (7 << 0) 517 518#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ 519#define DWC3_DSTS_SUPERSPEED (4 << 0) 520#define DWC3_DSTS_HIGHSPEED (0 << 0) 521#define DWC3_DSTS_FULLSPEED BIT(0) 522 523/* Device Generic Command Register */ 524#define DWC3_DGCMD_SET_LMP 0x01 525#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 526#define DWC3_DGCMD_XMIT_FUNCTION 0x03 527 528/* These apply for core versions 1.94a and later */ 529#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 530#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 531 532#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 533#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 534#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 535#define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d 536#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 537#define DWC3_DGCMD_DEV_NOTIFICATION 0x07 538 539#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) 540#define DWC3_DGCMD_CMDACT BIT(10) 541#define DWC3_DGCMD_CMDIOC BIT(8) 542 543/* Device Generic Command Parameter Register */ 544#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0) 545#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) 546#define DWC3_DGCMDPAR_RX_FIFO (0 << 5) 547#define DWC3_DGCMDPAR_TX_FIFO BIT(5) 548#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) 549#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0) 550#define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0) 551#define DWC3_DGCMDPAR_INTF_SEL(n) ((n) << 4) 552 553/* Device Endpoint Command Register */ 554#define DWC3_DEPCMD_PARAM_SHIFT 16 555#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 556#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 557#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) 558#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11) 559#define DWC3_DEPCMD_CLEARPENDIN BIT(11) 560#define DWC3_DEPCMD_CMDACT BIT(10) 561#define DWC3_DEPCMD_CMDIOC BIT(8) 562 563#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 564#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 565#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 566#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 567#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 568#define DWC3_DEPCMD_SETSTALL (0x04 << 0) 569/* This applies for core versions 1.90a and earlier */ 570#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 571/* This applies for core versions 1.94a and later */ 572#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) 573#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 574#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 575 576#define DWC3_DEPCMD_CMD(x) ((x) & 0xf) 577 578/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 579#define DWC3_DALEPENA_EP(n) BIT(n) 580 581/* DWC_usb32 DCFG1 config */ 582#define DWC3_DCFG1_DIS_MST_ENH BIT(1) 583 584#define DWC3_DEPCMD_TYPE_CONTROL 0 585#define DWC3_DEPCMD_TYPE_ISOC 1 586#define DWC3_DEPCMD_TYPE_BULK 2 587#define DWC3_DEPCMD_TYPE_INTR 3 588 589#define DWC3_DEV_IMOD_COUNT_SHIFT 16 590#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) 591#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 592#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) 593 594/* OTG Configuration Register */ 595#define DWC3_OCFG_DISPWRCUTTOFF BIT(5) 596#define DWC3_OCFG_HIBDISMASK BIT(4) 597#define DWC3_OCFG_SFTRSTMASK BIT(3) 598#define DWC3_OCFG_OTGVERSION BIT(2) 599#define DWC3_OCFG_HNPCAP BIT(1) 600#define DWC3_OCFG_SRPCAP BIT(0) 601 602/* OTG CTL Register */ 603#define DWC3_OCTL_OTG3GOERR BIT(7) 604#define DWC3_OCTL_PERIMODE BIT(6) 605#define DWC3_OCTL_PRTPWRCTL BIT(5) 606#define DWC3_OCTL_HNPREQ BIT(4) 607#define DWC3_OCTL_SESREQ BIT(3) 608#define DWC3_OCTL_TERMSELIDPULSE BIT(2) 609#define DWC3_OCTL_DEVSETHNPEN BIT(1) 610#define DWC3_OCTL_HSTSETHNPEN BIT(0) 611 612/* OTG Event Register */ 613#define DWC3_OEVT_DEVICEMODE BIT(31) 614#define DWC3_OEVT_XHCIRUNSTPSET BIT(27) 615#define DWC3_OEVT_DEVRUNSTPSET BIT(26) 616#define DWC3_OEVT_HIBENTRY BIT(25) 617#define DWC3_OEVT_CONIDSTSCHNG BIT(24) 618#define DWC3_OEVT_HRRCONFNOTIF BIT(23) 619#define DWC3_OEVT_HRRINITNOTIF BIT(22) 620#define DWC3_OEVT_ADEVIDLE BIT(21) 621#define DWC3_OEVT_ADEVBHOSTEND BIT(20) 622#define DWC3_OEVT_ADEVHOST BIT(19) 623#define DWC3_OEVT_ADEVHNPCHNG BIT(18) 624#define DWC3_OEVT_ADEVSRPDET BIT(17) 625#define DWC3_OEVT_ADEVSESSENDDET BIT(16) 626#define DWC3_OEVT_BDEVBHOSTEND BIT(11) 627#define DWC3_OEVT_BDEVHNPCHNG BIT(10) 628#define DWC3_OEVT_BDEVSESSVLDDET BIT(9) 629#define DWC3_OEVT_BDEVVBUSCHNG BIT(8) 630#define DWC3_OEVT_BSESSVLD BIT(3) 631#define DWC3_OEVT_HSTNEGSTS BIT(2) 632#define DWC3_OEVT_SESREQSTS BIT(1) 633#define DWC3_OEVT_ERROR BIT(0) 634 635/* OTG Event Enable Register */ 636#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27) 637#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26) 638#define DWC3_OEVTEN_HIBENTRYEN BIT(25) 639#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24) 640#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23) 641#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22) 642#define DWC3_OEVTEN_ADEVIDLEEN BIT(21) 643#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20) 644#define DWC3_OEVTEN_ADEVHOSTEN BIT(19) 645#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18) 646#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17) 647#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16) 648#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11) 649#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10) 650#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9) 651#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8) 652 653/* OTG Status Register */ 654#define DWC3_OSTS_DEVRUNSTP BIT(13) 655#define DWC3_OSTS_XHCIRUNSTP BIT(12) 656#define DWC3_OSTS_PERIPHERALSTATE BIT(4) 657#define DWC3_OSTS_XHCIPRTPOWER BIT(3) 658#define DWC3_OSTS_BSESVLD BIT(2) 659#define DWC3_OSTS_VBUSVLD BIT(1) 660#define DWC3_OSTS_CONIDSTS BIT(0) 661 662/* Force Gen1 speed on Gen2 link */ 663#define DWC3_LLUCTL_FORCE_GEN1 BIT(10) 664 665/* Structures */ 666 667struct dwc3_trb; 668 669/** 670 * struct dwc3_event_buffer - Software event buffer representation 671 * @buf: _THE_ buffer 672 * @cache: The buffer cache used in the threaded interrupt 673 * @length: size of this buffer 674 * @lpos: event offset 675 * @count: cache of last read event count register 676 * @flags: flags related to this event buffer 677 * @dma: dma_addr_t 678 * @dwc: pointer to DWC controller 679 */ 680struct dwc3_event_buffer { 681 void *buf; 682 void *cache; 683 unsigned int length; 684 unsigned int lpos; 685 unsigned int count; 686 unsigned int flags; 687 688#define DWC3_EVENT_PENDING BIT(0) 689 690 dma_addr_t dma; 691 692 struct dwc3 *dwc; 693}; 694 695#define DWC3_EP_FLAG_STALLED BIT(0) 696#define DWC3_EP_FLAG_WEDGED BIT(1) 697 698#define DWC3_EP_DIRECTION_TX true 699#define DWC3_EP_DIRECTION_RX false 700 701#define DWC3_TRB_NUM 256 702 703/** 704 * struct dwc3_ep - device side endpoint representation 705 * @endpoint: usb endpoint 706 * @cancelled_list: list of cancelled requests for this endpoint 707 * @pending_list: list of pending requests for this endpoint 708 * @started_list: list of started requests on this endpoint 709 * @regs: pointer to first endpoint register 710 * @trb_pool: array of transaction buffers 711 * @trb_pool_dma: dma address of @trb_pool 712 * @trb_enqueue: enqueue 'pointer' into TRB array 713 * @trb_dequeue: dequeue 'pointer' into TRB array 714 * @dwc: pointer to DWC controller 715 * @saved_state: ep state saved during hibernation 716 * @flags: endpoint flags (wedged, stalled, ...) 717 * @number: endpoint number (1 - 15) 718 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 719 * @resource_index: Resource transfer index 720 * @frame_number: set to the frame number we want this transfer to start (ISOC) 721 * @interval: the interval on which the ISOC transfer is started 722 * @name: a human readable name e.g. ep1out-bulk 723 * @direction: true for TX, false for RX 724 * @stream_capable: true when streams are enabled 725 * @combo_num: the test combination BIT[15:14] of the frame number to test 726 * isochronous START TRANSFER command failure workaround 727 * @start_cmd_status: the status of testing START TRANSFER command with 728 * combo_num = 'b00 729 */ 730struct dwc3_ep { 731 struct usb_ep endpoint; 732 struct list_head cancelled_list; 733 struct list_head pending_list; 734 struct list_head started_list; 735 736 void __iomem *regs; 737 738 struct dwc3_trb *trb_pool; 739 dma_addr_t trb_pool_dma; 740 struct dwc3 *dwc; 741 742 u32 saved_state; 743 unsigned int flags; 744#define DWC3_EP_ENABLED BIT(0) 745#define DWC3_EP_STALL BIT(1) 746#define DWC3_EP_WEDGE BIT(2) 747#define DWC3_EP_TRANSFER_STARTED BIT(3) 748#define DWC3_EP_END_TRANSFER_PENDING BIT(4) 749#define DWC3_EP_PENDING_REQUEST BIT(5) 750#define DWC3_EP_DELAY_START BIT(6) 751#define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7) 752#define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8) 753#define DWC3_EP_FORCE_RESTART_STREAM BIT(9) 754#define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) 755#define DWC3_EP_PENDING_CLEAR_STALL BIT(11) 756#define DWC3_EP_TXFIFO_RESIZED BIT(12) 757#define DWC3_EP_DELAY_STOP BIT(13) 758#define DWC3_EP_RESOURCE_ALLOCATED BIT(14) 759 760 /* This last one is specific to EP0 */ 761#define DWC3_EP0_DIR_IN BIT(31) 762 763 /* 764 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will 765 * use a u8 type here. If anybody decides to increase number of TRBs to 766 * anything larger than 256 - I can't see why people would want to do 767 * this though - then this type needs to be changed. 768 * 769 * By using u8 types we ensure that our % operator when incrementing 770 * enqueue and dequeue get optimized away by the compiler. 771 */ 772 u8 trb_enqueue; 773 u8 trb_dequeue; 774 775 u8 number; 776 u8 type; 777 u8 resource_index; 778 u32 frame_number; 779 u32 interval; 780 781 char name[20]; 782 783 unsigned direction:1; 784 unsigned stream_capable:1; 785 786 /* For isochronous START TRANSFER workaround only */ 787 u8 combo_num; 788 int start_cmd_status; 789}; 790 791enum dwc3_phy { 792 DWC3_PHY_UNKNOWN = 0, 793 DWC3_PHY_USB3, 794 DWC3_PHY_USB2, 795}; 796 797enum dwc3_ep0_next { 798 DWC3_EP0_UNKNOWN = 0, 799 DWC3_EP0_COMPLETE, 800 DWC3_EP0_NRDY_DATA, 801 DWC3_EP0_NRDY_STATUS, 802}; 803 804enum dwc3_ep0_state { 805 EP0_UNCONNECTED = 0, 806 EP0_SETUP_PHASE, 807 EP0_DATA_PHASE, 808 EP0_STATUS_PHASE, 809}; 810 811enum dwc3_link_state { 812 /* In SuperSpeed */ 813 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 814 DWC3_LINK_STATE_U1 = 0x01, 815 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 816 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 817 DWC3_LINK_STATE_SS_DIS = 0x04, 818 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 819 DWC3_LINK_STATE_SS_INACT = 0x06, 820 DWC3_LINK_STATE_POLL = 0x07, 821 DWC3_LINK_STATE_RECOV = 0x08, 822 DWC3_LINK_STATE_HRESET = 0x09, 823 DWC3_LINK_STATE_CMPLY = 0x0a, 824 DWC3_LINK_STATE_LPBK = 0x0b, 825 DWC3_LINK_STATE_RESET = 0x0e, 826 DWC3_LINK_STATE_RESUME = 0x0f, 827 DWC3_LINK_STATE_MASK = 0x0f, 828}; 829 830/* TRB Length, PCM and Status */ 831#define DWC3_TRB_SIZE_MASK (0x00ffffff) 832#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 833#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 834#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) 835 836#define DWC3_TRBSTS_OK 0 837#define DWC3_TRBSTS_MISSED_ISOC 1 838#define DWC3_TRBSTS_SETUP_PENDING 2 839#define DWC3_TRB_STS_XFER_IN_PROG 4 840 841/* TRB Control */ 842#define DWC3_TRB_CTRL_HWO BIT(0) 843#define DWC3_TRB_CTRL_LST BIT(1) 844#define DWC3_TRB_CTRL_CHN BIT(2) 845#define DWC3_TRB_CTRL_CSP BIT(3) 846#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 847#define DWC3_TRB_CTRL_ISP_IMI BIT(10) 848#define DWC3_TRB_CTRL_IOC BIT(11) 849#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 850#define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14) 851 852#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) 853#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 854#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 855#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 856#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 857#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 858#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 859#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 860#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 861 862/** 863 * struct dwc3_trb - transfer request block (hw format) 864 * @bpl: DW0-3 865 * @bph: DW4-7 866 * @size: DW8-B 867 * @ctrl: DWC-F 868 */ 869struct dwc3_trb { 870 u32 bpl; 871 u32 bph; 872 u32 size; 873 u32 ctrl; 874} __packed; 875 876/** 877 * struct dwc3_hwparams - copy of HWPARAMS registers 878 * @hwparams0: GHWPARAMS0 879 * @hwparams1: GHWPARAMS1 880 * @hwparams2: GHWPARAMS2 881 * @hwparams3: GHWPARAMS3 882 * @hwparams4: GHWPARAMS4 883 * @hwparams5: GHWPARAMS5 884 * @hwparams6: GHWPARAMS6 885 * @hwparams7: GHWPARAMS7 886 * @hwparams8: GHWPARAMS8 887 * @hwparams9: GHWPARAMS9 888 */ 889struct dwc3_hwparams { 890 u32 hwparams0; 891 u32 hwparams1; 892 u32 hwparams2; 893 u32 hwparams3; 894 u32 hwparams4; 895 u32 hwparams5; 896 u32 hwparams6; 897 u32 hwparams7; 898 u32 hwparams8; 899 u32 hwparams9; 900}; 901 902/* HWPARAMS0 */ 903#define DWC3_MODE(n) ((n) & 0x7) 904 905/* HWPARAMS1 */ 906#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 907 908/* HWPARAMS3 */ 909#define DWC3_NUM_IN_EPS_MASK (0x1f << 18) 910#define DWC3_NUM_EPS_MASK (0x3f << 12) 911#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ 912 (DWC3_NUM_EPS_MASK)) >> 12) 913#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ 914 (DWC3_NUM_IN_EPS_MASK)) >> 18) 915 916/* HWPARAMS7 */ 917#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 918 919/* HWPARAMS9 */ 920#define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \ 921 DWC3_GHWPARAMS9_DEV_MST)) 922 923/** 924 * struct dwc3_request - representation of a transfer request 925 * @request: struct usb_request to be transferred 926 * @list: a list_head used for request queueing 927 * @dep: struct dwc3_ep owning this request 928 * @sg: pointer to first incomplete sg 929 * @start_sg: pointer to the sg which should be queued next 930 * @num_pending_sgs: counter to pending sgs 931 * @num_queued_sgs: counter to the number of sgs which already got queued 932 * @remaining: amount of data remaining 933 * @status: internal dwc3 request status tracking 934 * @epnum: endpoint number to which this request refers 935 * @trb: pointer to struct dwc3_trb 936 * @trb_dma: DMA address of @trb 937 * @num_trbs: number of TRBs used by this request 938 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP 939 * or unaligned OUT) 940 * @direction: IN or OUT direction flag 941 * @mapped: true when request has been dma-mapped 942 */ 943struct dwc3_request { 944 struct usb_request request; 945 struct list_head list; 946 struct dwc3_ep *dep; 947 struct scatterlist *sg; 948 struct scatterlist *start_sg; 949 950 unsigned int num_pending_sgs; 951 unsigned int num_queued_sgs; 952 unsigned int remaining; 953 954 unsigned int status; 955#define DWC3_REQUEST_STATUS_QUEUED 0 956#define DWC3_REQUEST_STATUS_STARTED 1 957#define DWC3_REQUEST_STATUS_DISCONNECTED 2 958#define DWC3_REQUEST_STATUS_DEQUEUED 3 959#define DWC3_REQUEST_STATUS_STALLED 4 960#define DWC3_REQUEST_STATUS_COMPLETED 5 961#define DWC3_REQUEST_STATUS_UNKNOWN -1 962 963 u8 epnum; 964 struct dwc3_trb *trb; 965 dma_addr_t trb_dma; 966 967 unsigned int num_trbs; 968 969 unsigned int needs_extra_trb:1; 970 unsigned int direction:1; 971 unsigned int mapped:1; 972}; 973 974/* 975 * struct dwc3_scratchpad_array - hibernation scratchpad array 976 * (format defined by hw) 977 */ 978struct dwc3_scratchpad_array { 979 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; 980}; 981 982/** 983 * struct dwc3 - representation of our controller 984 * @drd_work: workqueue used for role swapping 985 * @ep0_trb: trb which is used for the ctrl_req 986 * @bounce: address of bounce buffer 987 * @setup_buf: used while precessing STD USB requests 988 * @ep0_trb_addr: dma address of @ep0_trb 989 * @bounce_addr: dma address of @bounce 990 * @ep0_usb_req: dummy req used while handling STD USB requests 991 * @ep0_in_setup: one control transfer is completed and enter setup phase 992 * @lock: for synchronizing 993 * @mutex: for mode switching 994 * @dev: pointer to our struct device 995 * @sysdev: pointer to the DMA-capable device 996 * @xhci: pointer to our xHCI child 997 * @xhci_resources: struct resources for our @xhci child 998 * @ev_buf: struct dwc3_event_buffer pointer 999 * @eps: endpoint array 1000 * @gadget: device side representation of the peripheral controller 1001 * @gadget_driver: pointer to the gadget driver 1002 * @bus_clk: clock for accessing the registers 1003 * @ref_clk: reference clock 1004 * @susp_clk: clock used when the SS phy is in low power (S3) state 1005 * @utmi_clk: clock used for USB2 PHY communication 1006 * @pipe_clk: clock used for USB3 PHY communication 1007 * @reset: reset control 1008 * @regs: base address for our registers 1009 * @regs_size: address space size 1010 * @fladj: frame length adjustment 1011 * @ref_clk_per: reference clock period configuration 1012 * @irq_gadget: peripheral controller's IRQ number 1013 * @otg_irq: IRQ number for OTG IRQs 1014 * @current_otg_role: current role of operation while using the OTG block 1015 * @desired_otg_role: desired role of operation while using the OTG block 1016 * @otg_restart_host: flag that OTG controller needs to restart host 1017 * @u1u2: only used on revisions <1.83a for workaround 1018 * @maximum_speed: maximum speed requested (mainly for testing purposes) 1019 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count 1020 * @gadget_max_speed: maximum gadget speed requested 1021 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling 1022 * rate and lane count. 1023 * @ip: controller's ID 1024 * @revision: controller's version of an IP 1025 * @version_type: VERSIONTYPE register contents, a sub release of a revision 1026 * @dr_mode: requested mode of operation 1027 * @current_dr_role: current role of operation when in dual-role mode 1028 * @desired_dr_role: desired role of operation when in dual-role mode 1029 * @edev: extcon handle 1030 * @edev_nb: extcon notifier 1031 * @hsphy_mode: UTMI phy mode, one of following: 1032 * - USBPHY_INTERFACE_MODE_UTMI 1033 * - USBPHY_INTERFACE_MODE_UTMIW 1034 * @role_sw: usb_role_switch handle 1035 * @role_switch_default_mode: default operation mode of controller while 1036 * usb role is USB_ROLE_NONE. 1037 * @usb_psy: pointer to power supply interface. 1038 * @usb2_phy: pointer to USB2 PHY 1039 * @usb3_phy: pointer to USB3 PHY 1040 * @usb2_generic_phy: pointer to USB2 PHY 1041 * @usb3_generic_phy: pointer to USB3 PHY 1042 * @phys_ready: flag to indicate that PHYs are ready 1043 * @ulpi: pointer to ulpi interface 1044 * @ulpi_ready: flag to indicate that ULPI is initialized 1045 * @u2sel: parameter from Set SEL request. 1046 * @u2pel: parameter from Set SEL request. 1047 * @u1sel: parameter from Set SEL request. 1048 * @u1pel: parameter from Set SEL request. 1049 * @num_eps: number of endpoints 1050 * @ep0_next_event: hold the next expected event 1051 * @ep0state: state of endpoint zero 1052 * @link_state: link state 1053 * @speed: device speed (super, high, full, low) 1054 * @hwparams: copy of hwparams registers 1055 * @regset: debugfs pointer to regdump file 1056 * @dbg_lsp_select: current debug lsp mux register selection 1057 * @test_mode: true when we're entering a USB test mode 1058 * @test_mode_nr: test feature selector 1059 * @lpm_nyet_threshold: LPM NYET response threshold 1060 * @hird_threshold: HIRD threshold 1061 * @rx_thr_num_pkt: USB receive packet count 1062 * @rx_max_burst: max USB receive burst size 1063 * @tx_thr_num_pkt: USB transmit packet count 1064 * @tx_max_burst: max USB transmit burst size 1065 * @rx_thr_num_pkt_prd: periodic ESS receive packet count 1066 * @rx_max_burst_prd: max periodic ESS receive burst size 1067 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count 1068 * @tx_max_burst_prd: max periodic ESS transmit burst size 1069 * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize 1070 * @clear_stall_protocol: endpoint number that requires a delayed status phase 1071 * @hsphy_interface: "utmi" or "ulpi" 1072 * @connected: true when we're connected to a host, false otherwise 1073 * @softconnect: true when gadget connect is called, false when disconnect runs 1074 * @delayed_status: true when gadget driver asks for delayed status 1075 * @ep0_bounced: true when we used bounce buffer 1076 * @ep0_expect_in: true when we expect a DATA IN transfer 1077 * @sysdev_is_parent: true when dwc3 device has a parent driver 1078 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that 1079 * there's now way for software to detect this in runtime. 1080 * @is_utmi_l1_suspend: the core asserts output signal 1081 * 0 - utmi_sleep_n 1082 * 1 - utmi_l1_suspend_n 1083 * @is_fpga: true when we are using the FPGA board 1084 * @pending_events: true when we have pending IRQs to be handled 1085 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints 1086 * @pullups_connected: true when Run/Stop bit is set 1087 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 1088 * @three_stage_setup: set if we perform a three phase setup 1089 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is 1090 * not needed for DWC_usb31 version 1.70a-ea06 and below 1091 * @usb3_lpm_capable: set if hadrware supports Link Power Management 1092 * @usb2_lpm_disable: set to disable usb2 lpm for host 1093 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget 1094 * @disable_scramble_quirk: set if we enable the disable scramble quirk 1095 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk 1096 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 1097 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk 1098 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk 1099 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk 1100 * @lfps_filter_quirk: set if we enable LFPS filter quirk 1101 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk 1102 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy 1103 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy 1104 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, 1105 * disabling the suspend signal to the PHY. 1106 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled. 1107 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled. 1108 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3 1109 * @async_callbacks: if set, indicate that async callbacks will be used. 1110 * 1111 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists 1112 * in GUSB2PHYCFG, specify that USB2 PHY doesn't 1113 * provide a free-running PHY clock. 1114 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power 1115 * change quirk. 1116 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate 1117 * check during HS transmit. 1118 * @resume_hs_terminations: Set if we enable quirk for fixing improper crc 1119 * generation after resume from suspend. 1120 * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin 1121 * VBUS with an external supply. 1122 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed 1123 * instances in park mode. 1124 * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed 1125 * instances in park mode. 1126 * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter 1127 * running based on ref_clk 1128 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk 1129 * @tx_de_emphasis: Tx de-emphasis value 1130 * 0 - -6dB de-emphasis 1131 * 1 - -3.5dB de-emphasis 1132 * 2 - No de-emphasis 1133 * 3 - Reserved 1134 * @dis_metastability_quirk: set to disable metastability quirk. 1135 * @dis_split_quirk: set to disable split boundary. 1136 * @sys_wakeup: set if the device may do system wakeup. 1137 * @wakeup_configured: set if the device is configured for remote wakeup. 1138 * @suspended: set to track suspend event due to U3/L2. 1139 * @imod_interval: set the interrupt moderation interval in 250ns 1140 * increments or 0 to disable. 1141 * @max_cfg_eps: current max number of IN eps used across all USB configs. 1142 * @last_fifo_depth: last fifo depth used to determine next fifo ram start 1143 * address. 1144 * @num_ep_resized: carries the current number endpoints which have had its tx 1145 * fifo resized. 1146 * @debug_root: root debugfs directory for this device to put its files in. 1147 */ 1148struct dwc3 { 1149 struct work_struct drd_work; 1150 struct dwc3_trb *ep0_trb; 1151 void *bounce; 1152 u8 *setup_buf; 1153 dma_addr_t ep0_trb_addr; 1154 dma_addr_t bounce_addr; 1155 struct dwc3_request ep0_usb_req; 1156 struct completion ep0_in_setup; 1157 1158 /* device lock */ 1159 spinlock_t lock; 1160 1161 /* mode switching lock */ 1162 struct mutex mutex; 1163 1164 struct device *dev; 1165 struct device *sysdev; 1166 1167 struct platform_device *xhci; 1168 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; 1169 1170 struct dwc3_event_buffer *ev_buf; 1171 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 1172 1173 struct usb_gadget *gadget; 1174 struct usb_gadget_driver *gadget_driver; 1175 1176 struct clk *bus_clk; 1177 struct clk *ref_clk; 1178 struct clk *susp_clk; 1179 struct clk *utmi_clk; 1180 struct clk *pipe_clk; 1181 1182 struct reset_control *reset; 1183 1184 struct usb_phy *usb2_phy; 1185 struct usb_phy *usb3_phy; 1186 1187 struct phy *usb2_generic_phy; 1188 struct phy *usb3_generic_phy; 1189 1190 bool phys_ready; 1191 1192 struct ulpi *ulpi; 1193 bool ulpi_ready; 1194 1195 void __iomem *regs; 1196 size_t regs_size; 1197 1198 enum usb_dr_mode dr_mode; 1199 u32 current_dr_role; 1200 u32 desired_dr_role; 1201 struct extcon_dev *edev; 1202 struct notifier_block edev_nb; 1203 enum usb_phy_interface hsphy_mode; 1204 struct usb_role_switch *role_sw; 1205 enum usb_dr_mode role_switch_default_mode; 1206 1207 struct power_supply *usb_psy; 1208 1209 u32 fladj; 1210 u32 ref_clk_per; 1211 u32 irq_gadget; 1212 u32 otg_irq; 1213 u32 current_otg_role; 1214 u32 desired_otg_role; 1215 bool otg_restart_host; 1216 u32 u1u2; 1217 u32 maximum_speed; 1218 u32 gadget_max_speed; 1219 enum usb_ssp_rate max_ssp_rate; 1220 enum usb_ssp_rate gadget_ssp_rate; 1221 1222 u32 ip; 1223 1224#define DWC3_IP 0x5533 1225#define DWC31_IP 0x3331 1226#define DWC32_IP 0x3332 1227 1228 u32 revision; 1229 1230#define DWC3_REVISION_ANY 0x0 1231#define DWC3_REVISION_173A 0x5533173a 1232#define DWC3_REVISION_175A 0x5533175a 1233#define DWC3_REVISION_180A 0x5533180a 1234#define DWC3_REVISION_183A 0x5533183a 1235#define DWC3_REVISION_185A 0x5533185a 1236#define DWC3_REVISION_187A 0x5533187a 1237#define DWC3_REVISION_188A 0x5533188a 1238#define DWC3_REVISION_190A 0x5533190a 1239#define DWC3_REVISION_194A 0x5533194a 1240#define DWC3_REVISION_200A 0x5533200a 1241#define DWC3_REVISION_202A 0x5533202a 1242#define DWC3_REVISION_210A 0x5533210a 1243#define DWC3_REVISION_220A 0x5533220a 1244#define DWC3_REVISION_230A 0x5533230a 1245#define DWC3_REVISION_240A 0x5533240a 1246#define DWC3_REVISION_250A 0x5533250a 1247#define DWC3_REVISION_260A 0x5533260a 1248#define DWC3_REVISION_270A 0x5533270a 1249#define DWC3_REVISION_280A 0x5533280a 1250#define DWC3_REVISION_290A 0x5533290a 1251#define DWC3_REVISION_300A 0x5533300a 1252#define DWC3_REVISION_310A 0x5533310a 1253#define DWC3_REVISION_330A 0x5533330a 1254 1255#define DWC31_REVISION_ANY 0x0 1256#define DWC31_REVISION_110A 0x3131302a 1257#define DWC31_REVISION_120A 0x3132302a 1258#define DWC31_REVISION_160A 0x3136302a 1259#define DWC31_REVISION_170A 0x3137302a 1260#define DWC31_REVISION_180A 0x3138302a 1261#define DWC31_REVISION_190A 0x3139302a 1262#define DWC31_REVISION_200A 0x3230302a 1263 1264#define DWC32_REVISION_ANY 0x0 1265#define DWC32_REVISION_100A 0x3130302a 1266 1267 u32 version_type; 1268 1269#define DWC31_VERSIONTYPE_ANY 0x0 1270#define DWC31_VERSIONTYPE_EA01 0x65613031 1271#define DWC31_VERSIONTYPE_EA02 0x65613032 1272#define DWC31_VERSIONTYPE_EA03 0x65613033 1273#define DWC31_VERSIONTYPE_EA04 0x65613034 1274#define DWC31_VERSIONTYPE_EA05 0x65613035 1275#define DWC31_VERSIONTYPE_EA06 0x65613036 1276 1277 enum dwc3_ep0_next ep0_next_event; 1278 enum dwc3_ep0_state ep0state; 1279 enum dwc3_link_state link_state; 1280 1281 u16 u2sel; 1282 u16 u2pel; 1283 u8 u1sel; 1284 u8 u1pel; 1285 1286 u8 speed; 1287 1288 u8 num_eps; 1289 1290 struct dwc3_hwparams hwparams; 1291 struct debugfs_regset32 *regset; 1292 1293 u32 dbg_lsp_select; 1294 1295 u8 test_mode; 1296 u8 test_mode_nr; 1297 u8 lpm_nyet_threshold; 1298 u8 hird_threshold; 1299 u8 rx_thr_num_pkt; 1300 u8 rx_max_burst; 1301 u8 tx_thr_num_pkt; 1302 u8 tx_max_burst; 1303 u8 rx_thr_num_pkt_prd; 1304 u8 rx_max_burst_prd; 1305 u8 tx_thr_num_pkt_prd; 1306 u8 tx_max_burst_prd; 1307 u8 tx_fifo_resize_max_num; 1308 u8 clear_stall_protocol; 1309 1310 const char *hsphy_interface; 1311 1312 unsigned connected:1; 1313 unsigned softconnect:1; 1314 unsigned delayed_status:1; 1315 unsigned ep0_bounced:1; 1316 unsigned ep0_expect_in:1; 1317 unsigned sysdev_is_parent:1; 1318 unsigned has_lpm_erratum:1; 1319 unsigned is_utmi_l1_suspend:1; 1320 unsigned is_fpga:1; 1321 unsigned pending_events:1; 1322 unsigned do_fifo_resize:1; 1323 unsigned pullups_connected:1; 1324 unsigned setup_packet_pending:1; 1325 unsigned three_stage_setup:1; 1326 unsigned dis_start_transfer_quirk:1; 1327 unsigned usb3_lpm_capable:1; 1328 unsigned usb2_lpm_disable:1; 1329 unsigned usb2_gadget_lpm_disable:1; 1330 1331 unsigned disable_scramble_quirk:1; 1332 unsigned u2exit_lfps_quirk:1; 1333 unsigned u2ss_inp3_quirk:1; 1334 unsigned req_p1p2p3_quirk:1; 1335 unsigned del_p1p2p3_quirk:1; 1336 unsigned del_phy_power_chg_quirk:1; 1337 unsigned lfps_filter_quirk:1; 1338 unsigned rx_detect_poll_quirk:1; 1339 unsigned dis_u3_susphy_quirk:1; 1340 unsigned dis_u2_susphy_quirk:1; 1341 unsigned dis_enblslpm_quirk:1; 1342 unsigned dis_u1_entry_quirk:1; 1343 unsigned dis_u2_entry_quirk:1; 1344 unsigned dis_rxdet_inp3_quirk:1; 1345 unsigned dis_u2_freeclk_exists_quirk:1; 1346 unsigned dis_del_phy_power_chg_quirk:1; 1347 unsigned dis_tx_ipgap_linecheck_quirk:1; 1348 unsigned resume_hs_terminations:1; 1349 unsigned ulpi_ext_vbus_drv:1; 1350 unsigned parkmode_disable_ss_quirk:1; 1351 unsigned parkmode_disable_hs_quirk:1; 1352 unsigned gfladj_refclk_lpm_sel:1; 1353 1354 unsigned tx_de_emphasis_quirk:1; 1355 unsigned tx_de_emphasis:2; 1356 1357 unsigned dis_metastability_quirk:1; 1358 1359 unsigned dis_split_quirk:1; 1360 unsigned async_callbacks:1; 1361 unsigned sys_wakeup:1; 1362 unsigned wakeup_configured:1; 1363 unsigned suspended:1; 1364 1365 u16 imod_interval; 1366 1367 int max_cfg_eps; 1368 int last_fifo_depth; 1369 int num_ep_resized; 1370 struct dentry *debug_root; 1371}; 1372 1373#define INCRX_BURST_MODE 0 1374#define INCRX_UNDEF_LENGTH_BURST_MODE 1 1375 1376#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) 1377 1378/* -------------------------------------------------------------------------- */ 1379 1380struct dwc3_event_type { 1381 u32 is_devspec:1; 1382 u32 type:7; 1383 u32 reserved8_31:24; 1384} __packed; 1385 1386#define DWC3_DEPEVT_XFERCOMPLETE 0x01 1387#define DWC3_DEPEVT_XFERINPROGRESS 0x02 1388#define DWC3_DEPEVT_XFERNOTREADY 0x03 1389#define DWC3_DEPEVT_RXTXFIFOEVT 0x04 1390#define DWC3_DEPEVT_STREAMEVT 0x06 1391#define DWC3_DEPEVT_EPCMDCMPLT 0x07 1392 1393/** 1394 * struct dwc3_event_depevt - Device Endpoint Events 1395 * @one_bit: indicates this is an endpoint event (not used) 1396 * @endpoint_number: number of the endpoint 1397 * @endpoint_event: The event we have: 1398 * 0x00 - Reserved 1399 * 0x01 - XferComplete 1400 * 0x02 - XferInProgress 1401 * 0x03 - XferNotReady 1402 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 1403 * 0x05 - Reserved 1404 * 0x06 - StreamEvt 1405 * 0x07 - EPCmdCmplt 1406 * @reserved11_10: Reserved, don't use. 1407 * @status: Indicates the status of the event. Refer to databook for 1408 * more information. 1409 * @parameters: Parameters of the current event. Refer to databook for 1410 * more information. 1411 */ 1412struct dwc3_event_depevt { 1413 u32 one_bit:1; 1414 u32 endpoint_number:5; 1415 u32 endpoint_event:4; 1416 u32 reserved11_10:2; 1417 u32 status:4; 1418 1419/* Within XferNotReady */ 1420#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3) 1421 1422/* Within XferComplete or XferInProgress */ 1423#define DEPEVT_STATUS_BUSERR BIT(0) 1424#define DEPEVT_STATUS_SHORT BIT(1) 1425#define DEPEVT_STATUS_IOC BIT(2) 1426#define DEPEVT_STATUS_LST BIT(3) /* XferComplete */ 1427#define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */ 1428 1429/* Stream event only */ 1430#define DEPEVT_STREAMEVT_FOUND 1 1431#define DEPEVT_STREAMEVT_NOTFOUND 2 1432 1433/* Stream event parameter */ 1434#define DEPEVT_STREAM_PRIME 0xfffe 1435#define DEPEVT_STREAM_NOSTREAM 0x0 1436 1437/* Control-only Status */ 1438#define DEPEVT_STATUS_CONTROL_DATA 1 1439#define DEPEVT_STATUS_CONTROL_STATUS 2 1440#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3) 1441 1442/* In response to Start Transfer */ 1443#define DEPEVT_TRANSFER_NO_RESOURCE 1 1444#define DEPEVT_TRANSFER_BUS_EXPIRY 2 1445 1446 u32 parameters:16; 1447 1448/* For Command Complete Events */ 1449#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8) 1450} __packed; 1451 1452/** 1453 * struct dwc3_event_devt - Device Events 1454 * @one_bit: indicates this is a non-endpoint event (not used) 1455 * @device_event: indicates it's a device event. Should read as 0x00 1456 * @type: indicates the type of device event. 1457 * 0 - DisconnEvt 1458 * 1 - USBRst 1459 * 2 - ConnectDone 1460 * 3 - ULStChng 1461 * 4 - WkUpEvt 1462 * 5 - Reserved 1463 * 6 - Suspend (EOPF on revisions 2.10a and prior) 1464 * 7 - SOF 1465 * 8 - Reserved 1466 * 9 - ErrticErr 1467 * 10 - CmdCmplt 1468 * 11 - EvntOverflow 1469 * 12 - VndrDevTstRcved 1470 * @reserved15_12: Reserved, not used 1471 * @event_info: Information about this event 1472 * @reserved31_25: Reserved, not used 1473 */ 1474struct dwc3_event_devt { 1475 u32 one_bit:1; 1476 u32 device_event:7; 1477 u32 type:4; 1478 u32 reserved15_12:4; 1479 u32 event_info:9; 1480 u32 reserved31_25:7; 1481} __packed; 1482 1483/** 1484 * struct dwc3_event_gevt - Other Core Events 1485 * @one_bit: indicates this is a non-endpoint event (not used) 1486 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 1487 * @phy_port_number: self-explanatory 1488 * @reserved31_12: Reserved, not used. 1489 */ 1490struct dwc3_event_gevt { 1491 u32 one_bit:1; 1492 u32 device_event:7; 1493 u32 phy_port_number:4; 1494 u32 reserved31_12:20; 1495} __packed; 1496 1497/** 1498 * union dwc3_event - representation of Event Buffer contents 1499 * @raw: raw 32-bit event 1500 * @type: the type of the event 1501 * @depevt: Device Endpoint Event 1502 * @devt: Device Event 1503 * @gevt: Global Event 1504 */ 1505union dwc3_event { 1506 u32 raw; 1507 struct dwc3_event_type type; 1508 struct dwc3_event_depevt depevt; 1509 struct dwc3_event_devt devt; 1510 struct dwc3_event_gevt gevt; 1511}; 1512 1513/** 1514 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command 1515 * parameters 1516 * @param2: third parameter 1517 * @param1: second parameter 1518 * @param0: first parameter 1519 */ 1520struct dwc3_gadget_ep_cmd_params { 1521 u32 param2; 1522 u32 param1; 1523 u32 param0; 1524}; 1525 1526/* 1527 * DWC3 Features to be used as Driver Data 1528 */ 1529 1530#define DWC3_HAS_PERIPHERAL BIT(0) 1531#define DWC3_HAS_XHCI BIT(1) 1532#define DWC3_HAS_OTG BIT(3) 1533 1534/* prototypes */ 1535void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode); 1536void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 1537u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); 1538 1539#define DWC3_IP_IS(_ip) \ 1540 (dwc->ip == _ip##_IP) 1541 1542#define DWC3_VER_IS(_ip, _ver) \ 1543 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver) 1544 1545#define DWC3_VER_IS_PRIOR(_ip, _ver) \ 1546 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver) 1547 1548#define DWC3_VER_IS_WITHIN(_ip, _from, _to) \ 1549 (DWC3_IP_IS(_ip) && \ 1550 dwc->revision >= _ip##_REVISION_##_from && \ 1551 (!(_ip##_REVISION_##_to) || \ 1552 dwc->revision <= _ip##_REVISION_##_to)) 1553 1554#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \ 1555 (DWC3_VER_IS(_ip, _ver) && \ 1556 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \ 1557 (!(_ip##_VERSIONTYPE_##_to) || \ 1558 dwc->version_type <= _ip##_VERSIONTYPE_##_to)) 1559 1560/** 1561 * dwc3_mdwidth - get MDWIDTH value in bits 1562 * @dwc: pointer to our context structure 1563 * 1564 * Return MDWIDTH configuration value in bits. 1565 */ 1566static inline u32 dwc3_mdwidth(struct dwc3 *dwc) 1567{ 1568 u32 mdwidth; 1569 1570 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); 1571 if (DWC3_IP_IS(DWC32)) 1572 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6); 1573 1574 return mdwidth; 1575} 1576 1577bool dwc3_has_imod(struct dwc3 *dwc); 1578 1579int dwc3_event_buffers_setup(struct dwc3 *dwc); 1580void dwc3_event_buffers_cleanup(struct dwc3 *dwc); 1581 1582int dwc3_core_soft_reset(struct dwc3 *dwc); 1583 1584#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1585int dwc3_host_init(struct dwc3 *dwc); 1586void dwc3_host_exit(struct dwc3 *dwc); 1587#else 1588static inline int dwc3_host_init(struct dwc3 *dwc) 1589{ return 0; } 1590static inline void dwc3_host_exit(struct dwc3 *dwc) 1591{ } 1592#endif 1593 1594#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1595int dwc3_gadget_init(struct dwc3 *dwc); 1596void dwc3_gadget_exit(struct dwc3 *dwc); 1597int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); 1598int dwc3_gadget_get_link_state(struct dwc3 *dwc); 1599int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); 1600int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 1601 struct dwc3_gadget_ep_cmd_params *params); 1602int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, 1603 u32 param); 1604void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc); 1605void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status); 1606#else 1607static inline int dwc3_gadget_init(struct dwc3 *dwc) 1608{ return 0; } 1609static inline void dwc3_gadget_exit(struct dwc3 *dwc) 1610{ } 1611static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 1612{ return 0; } 1613static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) 1614{ return 0; } 1615static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, 1616 enum dwc3_link_state state) 1617{ return 0; } 1618 1619static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd, 1620 struct dwc3_gadget_ep_cmd_params *params) 1621{ return 0; } 1622static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, 1623 int cmd, u32 param) 1624{ return 0; } 1625static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) 1626{ } 1627#endif 1628 1629#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) 1630int dwc3_drd_init(struct dwc3 *dwc); 1631void dwc3_drd_exit(struct dwc3 *dwc); 1632void dwc3_otg_init(struct dwc3 *dwc); 1633void dwc3_otg_exit(struct dwc3 *dwc); 1634void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus); 1635void dwc3_otg_host_init(struct dwc3 *dwc); 1636#else 1637static inline int dwc3_drd_init(struct dwc3 *dwc) 1638{ return 0; } 1639static inline void dwc3_drd_exit(struct dwc3 *dwc) 1640{ } 1641static inline void dwc3_otg_init(struct dwc3 *dwc) 1642{ } 1643static inline void dwc3_otg_exit(struct dwc3 *dwc) 1644{ } 1645static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) 1646{ } 1647static inline void dwc3_otg_host_init(struct dwc3 *dwc) 1648{ } 1649#endif 1650 1651/* power management interface */ 1652#if !IS_ENABLED(CONFIG_USB_DWC3_HOST) 1653int dwc3_gadget_suspend(struct dwc3 *dwc); 1654int dwc3_gadget_resume(struct dwc3 *dwc); 1655void dwc3_gadget_process_pending_events(struct dwc3 *dwc); 1656#else 1657static inline int dwc3_gadget_suspend(struct dwc3 *dwc) 1658{ 1659 return 0; 1660} 1661 1662static inline int dwc3_gadget_resume(struct dwc3 *dwc) 1663{ 1664 return 0; 1665} 1666 1667static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 1668{ 1669} 1670#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ 1671 1672#if IS_ENABLED(CONFIG_USB_DWC3_ULPI) 1673int dwc3_ulpi_init(struct dwc3 *dwc); 1674void dwc3_ulpi_exit(struct dwc3 *dwc); 1675#else 1676static inline int dwc3_ulpi_init(struct dwc3 *dwc) 1677{ return 0; } 1678static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 1679{ } 1680#endif 1681 1682#endif /* __DRIVERS_USB_DWC3_CORE_H */ 1683