1// SPDX-License-Identifier: GPL-2.0 2/* 3 * cdns3-imx.c - NXP i.MX specific Glue layer for Cadence USB Controller 4 * 5 * Copyright (C) 2019 NXP 6 */ 7 8#include <linux/bits.h> 9#include <linux/clk.h> 10#include <linux/module.h> 11#include <linux/kernel.h> 12#include <linux/interrupt.h> 13#include <linux/platform_device.h> 14#include <linux/dma-mapping.h> 15#include <linux/io.h> 16#include <linux/of_platform.h> 17#include <linux/iopoll.h> 18#include <linux/pm_runtime.h> 19#include "core.h" 20 21#define USB3_CORE_CTRL1 0x00 22#define USB3_CORE_CTRL2 0x04 23#define USB3_INT_REG 0x08 24#define USB3_CORE_STATUS 0x0c 25#define XHCI_DEBUG_LINK_ST 0x10 26#define XHCI_DEBUG_BUS 0x14 27#define USB3_SSPHY_CTRL1 0x40 28#define USB3_SSPHY_CTRL2 0x44 29#define USB3_SSPHY_STATUS 0x4c 30#define USB2_PHY_CTRL1 0x50 31#define USB2_PHY_CTRL2 0x54 32#define USB2_PHY_STATUS 0x5c 33 34/* Register bits definition */ 35 36/* USB3_CORE_CTRL1 */ 37#define SW_RESET_MASK GENMASK(31, 26) 38#define PWR_SW_RESET BIT(31) 39#define APB_SW_RESET BIT(30) 40#define AXI_SW_RESET BIT(29) 41#define RW_SW_RESET BIT(28) 42#define PHY_SW_RESET BIT(27) 43#define PHYAHB_SW_RESET BIT(26) 44#define ALL_SW_RESET (PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \ 45 RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET) 46#define OC_DISABLE BIT(9) 47#define MDCTRL_CLK_SEL BIT(7) 48#define MODE_STRAP_MASK (0x7) 49#define DEV_MODE (1 << 2) 50#define HOST_MODE (1 << 1) 51#define OTG_MODE (1 << 0) 52 53/* USB3_INT_REG */ 54#define CLK_125_REQ BIT(29) 55#define LPM_CLK_REQ BIT(28) 56#define DEVU3_WAEKUP_EN BIT(14) 57#define OTG_WAKEUP_EN BIT(12) 58#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */ 59#define HOST_INT1_EN (1 << 0) /* HOST INT b7:0 */ 60 61/* USB3_CORE_STATUS */ 62#define MDCTRL_CLK_STATUS BIT(15) 63#define DEV_POWER_ON_READY BIT(13) 64#define HOST_POWER_ON_READY BIT(12) 65 66/* USB3_SSPHY_STATUS */ 67#define CLK_VALID_MASK (0x3f << 26) 68#define CLK_VALID_COMPARE_BITS (0xf << 28) 69#define PHY_REFCLK_REQ (1 << 0) 70 71/* OTG registers definition */ 72#define OTGSTS 0x4 73/* OTGSTS */ 74#define OTG_NRDY BIT(11) 75 76/* xHCI registers definition */ 77#define XECP_PM_PMCSR 0x8018 78#define XECP_AUX_CTRL_REG1 0x8120 79 80/* Register bits definition */ 81/* XECP_AUX_CTRL_REG1 */ 82#define CFG_RXDET_P3_EN BIT(15) 83 84/* XECP_PM_PMCSR */ 85#define PS_MASK GENMASK(1, 0) 86#define PS_D0 0 87#define PS_D1 1 88 89struct cdns_imx { 90 struct device *dev; 91 void __iomem *noncore; 92 struct clk_bulk_data *clks; 93 int num_clks; 94 struct platform_device *cdns3_pdev; 95}; 96 97static inline u32 cdns_imx_readl(struct cdns_imx *data, u32 offset) 98{ 99 return readl(data->noncore + offset); 100} 101 102static inline void cdns_imx_writel(struct cdns_imx *data, u32 offset, u32 value) 103{ 104 writel(value, data->noncore + offset); 105} 106 107static const struct clk_bulk_data imx_cdns3_core_clks[] = { 108 { .id = "lpm" }, 109 { .id = "bus" }, 110 { .id = "aclk" }, 111 { .id = "ipg" }, 112 { .id = "core" }, 113}; 114 115static int cdns_imx_noncore_init(struct cdns_imx *data) 116{ 117 u32 value; 118 int ret; 119 struct device *dev = data->dev; 120 121 cdns_imx_writel(data, USB3_SSPHY_STATUS, CLK_VALID_MASK); 122 udelay(1); 123 ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value, 124 (value & CLK_VALID_COMPARE_BITS) == CLK_VALID_COMPARE_BITS, 125 10, 100000); 126 if (ret) { 127 dev_err(dev, "wait clkvld timeout\n"); 128 return ret; 129 } 130 131 value = cdns_imx_readl(data, USB3_CORE_CTRL1); 132 value |= ALL_SW_RESET; 133 cdns_imx_writel(data, USB3_CORE_CTRL1, value); 134 udelay(1); 135 136 value = cdns_imx_readl(data, USB3_CORE_CTRL1); 137 value = (value & ~MODE_STRAP_MASK) | OTG_MODE | OC_DISABLE; 138 cdns_imx_writel(data, USB3_CORE_CTRL1, value); 139 140 value = cdns_imx_readl(data, USB3_INT_REG); 141 value |= HOST_INT1_EN | DEV_INT_EN; 142 cdns_imx_writel(data, USB3_INT_REG, value); 143 144 value = cdns_imx_readl(data, USB3_CORE_CTRL1); 145 value &= ~ALL_SW_RESET; 146 cdns_imx_writel(data, USB3_CORE_CTRL1, value); 147 return ret; 148} 149 150static int cdns_imx_platform_suspend(struct device *dev, 151 bool suspend, bool wakeup); 152static struct cdns3_platform_data cdns_imx_pdata = { 153 .platform_suspend = cdns_imx_platform_suspend, 154 .quirks = CDNS3_DEFAULT_PM_RUNTIME_ALLOW, 155}; 156 157static const struct of_dev_auxdata cdns_imx_auxdata[] = { 158 { 159 .compatible = "cdns,usb3", 160 .platform_data = &cdns_imx_pdata, 161 }, 162 {}, 163}; 164 165static int cdns_imx_probe(struct platform_device *pdev) 166{ 167 struct device *dev = &pdev->dev; 168 struct device_node *node = dev->of_node; 169 struct cdns_imx *data; 170 int ret; 171 172 if (!node) 173 return -ENODEV; 174 175 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 176 if (!data) 177 return -ENOMEM; 178 179 platform_set_drvdata(pdev, data); 180 data->dev = dev; 181 data->noncore = devm_platform_ioremap_resource(pdev, 0); 182 if (IS_ERR(data->noncore)) { 183 dev_err(dev, "can't map IOMEM resource\n"); 184 return PTR_ERR(data->noncore); 185 } 186 187 data->num_clks = ARRAY_SIZE(imx_cdns3_core_clks); 188 data->clks = devm_kmemdup(dev, imx_cdns3_core_clks, 189 sizeof(imx_cdns3_core_clks), GFP_KERNEL); 190 if (!data->clks) 191 return -ENOMEM; 192 193 ret = devm_clk_bulk_get(dev, data->num_clks, data->clks); 194 if (ret) 195 return ret; 196 197 ret = clk_bulk_prepare_enable(data->num_clks, data->clks); 198 if (ret) 199 return ret; 200 201 ret = cdns_imx_noncore_init(data); 202 if (ret) 203 goto err; 204 205 ret = of_platform_populate(node, NULL, cdns_imx_auxdata, dev); 206 if (ret) { 207 dev_err(dev, "failed to create children: %d\n", ret); 208 goto err; 209 } 210 211 device_set_wakeup_capable(dev, true); 212 pm_runtime_set_active(dev); 213 pm_runtime_enable(dev); 214 215 return ret; 216err: 217 clk_bulk_disable_unprepare(data->num_clks, data->clks); 218 return ret; 219} 220 221static void cdns_imx_remove(struct platform_device *pdev) 222{ 223 struct device *dev = &pdev->dev; 224 struct cdns_imx *data = dev_get_drvdata(dev); 225 226 pm_runtime_get_sync(dev); 227 of_platform_depopulate(dev); 228 clk_bulk_disable_unprepare(data->num_clks, data->clks); 229 pm_runtime_disable(dev); 230 pm_runtime_put_noidle(dev); 231 platform_set_drvdata(pdev, NULL); 232} 233 234#ifdef CONFIG_PM 235static void cdns3_set_wakeup(struct cdns_imx *data, bool enable) 236{ 237 u32 value; 238 239 value = cdns_imx_readl(data, USB3_INT_REG); 240 if (enable) 241 value |= OTG_WAKEUP_EN | DEVU3_WAEKUP_EN; 242 else 243 value &= ~(OTG_WAKEUP_EN | DEVU3_WAEKUP_EN); 244 245 cdns_imx_writel(data, USB3_INT_REG, value); 246} 247 248static int cdns_imx_platform_suspend(struct device *dev, 249 bool suspend, bool wakeup) 250{ 251 struct cdns *cdns = dev_get_drvdata(dev); 252 struct device *parent = dev->parent; 253 struct cdns_imx *data = dev_get_drvdata(parent); 254 void __iomem *otg_regs = (void __iomem *)(cdns->otg_regs); 255 void __iomem *xhci_regs = cdns->xhci_regs; 256 u32 value; 257 int ret = 0; 258 259 if (cdns->role != USB_ROLE_HOST) 260 return 0; 261 262 if (suspend) { 263 /* SW request low power when all usb ports allow to it ??? */ 264 value = readl(xhci_regs + XECP_PM_PMCSR); 265 value &= ~PS_MASK; 266 value |= PS_D1; 267 writel(value, xhci_regs + XECP_PM_PMCSR); 268 269 /* mdctrl_clk_sel */ 270 value = cdns_imx_readl(data, USB3_CORE_CTRL1); 271 value |= MDCTRL_CLK_SEL; 272 cdns_imx_writel(data, USB3_CORE_CTRL1, value); 273 274 /* wait for mdctrl_clk_status */ 275 value = cdns_imx_readl(data, USB3_CORE_STATUS); 276 ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value, 277 (value & MDCTRL_CLK_STATUS) == MDCTRL_CLK_STATUS, 278 10, 100000); 279 if (ret) 280 dev_warn(parent, "wait mdctrl_clk_status timeout\n"); 281 282 /* wait lpm_clk_req to be 0 */ 283 value = cdns_imx_readl(data, USB3_INT_REG); 284 ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value, 285 (value & LPM_CLK_REQ) != LPM_CLK_REQ, 286 10, 100000); 287 if (ret) 288 dev_warn(parent, "wait lpm_clk_req timeout\n"); 289 290 /* wait phy_refclk_req to be 0 */ 291 value = cdns_imx_readl(data, USB3_SSPHY_STATUS); 292 ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value, 293 (value & PHY_REFCLK_REQ) != PHY_REFCLK_REQ, 294 10, 100000); 295 if (ret) 296 dev_warn(parent, "wait phy_refclk_req timeout\n"); 297 298 cdns3_set_wakeup(data, wakeup); 299 } else { 300 cdns3_set_wakeup(data, false); 301 302 /* SW request D0 */ 303 value = readl(xhci_regs + XECP_PM_PMCSR); 304 value &= ~PS_MASK; 305 value |= PS_D0; 306 writel(value, xhci_regs + XECP_PM_PMCSR); 307 308 /* clr CFG_RXDET_P3_EN */ 309 value = readl(xhci_regs + XECP_AUX_CTRL_REG1); 310 value &= ~CFG_RXDET_P3_EN; 311 writel(value, xhci_regs + XECP_AUX_CTRL_REG1); 312 313 /* clear mdctrl_clk_sel */ 314 value = cdns_imx_readl(data, USB3_CORE_CTRL1); 315 value &= ~MDCTRL_CLK_SEL; 316 cdns_imx_writel(data, USB3_CORE_CTRL1, value); 317 318 /* wait CLK_125_REQ to be 1 */ 319 value = cdns_imx_readl(data, USB3_INT_REG); 320 ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value, 321 (value & CLK_125_REQ) == CLK_125_REQ, 322 10, 100000); 323 if (ret) 324 dev_warn(parent, "wait CLK_125_REQ timeout\n"); 325 326 /* wait for mdctrl_clk_status is cleared */ 327 value = cdns_imx_readl(data, USB3_CORE_STATUS); 328 ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value, 329 (value & MDCTRL_CLK_STATUS) != MDCTRL_CLK_STATUS, 330 10, 100000); 331 if (ret) 332 dev_warn(parent, "wait mdctrl_clk_status cleared timeout\n"); 333 334 /* Wait until OTG_NRDY is 0 */ 335 value = readl(otg_regs + OTGSTS); 336 ret = readl_poll_timeout(otg_regs + OTGSTS, value, 337 (value & OTG_NRDY) != OTG_NRDY, 338 10, 100000); 339 if (ret) 340 dev_warn(parent, "wait OTG ready timeout\n"); 341 } 342 343 return ret; 344 345} 346 347static int cdns_imx_resume(struct device *dev) 348{ 349 struct cdns_imx *data = dev_get_drvdata(dev); 350 351 return clk_bulk_prepare_enable(data->num_clks, data->clks); 352} 353 354static int cdns_imx_suspend(struct device *dev) 355{ 356 struct cdns_imx *data = dev_get_drvdata(dev); 357 358 clk_bulk_disable_unprepare(data->num_clks, data->clks); 359 360 return 0; 361} 362 363 364/* Indicate if the controller was power lost before */ 365static inline bool cdns_imx_is_power_lost(struct cdns_imx *data) 366{ 367 u32 value; 368 369 value = cdns_imx_readl(data, USB3_CORE_CTRL1); 370 if ((value & SW_RESET_MASK) == ALL_SW_RESET) 371 return true; 372 else 373 return false; 374} 375 376static int __maybe_unused cdns_imx_system_suspend(struct device *dev) 377{ 378 pm_runtime_put_sync(dev); 379 return 0; 380} 381 382static int __maybe_unused cdns_imx_system_resume(struct device *dev) 383{ 384 struct cdns_imx *data = dev_get_drvdata(dev); 385 int ret; 386 387 ret = pm_runtime_resume_and_get(dev); 388 if (ret < 0) { 389 dev_err(dev, "Could not get runtime PM.\n"); 390 return ret; 391 } 392 393 if (cdns_imx_is_power_lost(data)) { 394 dev_dbg(dev, "resume from power lost\n"); 395 ret = cdns_imx_noncore_init(data); 396 if (ret) 397 cdns_imx_suspend(dev); 398 } 399 400 return ret; 401} 402 403#else 404static int cdns_imx_platform_suspend(struct device *dev, 405 bool suspend, bool wakeup) 406{ 407 return 0; 408} 409 410#endif /* CONFIG_PM */ 411 412static const struct dev_pm_ops cdns_imx_pm_ops = { 413 SET_RUNTIME_PM_OPS(cdns_imx_suspend, cdns_imx_resume, NULL) 414 SET_SYSTEM_SLEEP_PM_OPS(cdns_imx_system_suspend, cdns_imx_system_resume) 415}; 416 417static const struct of_device_id cdns_imx_of_match[] = { 418 { .compatible = "fsl,imx8qm-usb3", }, 419 {}, 420}; 421MODULE_DEVICE_TABLE(of, cdns_imx_of_match); 422 423static struct platform_driver cdns_imx_driver = { 424 .probe = cdns_imx_probe, 425 .remove_new = cdns_imx_remove, 426 .driver = { 427 .name = "cdns3-imx", 428 .of_match_table = cdns_imx_of_match, 429 .pm = &cdns_imx_pm_ops, 430 }, 431}; 432module_platform_driver(cdns_imx_driver); 433 434MODULE_ALIAS("platform:cdns3-imx"); 435MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>"); 436MODULE_LICENSE("GPL v2"); 437MODULE_DESCRIPTION("Cadence USB3 i.MX Glue Layer"); 438