1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11#include <linux/module.h> 12#include <linux/ioport.h> 13#include <linux/init.h> 14#include <linux/console.h> 15#include <linux/sysrq.h> 16#include <linux/platform_device.h> 17#include <linux/tty.h> 18#include <linux/tty_flip.h> 19#include <linux/serial_core.h> 20#include <linux/serial.h> 21#include <linux/clk.h> 22#include <linux/delay.h> 23#include <linux/ktime.h> 24#include <linux/pinctrl/consumer.h> 25#include <linux/rational.h> 26#include <linux/slab.h> 27#include <linux/of.h> 28#include <linux/io.h> 29#include <linux/dma-mapping.h> 30 31#include <asm/irq.h> 32#include <linux/dma/imx-dma.h> 33 34#include "serial_mctrl_gpio.h" 35 36/* Register definitions */ 37#define URXD0 0x0 /* Receiver Register */ 38#define URTX0 0x40 /* Transmitter Register */ 39#define UCR1 0x80 /* Control Register 1 */ 40#define UCR2 0x84 /* Control Register 2 */ 41#define UCR3 0x88 /* Control Register 3 */ 42#define UCR4 0x8c /* Control Register 4 */ 43#define UFCR 0x90 /* FIFO Control Register */ 44#define USR1 0x94 /* Status Register 1 */ 45#define USR2 0x98 /* Status Register 2 */ 46#define UESC 0x9c /* Escape Character Register */ 47#define UTIM 0xa0 /* Escape Timer Register */ 48#define UBIR 0xa4 /* BRM Incremental Register */ 49#define UBMR 0xa8 /* BRM Modulator Register */ 50#define UBRC 0xac /* Baud Rate Count Register */ 51#define IMX21_ONEMS 0xb0 /* One Millisecond register */ 52#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 53#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 54 55/* UART Control Register Bit Fields.*/ 56#define URXD_DUMMY_READ (1<<16) 57#define URXD_CHARRDY (1<<15) 58#define URXD_ERR (1<<14) 59#define URXD_OVRRUN (1<<13) 60#define URXD_FRMERR (1<<12) 61#define URXD_BRK (1<<11) 62#define URXD_PRERR (1<<10) 63#define URXD_RX_DATA (0xFF<<0) 64#define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 65#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 66#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 67#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 68#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 69#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 70#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 71#define UCR1_IREN (1<<7) /* Infrared interface enable */ 72#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 73#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 74#define UCR1_SNDBRK (1<<4) /* Send break */ 75#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 76#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 77#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 78#define UCR1_DOZE (1<<1) /* Doze */ 79#define UCR1_UARTEN (1<<0) /* UART enabled */ 80#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 81#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 82#define UCR2_CTSC (1<<13) /* CTS pin control */ 83#define UCR2_CTS (1<<12) /* Clear to send */ 84#define UCR2_ESCEN (1<<11) /* Escape enable */ 85#define UCR2_PREN (1<<8) /* Parity enable */ 86#define UCR2_PROE (1<<7) /* Parity odd/even */ 87#define UCR2_STPB (1<<6) /* Stop */ 88#define UCR2_WS (1<<5) /* Word size */ 89#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 90#define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 91#define UCR2_TXEN (1<<2) /* Transmitter enabled */ 92#define UCR2_RXEN (1<<1) /* Receiver enabled */ 93#define UCR2_SRST (1<<0) /* SW reset */ 94#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 95#define UCR3_PARERREN (1<<12) /* Parity enable */ 96#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 97#define UCR3_DSR (1<<10) /* Data set ready */ 98#define UCR3_DCD (1<<9) /* Data carrier detect */ 99#define UCR3_RI (1<<8) /* Ring indicator */ 100#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 101#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 102#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 103#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 104#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 105#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 106#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 107#define UCR3_BPEN (1<<0) /* Preset registers enable */ 108#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 109#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 110#define UCR4_INVR (1<<9) /* Inverted infrared reception */ 111#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 112#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 113#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 114#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 115#define UCR4_IRSC (1<<5) /* IR special case */ 116#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 117#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 118#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 119#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 120#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 121#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 122#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 123#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 124#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 125#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 126#define USR1_RTSS (1<<14) /* RTS pin status */ 127#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 128#define USR1_RTSD (1<<12) /* RTS delta */ 129#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 130#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 131#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 132#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 133#define USR1_DTRD (1<<7) /* DTR Delta */ 134#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 135#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 136#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 137#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 138#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 139#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 140#define USR2_IDLE (1<<12) /* Idle condition */ 141#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 142#define USR2_RIIN (1<<9) /* Ring Indicator Input */ 143#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 144#define USR2_WAKE (1<<7) /* Wake */ 145#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 146#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 147#define USR2_TXDC (1<<3) /* Transmitter complete */ 148#define USR2_BRCD (1<<2) /* Break condition */ 149#define USR2_ORE (1<<1) /* Overrun error */ 150#define USR2_RDR (1<<0) /* Recv data ready */ 151#define UTS_FRCPERR (1<<13) /* Force parity error */ 152#define UTS_LOOP (1<<12) /* Loop tx and rx */ 153#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 154#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 155#define UTS_TXFULL (1<<4) /* TxFIFO full */ 156#define UTS_RXFULL (1<<3) /* RxFIFO full */ 157#define UTS_SOFTRST (1<<0) /* Software reset */ 158 159/* We've been assigned a range on the "Low-density serial ports" major */ 160#define SERIAL_IMX_MAJOR 207 161#define MINOR_START 16 162#define DEV_NAME "ttymxc" 163 164/* 165 * This determines how often we check the modem status signals 166 * for any change. They generally aren't connected to an IRQ 167 * so we have to poll them. We also check immediately before 168 * filling the TX fifo incase CTS has been dropped. 169 */ 170#define MCTRL_TIMEOUT (250*HZ/1000) 171 172#define DRIVER_NAME "IMX-uart" 173 174#define UART_NR 8 175 176/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 177enum imx_uart_type { 178 IMX1_UART, 179 IMX21_UART, 180}; 181 182/* device type dependent stuff */ 183struct imx_uart_data { 184 unsigned uts_reg; 185 enum imx_uart_type devtype; 186}; 187 188enum imx_tx_state { 189 OFF, 190 WAIT_AFTER_RTS, 191 SEND, 192 WAIT_AFTER_SEND, 193}; 194 195struct imx_port { 196 struct uart_port port; 197 struct timer_list timer; 198 unsigned int old_status; 199 unsigned int have_rtscts:1; 200 unsigned int have_rtsgpio:1; 201 unsigned int dte_mode:1; 202 unsigned int inverted_tx:1; 203 unsigned int inverted_rx:1; 204 struct clk *clk_ipg; 205 struct clk *clk_per; 206 const struct imx_uart_data *devdata; 207 208 struct mctrl_gpios *gpios; 209 210 /* counter to stop 0xff flood */ 211 int idle_counter; 212 213 /* DMA fields */ 214 unsigned int dma_is_enabled:1; 215 unsigned int dma_is_rxing:1; 216 unsigned int dma_is_txing:1; 217 struct dma_chan *dma_chan_rx, *dma_chan_tx; 218 struct scatterlist rx_sgl, tx_sgl[2]; 219 void *rx_buf; 220 struct circ_buf rx_ring; 221 unsigned int rx_buf_size; 222 unsigned int rx_period_length; 223 unsigned int rx_periods; 224 dma_cookie_t rx_cookie; 225 unsigned int tx_bytes; 226 unsigned int dma_tx_nents; 227 unsigned int saved_reg[10]; 228 bool context_saved; 229 230 enum imx_tx_state tx_state; 231 struct hrtimer trigger_start_tx; 232 struct hrtimer trigger_stop_tx; 233}; 234 235struct imx_port_ucrs { 236 unsigned int ucr1; 237 unsigned int ucr2; 238 unsigned int ucr3; 239}; 240 241static const struct imx_uart_data imx_uart_imx1_devdata = { 242 .uts_reg = IMX1_UTS, 243 .devtype = IMX1_UART, 244}; 245 246static const struct imx_uart_data imx_uart_imx21_devdata = { 247 .uts_reg = IMX21_UTS, 248 .devtype = IMX21_UART, 249}; 250 251static const struct of_device_id imx_uart_dt_ids[] = { 252 /* 253 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are 254 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the 255 * original imx6q's UART is compatible to fsl,imx21-uart. This driver 256 * doesn't make any distinction between these two variants. 257 */ 258 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, }, 259 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, }, 260 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, }, 261 { /* sentinel */ } 262}; 263MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 264 265static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 266{ 267 writel(val, sport->port.membase + offset); 268} 269 270static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset) 271{ 272 return readl(sport->port.membase + offset); 273} 274 275static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 276{ 277 return sport->devdata->uts_reg; 278} 279 280static inline int imx_uart_is_imx1(struct imx_port *sport) 281{ 282 return sport->devdata->devtype == IMX1_UART; 283} 284 285/* 286 * Save and restore functions for UCR1, UCR2 and UCR3 registers 287 */ 288#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 289static void imx_uart_ucrs_save(struct imx_port *sport, 290 struct imx_port_ucrs *ucr) 291{ 292 /* save control registers */ 293 ucr->ucr1 = imx_uart_readl(sport, UCR1); 294 ucr->ucr2 = imx_uart_readl(sport, UCR2); 295 ucr->ucr3 = imx_uart_readl(sport, UCR3); 296} 297 298static void imx_uart_ucrs_restore(struct imx_port *sport, 299 struct imx_port_ucrs *ucr) 300{ 301 /* restore control registers */ 302 imx_uart_writel(sport, ucr->ucr1, UCR1); 303 imx_uart_writel(sport, ucr->ucr2, UCR2); 304 imx_uart_writel(sport, ucr->ucr3, UCR3); 305} 306#endif 307 308/* called with port.lock taken and irqs caller dependent */ 309static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 310{ 311 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 312 313 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); 314} 315 316/* called with port.lock taken and irqs caller dependent */ 317static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 318{ 319 *ucr2 &= ~UCR2_CTSC; 320 *ucr2 |= UCR2_CTS; 321 322 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); 323} 324 325static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 326{ 327 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 328} 329 330/* called with port.lock taken and irqs off */ 331static void imx_uart_soft_reset(struct imx_port *sport) 332{ 333 int i = 10; 334 u32 ucr2, ubir, ubmr, uts; 335 336 /* 337 * According to the Reference Manual description of the UART SRST bit: 338 * 339 * "Reset the transmit and receive state machines, 340 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 341 * and UTS[6-3]". 342 * 343 * We don't need to restore the old values from USR1, USR2, URXD and 344 * UTXD. UBRC is read only, so only save/restore the other three 345 * registers. 346 */ 347 ubir = imx_uart_readl(sport, UBIR); 348 ubmr = imx_uart_readl(sport, UBMR); 349 uts = imx_uart_readl(sport, IMX21_UTS); 350 351 ucr2 = imx_uart_readl(sport, UCR2); 352 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2); 353 354 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 355 udelay(1); 356 357 /* Restore the registers */ 358 imx_uart_writel(sport, ubir, UBIR); 359 imx_uart_writel(sport, ubmr, UBMR); 360 imx_uart_writel(sport, uts, IMX21_UTS); 361 362 sport->idle_counter = 0; 363} 364 365static void imx_uart_disable_loopback_rs485(struct imx_port *sport) 366{ 367 unsigned int uts; 368 369 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 370 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 371 uts &= ~UTS_LOOP; 372 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 373} 374 375/* called with port.lock taken and irqs off */ 376static void imx_uart_start_rx(struct uart_port *port) 377{ 378 struct imx_port *sport = (struct imx_port *)port; 379 unsigned int ucr1, ucr2; 380 381 ucr1 = imx_uart_readl(sport, UCR1); 382 ucr2 = imx_uart_readl(sport, UCR2); 383 384 ucr2 |= UCR2_RXEN; 385 386 if (sport->dma_is_enabled) { 387 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 388 } else { 389 ucr1 |= UCR1_RRDYEN; 390 ucr2 |= UCR2_ATEN; 391 } 392 393 /* Write UCR2 first as it includes RXEN */ 394 imx_uart_writel(sport, ucr2, UCR2); 395 imx_uart_writel(sport, ucr1, UCR1); 396 imx_uart_disable_loopback_rs485(sport); 397} 398 399/* called with port.lock taken and irqs off */ 400static void imx_uart_stop_tx(struct uart_port *port) 401{ 402 struct imx_port *sport = (struct imx_port *)port; 403 u32 ucr1, ucr4, usr2; 404 405 if (sport->tx_state == OFF) 406 return; 407 408 /* 409 * We are maybe in the SMP context, so if the DMA TX thread is running 410 * on other cpu, we have to wait for it to finish. 411 */ 412 if (sport->dma_is_txing) 413 return; 414 415 ucr1 = imx_uart_readl(sport, UCR1); 416 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 417 418 ucr4 = imx_uart_readl(sport, UCR4); 419 usr2 = imx_uart_readl(sport, USR2); 420 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) { 421 /* The shifter is still busy, so retry once TC triggers */ 422 return; 423 } 424 425 ucr4 &= ~UCR4_TCEN; 426 imx_uart_writel(sport, ucr4, UCR4); 427 428 /* in rs485 mode disable transmitter */ 429 if (port->rs485.flags & SER_RS485_ENABLED) { 430 if (sport->tx_state == SEND) { 431 sport->tx_state = WAIT_AFTER_SEND; 432 433 if (port->rs485.delay_rts_after_send > 0) { 434 start_hrtimer_ms(&sport->trigger_stop_tx, 435 port->rs485.delay_rts_after_send); 436 return; 437 } 438 439 /* continue without any delay */ 440 } 441 442 if (sport->tx_state == WAIT_AFTER_RTS || 443 sport->tx_state == WAIT_AFTER_SEND) { 444 u32 ucr2; 445 446 hrtimer_try_to_cancel(&sport->trigger_start_tx); 447 448 ucr2 = imx_uart_readl(sport, UCR2); 449 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 450 imx_uart_rts_active(sport, &ucr2); 451 else 452 imx_uart_rts_inactive(sport, &ucr2); 453 imx_uart_writel(sport, ucr2, UCR2); 454 455 if (!port->rs485_rx_during_tx_gpio) 456 imx_uart_start_rx(port); 457 458 sport->tx_state = OFF; 459 } 460 } else { 461 sport->tx_state = OFF; 462 } 463} 464 465static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback) 466{ 467 struct imx_port *sport = (struct imx_port *)port; 468 u32 ucr1, ucr2, ucr4, uts; 469 470 ucr1 = imx_uart_readl(sport, UCR1); 471 ucr2 = imx_uart_readl(sport, UCR2); 472 ucr4 = imx_uart_readl(sport, UCR4); 473 474 if (sport->dma_is_enabled) { 475 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 476 } else { 477 ucr1 &= ~UCR1_RRDYEN; 478 ucr2 &= ~UCR2_ATEN; 479 ucr4 &= ~UCR4_OREN; 480 } 481 imx_uart_writel(sport, ucr1, UCR1); 482 imx_uart_writel(sport, ucr4, UCR4); 483 484 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 485 if (port->rs485.flags & SER_RS485_ENABLED && 486 port->rs485.flags & SER_RS485_RTS_ON_SEND && 487 sport->have_rtscts && !sport->have_rtsgpio && loopback) { 488 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 489 uts |= UTS_LOOP; 490 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 491 ucr2 |= UCR2_RXEN; 492 } else { 493 ucr2 &= ~UCR2_RXEN; 494 } 495 496 imx_uart_writel(sport, ucr2, UCR2); 497} 498 499/* called with port.lock taken and irqs off */ 500static void imx_uart_stop_rx(struct uart_port *port) 501{ 502 /* 503 * Stop RX and enable loopback in order to make sure RS485 bus 504 * is not blocked. Se comment in imx_uart_probe(). 505 */ 506 imx_uart_stop_rx_with_loopback_ctrl(port, true); 507} 508 509/* called with port.lock taken and irqs off */ 510static void imx_uart_enable_ms(struct uart_port *port) 511{ 512 struct imx_port *sport = (struct imx_port *)port; 513 514 mod_timer(&sport->timer, jiffies); 515 516 mctrl_gpio_enable_ms(sport->gpios); 517} 518 519static void imx_uart_dma_tx(struct imx_port *sport); 520 521/* called with port.lock taken and irqs off */ 522static inline void imx_uart_transmit_buffer(struct imx_port *sport) 523{ 524 struct circ_buf *xmit = &sport->port.state->xmit; 525 526 if (sport->port.x_char) { 527 /* Send next char */ 528 imx_uart_writel(sport, sport->port.x_char, URTX0); 529 sport->port.icount.tx++; 530 sport->port.x_char = 0; 531 return; 532 } 533 534 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 535 imx_uart_stop_tx(&sport->port); 536 return; 537 } 538 539 if (sport->dma_is_enabled) { 540 u32 ucr1; 541 /* 542 * We've just sent a X-char Ensure the TX DMA is enabled 543 * and the TX IRQ is disabled. 544 **/ 545 ucr1 = imx_uart_readl(sport, UCR1); 546 ucr1 &= ~UCR1_TRDYEN; 547 if (sport->dma_is_txing) { 548 ucr1 |= UCR1_TXDMAEN; 549 imx_uart_writel(sport, ucr1, UCR1); 550 } else { 551 imx_uart_writel(sport, ucr1, UCR1); 552 imx_uart_dma_tx(sport); 553 } 554 555 return; 556 } 557 558 while (!uart_circ_empty(xmit) && 559 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 560 /* send xmit->buf[xmit->tail] 561 * out the port here */ 562 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 563 uart_xmit_advance(&sport->port, 1); 564 } 565 566 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 567 uart_write_wakeup(&sport->port); 568 569 if (uart_circ_empty(xmit)) 570 imx_uart_stop_tx(&sport->port); 571} 572 573static void imx_uart_dma_tx_callback(void *data) 574{ 575 struct imx_port *sport = data; 576 struct scatterlist *sgl = &sport->tx_sgl[0]; 577 struct circ_buf *xmit = &sport->port.state->xmit; 578 unsigned long flags; 579 u32 ucr1; 580 581 uart_port_lock_irqsave(&sport->port, &flags); 582 583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 584 585 ucr1 = imx_uart_readl(sport, UCR1); 586 ucr1 &= ~UCR1_TXDMAEN; 587 imx_uart_writel(sport, ucr1, UCR1); 588 589 uart_xmit_advance(&sport->port, sport->tx_bytes); 590 591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 592 593 sport->dma_is_txing = 0; 594 595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 596 uart_write_wakeup(&sport->port); 597 598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 599 imx_uart_dma_tx(sport); 600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 601 u32 ucr4 = imx_uart_readl(sport, UCR4); 602 ucr4 |= UCR4_TCEN; 603 imx_uart_writel(sport, ucr4, UCR4); 604 } 605 606 uart_port_unlock_irqrestore(&sport->port, flags); 607} 608 609/* called with port.lock taken and irqs off */ 610static void imx_uart_dma_tx(struct imx_port *sport) 611{ 612 struct circ_buf *xmit = &sport->port.state->xmit; 613 struct scatterlist *sgl = sport->tx_sgl; 614 struct dma_async_tx_descriptor *desc; 615 struct dma_chan *chan = sport->dma_chan_tx; 616 struct device *dev = sport->port.dev; 617 u32 ucr1, ucr4; 618 int ret; 619 620 if (sport->dma_is_txing) 621 return; 622 623 ucr4 = imx_uart_readl(sport, UCR4); 624 ucr4 &= ~UCR4_TCEN; 625 imx_uart_writel(sport, ucr4, UCR4); 626 627 sport->tx_bytes = uart_circ_chars_pending(xmit); 628 629 if (xmit->tail < xmit->head || xmit->head == 0) { 630 sport->dma_tx_nents = 1; 631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 632 } else { 633 sport->dma_tx_nents = 2; 634 sg_init_table(sgl, 2); 635 sg_set_buf(sgl, xmit->buf + xmit->tail, 636 UART_XMIT_SIZE - xmit->tail); 637 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 638 } 639 640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 641 if (ret == 0) { 642 dev_err(dev, "DMA mapping error for TX.\n"); 643 return; 644 } 645 desc = dmaengine_prep_slave_sg(chan, sgl, ret, 646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 647 if (!desc) { 648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 649 DMA_TO_DEVICE); 650 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 651 return; 652 } 653 desc->callback = imx_uart_dma_tx_callback; 654 desc->callback_param = sport; 655 656 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 657 uart_circ_chars_pending(xmit)); 658 659 ucr1 = imx_uart_readl(sport, UCR1); 660 ucr1 |= UCR1_TXDMAEN; 661 imx_uart_writel(sport, ucr1, UCR1); 662 663 /* fire it */ 664 sport->dma_is_txing = 1; 665 dmaengine_submit(desc); 666 dma_async_issue_pending(chan); 667 return; 668} 669 670/* called with port.lock taken and irqs off */ 671static void imx_uart_start_tx(struct uart_port *port) 672{ 673 struct imx_port *sport = (struct imx_port *)port; 674 u32 ucr1; 675 676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 677 return; 678 679 /* 680 * We cannot simply do nothing here if sport->tx_state == SEND already 681 * because UCR1_TXMPTYEN might already have been cleared in 682 * imx_uart_stop_tx(), but tx_state is still SEND. 683 */ 684 685 if (port->rs485.flags & SER_RS485_ENABLED) { 686 if (sport->tx_state == OFF) { 687 u32 ucr2 = imx_uart_readl(sport, UCR2); 688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 689 imx_uart_rts_active(sport, &ucr2); 690 else 691 imx_uart_rts_inactive(sport, &ucr2); 692 imx_uart_writel(sport, ucr2, UCR2); 693 694 /* 695 * Since we are about to transmit we can not stop RX 696 * with loopback enabled because that will make our 697 * transmitted data being just looped to RX. 698 */ 699 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && 700 !port->rs485_rx_during_tx_gpio) 701 imx_uart_stop_rx_with_loopback_ctrl(port, false); 702 703 sport->tx_state = WAIT_AFTER_RTS; 704 705 if (port->rs485.delay_rts_before_send > 0) { 706 start_hrtimer_ms(&sport->trigger_start_tx, 707 port->rs485.delay_rts_before_send); 708 return; 709 } 710 711 /* continue without any delay */ 712 } 713 714 if (sport->tx_state == WAIT_AFTER_SEND 715 || sport->tx_state == WAIT_AFTER_RTS) { 716 717 hrtimer_try_to_cancel(&sport->trigger_stop_tx); 718 719 /* 720 * Enable transmitter and shifter empty irq only if DMA 721 * is off. In the DMA case this is done in the 722 * tx-callback. 723 */ 724 if (!sport->dma_is_enabled) { 725 u32 ucr4 = imx_uart_readl(sport, UCR4); 726 ucr4 |= UCR4_TCEN; 727 imx_uart_writel(sport, ucr4, UCR4); 728 } 729 730 sport->tx_state = SEND; 731 } 732 } else { 733 sport->tx_state = SEND; 734 } 735 736 if (!sport->dma_is_enabled) { 737 ucr1 = imx_uart_readl(sport, UCR1); 738 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 739 } 740 741 if (sport->dma_is_enabled) { 742 if (sport->port.x_char) { 743 /* We have X-char to send, so enable TX IRQ and 744 * disable TX DMA to let TX interrupt to send X-char */ 745 ucr1 = imx_uart_readl(sport, UCR1); 746 ucr1 &= ~UCR1_TXDMAEN; 747 ucr1 |= UCR1_TRDYEN; 748 imx_uart_writel(sport, ucr1, UCR1); 749 return; 750 } 751 752 if (!uart_circ_empty(&port->state->xmit) && 753 !uart_tx_stopped(port)) 754 imx_uart_dma_tx(sport); 755 return; 756 } 757} 758 759static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) 760{ 761 struct imx_port *sport = dev_id; 762 u32 usr1; 763 764 imx_uart_writel(sport, USR1_RTSD, USR1); 765 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 766 uart_handle_cts_change(&sport->port, usr1); 767 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 768 769 return IRQ_HANDLED; 770} 771 772static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 773{ 774 struct imx_port *sport = dev_id; 775 irqreturn_t ret; 776 777 uart_port_lock(&sport->port); 778 779 ret = __imx_uart_rtsint(irq, dev_id); 780 781 uart_port_unlock(&sport->port); 782 783 return ret; 784} 785 786static irqreturn_t imx_uart_txint(int irq, void *dev_id) 787{ 788 struct imx_port *sport = dev_id; 789 790 uart_port_lock(&sport->port); 791 imx_uart_transmit_buffer(sport); 792 uart_port_unlock(&sport->port); 793 return IRQ_HANDLED; 794} 795 796/* Check if hardware Rx flood is in progress, and issue soft reset to stop it. 797 * This is to be called from Rx ISRs only when some bytes were actually 798 * received. 799 * 800 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600 801 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of 802 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART 803 * that is terminated by any activity on RxD line, or could be stopped by 804 * issuing soft reset to the UART (just stop/start of RX does not help). Note 805 * that what we do here is sending isolated start bit about 2.4 times shorter 806 * than it is to be on UART configured baud rate. 807 */ 808static void imx_uart_check_flood(struct imx_port *sport, u32 usr2) 809{ 810 /* To detect hardware 0xff flood we monitor RxD line between RX 811 * interrupts to isolate "receiving" of char(s) with no activity 812 * on RxD line, that'd never happen on actual data transfers. 813 * 814 * We use USR2_WAKE bit to check for activity on RxD line, but we have a 815 * race here if we clear USR2_WAKE when receiving of a char is in 816 * progress, so we might get RX interrupt later with USR2_WAKE bit 817 * cleared. Note though that as we don't try to clear USR2_WAKE when we 818 * detected no activity, this race may hide actual activity only once. 819 * 820 * Yet another case where receive interrupt may occur without RxD 821 * activity is expiration of aging timer, so we consider this as well. 822 * 823 * We use 'idle_counter' to ensure that we got at least so many RX 824 * interrupts without any detected activity on RxD line. 2 cases 825 * described plus 1 to be on the safe side gives us a margin of 3, 826 * below. In practice I was not able to produce a false positive to 827 * induce soft reset at regular data transfers even using 1 as the 828 * margin, so 3 is actually very strong. 829 * 830 * We count interrupts, not chars in 'idle-counter' for simplicity. 831 */ 832 833 if (usr2 & USR2_WAKE) { 834 imx_uart_writel(sport, USR2_WAKE, USR2); 835 sport->idle_counter = 0; 836 } else if (++sport->idle_counter > 3) { 837 dev_warn(sport->port.dev, "RX flood detected: soft reset."); 838 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ 839 } 840} 841 842static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) 843{ 844 struct imx_port *sport = dev_id; 845 struct tty_port *port = &sport->port.state->port; 846 u32 usr2, rx; 847 848 /* If we received something, check for 0xff flood */ 849 usr2 = imx_uart_readl(sport, USR2); 850 if (usr2 & USR2_RDR) 851 imx_uart_check_flood(sport, usr2); 852 853 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { 854 unsigned int flg = TTY_NORMAL; 855 sport->port.icount.rx++; 856 857 if (unlikely(rx & URXD_ERR)) { 858 if (rx & URXD_BRK) { 859 sport->port.icount.brk++; 860 if (uart_handle_break(&sport->port)) 861 continue; 862 } 863 else if (rx & URXD_PRERR) 864 sport->port.icount.parity++; 865 else if (rx & URXD_FRMERR) 866 sport->port.icount.frame++; 867 if (rx & URXD_OVRRUN) 868 sport->port.icount.overrun++; 869 870 if (rx & sport->port.ignore_status_mask) 871 continue; 872 873 rx &= (sport->port.read_status_mask | 0xFF); 874 875 if (rx & URXD_BRK) 876 flg = TTY_BREAK; 877 else if (rx & URXD_PRERR) 878 flg = TTY_PARITY; 879 else if (rx & URXD_FRMERR) 880 flg = TTY_FRAME; 881 if (rx & URXD_OVRRUN) 882 flg = TTY_OVERRUN; 883 884 sport->port.sysrq = 0; 885 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { 886 continue; 887 } 888 889 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 890 continue; 891 892 if (tty_insert_flip_char(port, rx, flg) == 0) 893 sport->port.icount.buf_overrun++; 894 } 895 896 tty_flip_buffer_push(port); 897 898 return IRQ_HANDLED; 899} 900 901static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 902{ 903 struct imx_port *sport = dev_id; 904 irqreturn_t ret; 905 906 uart_port_lock(&sport->port); 907 908 ret = __imx_uart_rxint(irq, dev_id); 909 910 uart_port_unlock(&sport->port); 911 912 return ret; 913} 914 915static void imx_uart_clear_rx_errors(struct imx_port *sport); 916 917/* 918 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 919 */ 920static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 921{ 922 unsigned int tmp = TIOCM_DSR; 923 unsigned usr1 = imx_uart_readl(sport, USR1); 924 unsigned usr2 = imx_uart_readl(sport, USR2); 925 926 if (usr1 & USR1_RTSS) 927 tmp |= TIOCM_CTS; 928 929 /* in DCE mode DCDIN is always 0 */ 930 if (!(usr2 & USR2_DCDIN)) 931 tmp |= TIOCM_CAR; 932 933 if (sport->dte_mode) 934 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 935 tmp |= TIOCM_RI; 936 937 return tmp; 938} 939 940/* 941 * Handle any change of modem status signal since we were last called. 942 */ 943static void imx_uart_mctrl_check(struct imx_port *sport) 944{ 945 unsigned int status, changed; 946 947 status = imx_uart_get_hwmctrl(sport); 948 changed = status ^ sport->old_status; 949 950 if (changed == 0) 951 return; 952 953 sport->old_status = status; 954 955 if (changed & TIOCM_RI && status & TIOCM_RI) 956 sport->port.icount.rng++; 957 if (changed & TIOCM_DSR) 958 sport->port.icount.dsr++; 959 if (changed & TIOCM_CAR) 960 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 961 if (changed & TIOCM_CTS) 962 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 963 964 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 965} 966 967static irqreturn_t imx_uart_int(int irq, void *dev_id) 968{ 969 struct imx_port *sport = dev_id; 970 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 971 irqreturn_t ret = IRQ_NONE; 972 973 uart_port_lock(&sport->port); 974 975 usr1 = imx_uart_readl(sport, USR1); 976 usr2 = imx_uart_readl(sport, USR2); 977 ucr1 = imx_uart_readl(sport, UCR1); 978 ucr2 = imx_uart_readl(sport, UCR2); 979 ucr3 = imx_uart_readl(sport, UCR3); 980 ucr4 = imx_uart_readl(sport, UCR4); 981 982 /* 983 * Even if a condition is true that can trigger an irq only handle it if 984 * the respective irq source is enabled. This prevents some undesired 985 * actions, for example if a character that sits in the RX FIFO and that 986 * should be fetched via DMA is tried to be fetched using PIO. Or the 987 * receiver is currently off and so reading from URXD0 results in an 988 * exception. So just mask the (raw) status bits for disabled irqs. 989 */ 990 if ((ucr1 & UCR1_RRDYEN) == 0) 991 usr1 &= ~USR1_RRDY; 992 if ((ucr2 & UCR2_ATEN) == 0) 993 usr1 &= ~USR1_AGTIM; 994 if ((ucr1 & UCR1_TRDYEN) == 0) 995 usr1 &= ~USR1_TRDY; 996 if ((ucr4 & UCR4_TCEN) == 0) 997 usr2 &= ~USR2_TXDC; 998 if ((ucr3 & UCR3_DTRDEN) == 0) 999 usr1 &= ~USR1_DTRD; 1000 if ((ucr1 & UCR1_RTSDEN) == 0) 1001 usr1 &= ~USR1_RTSD; 1002 if ((ucr3 & UCR3_AWAKEN) == 0) 1003 usr1 &= ~USR1_AWAKE; 1004 if ((ucr4 & UCR4_OREN) == 0) 1005 usr2 &= ~USR2_ORE; 1006 1007 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 1008 imx_uart_writel(sport, USR1_AGTIM, USR1); 1009 1010 __imx_uart_rxint(irq, dev_id); 1011 ret = IRQ_HANDLED; 1012 } 1013 1014 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 1015 imx_uart_transmit_buffer(sport); 1016 ret = IRQ_HANDLED; 1017 } 1018 1019 if (usr1 & USR1_DTRD) { 1020 imx_uart_writel(sport, USR1_DTRD, USR1); 1021 1022 imx_uart_mctrl_check(sport); 1023 1024 ret = IRQ_HANDLED; 1025 } 1026 1027 if (usr1 & USR1_RTSD) { 1028 __imx_uart_rtsint(irq, dev_id); 1029 ret = IRQ_HANDLED; 1030 } 1031 1032 if (usr1 & USR1_AWAKE) { 1033 imx_uart_writel(sport, USR1_AWAKE, USR1); 1034 ret = IRQ_HANDLED; 1035 } 1036 1037 if (usr2 & USR2_ORE) { 1038 sport->port.icount.overrun++; 1039 imx_uart_writel(sport, USR2_ORE, USR2); 1040 ret = IRQ_HANDLED; 1041 } 1042 1043 uart_port_unlock(&sport->port); 1044 1045 return ret; 1046} 1047 1048/* 1049 * Return TIOCSER_TEMT when transmitter is not busy. 1050 */ 1051static unsigned int imx_uart_tx_empty(struct uart_port *port) 1052{ 1053 struct imx_port *sport = (struct imx_port *)port; 1054 unsigned int ret; 1055 1056 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 1057 1058 /* If the TX DMA is working, return 0. */ 1059 if (sport->dma_is_txing) 1060 ret = 0; 1061 1062 return ret; 1063} 1064 1065/* called with port.lock taken and irqs off */ 1066static unsigned int imx_uart_get_mctrl(struct uart_port *port) 1067{ 1068 struct imx_port *sport = (struct imx_port *)port; 1069 unsigned int ret = imx_uart_get_hwmctrl(sport); 1070 1071 mctrl_gpio_get(sport->gpios, &ret); 1072 1073 return ret; 1074} 1075 1076/* called with port.lock taken and irqs off */ 1077static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1078{ 1079 struct imx_port *sport = (struct imx_port *)port; 1080 u32 ucr3, uts; 1081 1082 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 1083 u32 ucr2; 1084 1085 /* 1086 * Turn off autoRTS if RTS is lowered and restore autoRTS 1087 * setting if RTS is raised. 1088 */ 1089 ucr2 = imx_uart_readl(sport, UCR2); 1090 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 1091 if (mctrl & TIOCM_RTS) { 1092 ucr2 |= UCR2_CTS; 1093 /* 1094 * UCR2_IRTS is unset if and only if the port is 1095 * configured for CRTSCTS, so we use inverted UCR2_IRTS 1096 * to get the state to restore to. 1097 */ 1098 if (!(ucr2 & UCR2_IRTS)) 1099 ucr2 |= UCR2_CTSC; 1100 } 1101 imx_uart_writel(sport, ucr2, UCR2); 1102 } 1103 1104 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 1105 if (!(mctrl & TIOCM_DTR)) 1106 ucr3 |= UCR3_DSR; 1107 imx_uart_writel(sport, ucr3, UCR3); 1108 1109 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 1110 if (mctrl & TIOCM_LOOP) 1111 uts |= UTS_LOOP; 1112 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1113 1114 mctrl_gpio_set(sport->gpios, mctrl); 1115} 1116 1117/* 1118 * Interrupts always disabled. 1119 */ 1120static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1121{ 1122 struct imx_port *sport = (struct imx_port *)port; 1123 unsigned long flags; 1124 u32 ucr1; 1125 1126 uart_port_lock_irqsave(&sport->port, &flags); 1127 1128 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1129 1130 if (break_state != 0) 1131 ucr1 |= UCR1_SNDBRK; 1132 1133 imx_uart_writel(sport, ucr1, UCR1); 1134 1135 uart_port_unlock_irqrestore(&sport->port, flags); 1136} 1137 1138/* 1139 * This is our per-port timeout handler, for checking the 1140 * modem status signals. 1141 */ 1142static void imx_uart_timeout(struct timer_list *t) 1143{ 1144 struct imx_port *sport = from_timer(sport, t, timer); 1145 unsigned long flags; 1146 1147 if (sport->port.state) { 1148 uart_port_lock_irqsave(&sport->port, &flags); 1149 imx_uart_mctrl_check(sport); 1150 uart_port_unlock_irqrestore(&sport->port, flags); 1151 1152 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1153 } 1154} 1155 1156/* 1157 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1158 * [1] the RX DMA buffer is full. 1159 * [2] the aging timer expires 1160 * 1161 * Condition [2] is triggered when a character has been sitting in the FIFO 1162 * for at least 8 byte durations. 1163 */ 1164static void imx_uart_dma_rx_callback(void *data) 1165{ 1166 struct imx_port *sport = data; 1167 struct dma_chan *chan = sport->dma_chan_rx; 1168 struct scatterlist *sgl = &sport->rx_sgl; 1169 struct tty_port *port = &sport->port.state->port; 1170 struct dma_tx_state state; 1171 struct circ_buf *rx_ring = &sport->rx_ring; 1172 enum dma_status status; 1173 unsigned int w_bytes = 0; 1174 unsigned int r_bytes; 1175 unsigned int bd_size; 1176 1177 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1178 1179 if (status == DMA_ERROR) { 1180 uart_port_lock(&sport->port); 1181 imx_uart_clear_rx_errors(sport); 1182 uart_port_unlock(&sport->port); 1183 return; 1184 } 1185 1186 /* 1187 * The state-residue variable represents the empty space 1188 * relative to the entire buffer. Taking this in consideration 1189 * the head is always calculated base on the buffer total 1190 * length - DMA transaction residue. The UART script from the 1191 * SDMA firmware will jump to the next buffer descriptor, 1192 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1193 * Taking this in consideration the tail is always at the 1194 * beginning of the buffer descriptor that contains the head. 1195 */ 1196 1197 /* Calculate the head */ 1198 rx_ring->head = sg_dma_len(sgl) - state.residue; 1199 1200 /* Calculate the tail. */ 1201 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1202 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1203 1204 if (rx_ring->head <= sg_dma_len(sgl) && 1205 rx_ring->head > rx_ring->tail) { 1206 1207 /* Move data from tail to head */ 1208 r_bytes = rx_ring->head - rx_ring->tail; 1209 1210 /* If we received something, check for 0xff flood */ 1211 uart_port_lock(&sport->port); 1212 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2)); 1213 uart_port_unlock(&sport->port); 1214 1215 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1216 1217 /* CPU claims ownership of RX DMA buffer */ 1218 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1219 DMA_FROM_DEVICE); 1220 1221 w_bytes = tty_insert_flip_string(port, 1222 sport->rx_buf + rx_ring->tail, r_bytes); 1223 1224 /* UART retrieves ownership of RX DMA buffer */ 1225 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1226 DMA_FROM_DEVICE); 1227 1228 if (w_bytes != r_bytes) 1229 sport->port.icount.buf_overrun++; 1230 1231 sport->port.icount.rx += w_bytes; 1232 } 1233 } else { 1234 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1235 WARN_ON(rx_ring->head <= rx_ring->tail); 1236 } 1237 1238 if (w_bytes) { 1239 tty_flip_buffer_push(port); 1240 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1241 } 1242} 1243 1244static int imx_uart_start_rx_dma(struct imx_port *sport) 1245{ 1246 struct scatterlist *sgl = &sport->rx_sgl; 1247 struct dma_chan *chan = sport->dma_chan_rx; 1248 struct device *dev = sport->port.dev; 1249 struct dma_async_tx_descriptor *desc; 1250 int ret; 1251 1252 sport->rx_ring.head = 0; 1253 sport->rx_ring.tail = 0; 1254 1255 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); 1256 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1257 if (ret == 0) { 1258 dev_err(dev, "DMA mapping error for RX.\n"); 1259 return -EINVAL; 1260 } 1261 1262 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1263 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1264 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1265 1266 if (!desc) { 1267 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1268 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1269 return -EINVAL; 1270 } 1271 desc->callback = imx_uart_dma_rx_callback; 1272 desc->callback_param = sport; 1273 1274 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1275 sport->dma_is_rxing = 1; 1276 sport->rx_cookie = dmaengine_submit(desc); 1277 dma_async_issue_pending(chan); 1278 return 0; 1279} 1280 1281static void imx_uart_clear_rx_errors(struct imx_port *sport) 1282{ 1283 struct tty_port *port = &sport->port.state->port; 1284 u32 usr1, usr2; 1285 1286 usr1 = imx_uart_readl(sport, USR1); 1287 usr2 = imx_uart_readl(sport, USR2); 1288 1289 if (usr2 & USR2_BRCD) { 1290 sport->port.icount.brk++; 1291 imx_uart_writel(sport, USR2_BRCD, USR2); 1292 uart_handle_break(&sport->port); 1293 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1294 sport->port.icount.buf_overrun++; 1295 tty_flip_buffer_push(port); 1296 } else { 1297 if (usr1 & USR1_FRAMERR) { 1298 sport->port.icount.frame++; 1299 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1300 } else if (usr1 & USR1_PARITYERR) { 1301 sport->port.icount.parity++; 1302 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1303 } 1304 } 1305 1306 if (usr2 & USR2_ORE) { 1307 sport->port.icount.overrun++; 1308 imx_uart_writel(sport, USR2_ORE, USR2); 1309 } 1310 1311 sport->idle_counter = 0; 1312 1313} 1314 1315#define TXTL_DEFAULT 2 /* reset default */ 1316#define RXTL_DEFAULT 8 /* 8 characters or aging timer */ 1317#define TXTL_DMA 8 /* DMA burst setting */ 1318#define RXTL_DMA 9 /* DMA burst setting */ 1319 1320static void imx_uart_setup_ufcr(struct imx_port *sport, 1321 unsigned char txwl, unsigned char rxwl) 1322{ 1323 unsigned int val; 1324 1325 /* set receiver / transmitter trigger level */ 1326 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1327 val |= txwl << UFCR_TXTL_SHF | rxwl; 1328 imx_uart_writel(sport, val, UFCR); 1329} 1330 1331static void imx_uart_dma_exit(struct imx_port *sport) 1332{ 1333 if (sport->dma_chan_rx) { 1334 dmaengine_terminate_sync(sport->dma_chan_rx); 1335 dma_release_channel(sport->dma_chan_rx); 1336 sport->dma_chan_rx = NULL; 1337 sport->rx_cookie = -EINVAL; 1338 kfree(sport->rx_buf); 1339 sport->rx_buf = NULL; 1340 } 1341 1342 if (sport->dma_chan_tx) { 1343 dmaengine_terminate_sync(sport->dma_chan_tx); 1344 dma_release_channel(sport->dma_chan_tx); 1345 sport->dma_chan_tx = NULL; 1346 } 1347} 1348 1349static int imx_uart_dma_init(struct imx_port *sport) 1350{ 1351 struct dma_slave_config slave_config = {}; 1352 struct device *dev = sport->port.dev; 1353 struct dma_chan *chan; 1354 int ret; 1355 1356 /* Prepare for RX : */ 1357 chan = dma_request_chan(dev, "rx"); 1358 if (IS_ERR(chan)) { 1359 dev_dbg(dev, "cannot get the DMA channel.\n"); 1360 sport->dma_chan_rx = NULL; 1361 ret = PTR_ERR(chan); 1362 goto err; 1363 } 1364 sport->dma_chan_rx = chan; 1365 1366 slave_config.direction = DMA_DEV_TO_MEM; 1367 slave_config.src_addr = sport->port.mapbase + URXD0; 1368 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1369 /* one byte less than the watermark level to enable the aging timer */ 1370 slave_config.src_maxburst = RXTL_DMA - 1; 1371 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1372 if (ret) { 1373 dev_err(dev, "error in RX dma configuration.\n"); 1374 goto err; 1375 } 1376 1377 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; 1378 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); 1379 if (!sport->rx_buf) { 1380 ret = -ENOMEM; 1381 goto err; 1382 } 1383 sport->rx_ring.buf = sport->rx_buf; 1384 1385 /* Prepare for TX : */ 1386 chan = dma_request_chan(dev, "tx"); 1387 if (IS_ERR(chan)) { 1388 dev_err(dev, "cannot get the TX DMA channel!\n"); 1389 sport->dma_chan_tx = NULL; 1390 ret = PTR_ERR(chan); 1391 goto err; 1392 } 1393 sport->dma_chan_tx = chan; 1394 1395 slave_config.direction = DMA_MEM_TO_DEV; 1396 slave_config.dst_addr = sport->port.mapbase + URTX0; 1397 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1398 slave_config.dst_maxburst = TXTL_DMA; 1399 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1400 if (ret) { 1401 dev_err(dev, "error in TX dma configuration."); 1402 goto err; 1403 } 1404 1405 return 0; 1406err: 1407 imx_uart_dma_exit(sport); 1408 return ret; 1409} 1410 1411static void imx_uart_enable_dma(struct imx_port *sport) 1412{ 1413 u32 ucr1; 1414 1415 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1416 1417 /* set UCR1 */ 1418 ucr1 = imx_uart_readl(sport, UCR1); 1419 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1420 imx_uart_writel(sport, ucr1, UCR1); 1421 1422 sport->dma_is_enabled = 1; 1423} 1424 1425static void imx_uart_disable_dma(struct imx_port *sport) 1426{ 1427 u32 ucr1; 1428 1429 /* clear UCR1 */ 1430 ucr1 = imx_uart_readl(sport, UCR1); 1431 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1432 imx_uart_writel(sport, ucr1, UCR1); 1433 1434 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1435 1436 sport->dma_is_enabled = 0; 1437} 1438 1439/* half the RX buffer size */ 1440#define CTSTL 16 1441 1442static int imx_uart_startup(struct uart_port *port) 1443{ 1444 struct imx_port *sport = (struct imx_port *)port; 1445 int retval; 1446 unsigned long flags; 1447 int dma_is_inited = 0; 1448 u32 ucr1, ucr2, ucr3, ucr4; 1449 1450 retval = clk_prepare_enable(sport->clk_per); 1451 if (retval) 1452 return retval; 1453 retval = clk_prepare_enable(sport->clk_ipg); 1454 if (retval) { 1455 clk_disable_unprepare(sport->clk_per); 1456 return retval; 1457 } 1458 1459 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1460 1461 /* disable the DREN bit (Data Ready interrupt enable) before 1462 * requesting IRQs 1463 */ 1464 ucr4 = imx_uart_readl(sport, UCR4); 1465 1466 /* set the trigger level for CTS */ 1467 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1468 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1469 1470 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1471 1472 /* Can we enable the DMA support? */ 1473 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) { 1474 lockdep_set_subclass(&port->lock, 1); 1475 dma_is_inited = 1; 1476 } 1477 1478 uart_port_lock_irqsave(&sport->port, &flags); 1479 1480 /* Reset fifo's and state machines */ 1481 imx_uart_soft_reset(sport); 1482 1483 /* 1484 * Finally, clear and enable interrupts 1485 */ 1486 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1487 imx_uart_writel(sport, USR2_ORE, USR2); 1488 1489 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1490 ucr1 |= UCR1_UARTEN; 1491 if (sport->have_rtscts) 1492 ucr1 |= UCR1_RTSDEN; 1493 1494 imx_uart_writel(sport, ucr1, UCR1); 1495 1496 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); 1497 if (!dma_is_inited) 1498 ucr4 |= UCR4_OREN; 1499 if (sport->inverted_rx) 1500 ucr4 |= UCR4_INVR; 1501 imx_uart_writel(sport, ucr4, UCR4); 1502 1503 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; 1504 /* 1505 * configure tx polarity before enabling tx 1506 */ 1507 if (sport->inverted_tx) 1508 ucr3 |= UCR3_INVT; 1509 1510 if (!imx_uart_is_imx1(sport)) { 1511 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1512 1513 if (sport->dte_mode) 1514 /* disable broken interrupts */ 1515 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1516 } 1517 imx_uart_writel(sport, ucr3, UCR3); 1518 1519 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1520 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1521 if (!sport->have_rtscts) 1522 ucr2 |= UCR2_IRTS; 1523 /* 1524 * make sure the edge sensitive RTS-irq is disabled, 1525 * we're using RTSD instead. 1526 */ 1527 if (!imx_uart_is_imx1(sport)) 1528 ucr2 &= ~UCR2_RTSEN; 1529 imx_uart_writel(sport, ucr2, UCR2); 1530 1531 /* 1532 * Enable modem status interrupts 1533 */ 1534 imx_uart_enable_ms(&sport->port); 1535 1536 if (dma_is_inited) { 1537 imx_uart_enable_dma(sport); 1538 imx_uart_start_rx_dma(sport); 1539 } else { 1540 ucr1 = imx_uart_readl(sport, UCR1); 1541 ucr1 |= UCR1_RRDYEN; 1542 imx_uart_writel(sport, ucr1, UCR1); 1543 1544 ucr2 = imx_uart_readl(sport, UCR2); 1545 ucr2 |= UCR2_ATEN; 1546 imx_uart_writel(sport, ucr2, UCR2); 1547 } 1548 1549 imx_uart_disable_loopback_rs485(sport); 1550 1551 uart_port_unlock_irqrestore(&sport->port, flags); 1552 1553 return 0; 1554} 1555 1556static void imx_uart_shutdown(struct uart_port *port) 1557{ 1558 struct imx_port *sport = (struct imx_port *)port; 1559 unsigned long flags; 1560 u32 ucr1, ucr2, ucr4, uts; 1561 1562 if (sport->dma_is_enabled) { 1563 dmaengine_terminate_sync(sport->dma_chan_tx); 1564 if (sport->dma_is_txing) { 1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1566 sport->dma_tx_nents, DMA_TO_DEVICE); 1567 sport->dma_is_txing = 0; 1568 } 1569 dmaengine_terminate_sync(sport->dma_chan_rx); 1570 if (sport->dma_is_rxing) { 1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1572 1, DMA_FROM_DEVICE); 1573 sport->dma_is_rxing = 0; 1574 } 1575 1576 uart_port_lock_irqsave(&sport->port, &flags); 1577 imx_uart_stop_tx(port); 1578 imx_uart_stop_rx(port); 1579 imx_uart_disable_dma(sport); 1580 uart_port_unlock_irqrestore(&sport->port, flags); 1581 imx_uart_dma_exit(sport); 1582 } 1583 1584 mctrl_gpio_disable_ms(sport->gpios); 1585 1586 uart_port_lock_irqsave(&sport->port, &flags); 1587 ucr2 = imx_uart_readl(sport, UCR2); 1588 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1589 imx_uart_writel(sport, ucr2, UCR2); 1590 uart_port_unlock_irqrestore(&sport->port, flags); 1591 1592 /* 1593 * Stop our timer. 1594 */ 1595 del_timer_sync(&sport->timer); 1596 1597 /* 1598 * Disable all interrupts, port and break condition. 1599 */ 1600 1601 uart_port_lock_irqsave(&sport->port, &flags); 1602 1603 ucr1 = imx_uart_readl(sport, UCR1); 1604 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | 1605 UCR1_ATDMAEN | UCR1_SNDBRK); 1606 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ 1607 if (port->rs485.flags & SER_RS485_ENABLED && 1608 port->rs485.flags & SER_RS485_RTS_ON_SEND && 1609 sport->have_rtscts && !sport->have_rtsgpio) { 1610 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 1611 uts |= UTS_LOOP; 1612 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 1613 ucr1 |= UCR1_UARTEN; 1614 } else { 1615 ucr1 &= ~UCR1_UARTEN; 1616 } 1617 imx_uart_writel(sport, ucr1, UCR1); 1618 1619 ucr4 = imx_uart_readl(sport, UCR4); 1620 ucr4 &= ~UCR4_TCEN; 1621 imx_uart_writel(sport, ucr4, UCR4); 1622 1623 uart_port_unlock_irqrestore(&sport->port, flags); 1624 1625 clk_disable_unprepare(sport->clk_per); 1626 clk_disable_unprepare(sport->clk_ipg); 1627} 1628 1629/* called with port.lock taken and irqs off */ 1630static void imx_uart_flush_buffer(struct uart_port *port) 1631{ 1632 struct imx_port *sport = (struct imx_port *)port; 1633 struct scatterlist *sgl = &sport->tx_sgl[0]; 1634 1635 if (!sport->dma_chan_tx) 1636 return; 1637 1638 sport->tx_bytes = 0; 1639 dmaengine_terminate_all(sport->dma_chan_tx); 1640 if (sport->dma_is_txing) { 1641 u32 ucr1; 1642 1643 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1644 DMA_TO_DEVICE); 1645 ucr1 = imx_uart_readl(sport, UCR1); 1646 ucr1 &= ~UCR1_TXDMAEN; 1647 imx_uart_writel(sport, ucr1, UCR1); 1648 sport->dma_is_txing = 0; 1649 } 1650 1651 imx_uart_soft_reset(sport); 1652 1653} 1654 1655static void 1656imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1657 const struct ktermios *old) 1658{ 1659 struct imx_port *sport = (struct imx_port *)port; 1660 unsigned long flags; 1661 u32 ucr2, old_ucr2, ufcr; 1662 unsigned int baud, quot; 1663 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1664 unsigned long div; 1665 unsigned long num, denom, old_ubir, old_ubmr; 1666 uint64_t tdiv64; 1667 1668 /* 1669 * We only support CS7 and CS8. 1670 */ 1671 while ((termios->c_cflag & CSIZE) != CS7 && 1672 (termios->c_cflag & CSIZE) != CS8) { 1673 termios->c_cflag &= ~CSIZE; 1674 termios->c_cflag |= old_csize; 1675 old_csize = CS8; 1676 } 1677 1678 del_timer_sync(&sport->timer); 1679 1680 /* 1681 * Ask the core to calculate the divisor for us. 1682 */ 1683 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1684 quot = uart_get_divisor(port, baud); 1685 1686 uart_port_lock_irqsave(&sport->port, &flags); 1687 1688 /* 1689 * Read current UCR2 and save it for future use, then clear all the bits 1690 * except those we will or may need to preserve. 1691 */ 1692 old_ucr2 = imx_uart_readl(sport, UCR2); 1693 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1694 1695 ucr2 |= UCR2_SRST | UCR2_IRTS; 1696 if ((termios->c_cflag & CSIZE) == CS8) 1697 ucr2 |= UCR2_WS; 1698 1699 if (!sport->have_rtscts) 1700 termios->c_cflag &= ~CRTSCTS; 1701 1702 if (port->rs485.flags & SER_RS485_ENABLED) { 1703 /* 1704 * RTS is mandatory for rs485 operation, so keep 1705 * it under manual control and keep transmitter 1706 * disabled. 1707 */ 1708 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1709 imx_uart_rts_active(sport, &ucr2); 1710 else 1711 imx_uart_rts_inactive(sport, &ucr2); 1712 1713 } else if (termios->c_cflag & CRTSCTS) { 1714 /* 1715 * Only let receiver control RTS output if we were not requested 1716 * to have RTS inactive (which then should take precedence). 1717 */ 1718 if (ucr2 & UCR2_CTS) 1719 ucr2 |= UCR2_CTSC; 1720 } 1721 1722 if (termios->c_cflag & CRTSCTS) 1723 ucr2 &= ~UCR2_IRTS; 1724 if (termios->c_cflag & CSTOPB) 1725 ucr2 |= UCR2_STPB; 1726 if (termios->c_cflag & PARENB) { 1727 ucr2 |= UCR2_PREN; 1728 if (termios->c_cflag & PARODD) 1729 ucr2 |= UCR2_PROE; 1730 } 1731 1732 sport->port.read_status_mask = 0; 1733 if (termios->c_iflag & INPCK) 1734 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1735 if (termios->c_iflag & (BRKINT | PARMRK)) 1736 sport->port.read_status_mask |= URXD_BRK; 1737 1738 /* 1739 * Characters to ignore 1740 */ 1741 sport->port.ignore_status_mask = 0; 1742 if (termios->c_iflag & IGNPAR) 1743 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1744 if (termios->c_iflag & IGNBRK) { 1745 sport->port.ignore_status_mask |= URXD_BRK; 1746 /* 1747 * If we're ignoring parity and break indicators, 1748 * ignore overruns too (for real raw support). 1749 */ 1750 if (termios->c_iflag & IGNPAR) 1751 sport->port.ignore_status_mask |= URXD_OVRRUN; 1752 } 1753 1754 if ((termios->c_cflag & CREAD) == 0) 1755 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1756 1757 /* 1758 * Update the per-port timeout. 1759 */ 1760 uart_update_timeout(port, termios->c_cflag, baud); 1761 1762 /* custom-baudrate handling */ 1763 div = sport->port.uartclk / (baud * 16); 1764 if (baud == 38400 && quot != div) 1765 baud = sport->port.uartclk / (quot * 16); 1766 1767 div = sport->port.uartclk / (baud * 16); 1768 if (div > 7) 1769 div = 7; 1770 if (!div) 1771 div = 1; 1772 1773 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1774 1 << 16, 1 << 16, &num, &denom); 1775 1776 tdiv64 = sport->port.uartclk; 1777 tdiv64 *= num; 1778 do_div(tdiv64, denom * 16 * div); 1779 tty_termios_encode_baud_rate(termios, 1780 (speed_t)tdiv64, (speed_t)tdiv64); 1781 1782 num -= 1; 1783 denom -= 1; 1784 1785 ufcr = imx_uart_readl(sport, UFCR); 1786 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1787 imx_uart_writel(sport, ufcr, UFCR); 1788 1789 /* 1790 * Two registers below should always be written both and in this 1791 * particular order. One consequence is that we need to check if any of 1792 * them changes and then update both. We do need the check for change 1793 * as even writing the same values seem to "restart" 1794 * transmission/receiving logic in the hardware, that leads to data 1795 * breakage even when rate doesn't in fact change. E.g., user switches 1796 * RTS/CTS handshake and suddenly gets broken bytes. 1797 */ 1798 old_ubir = imx_uart_readl(sport, UBIR); 1799 old_ubmr = imx_uart_readl(sport, UBMR); 1800 if (old_ubir != num || old_ubmr != denom) { 1801 imx_uart_writel(sport, num, UBIR); 1802 imx_uart_writel(sport, denom, UBMR); 1803 } 1804 1805 if (!imx_uart_is_imx1(sport)) 1806 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1807 IMX21_ONEMS); 1808 1809 imx_uart_writel(sport, ucr2, UCR2); 1810 1811 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1812 imx_uart_enable_ms(&sport->port); 1813 1814 uart_port_unlock_irqrestore(&sport->port, flags); 1815} 1816 1817static const char *imx_uart_type(struct uart_port *port) 1818{ 1819 return port->type == PORT_IMX ? "IMX" : NULL; 1820} 1821 1822/* 1823 * Configure/autoconfigure the port. 1824 */ 1825static void imx_uart_config_port(struct uart_port *port, int flags) 1826{ 1827 if (flags & UART_CONFIG_TYPE) 1828 port->type = PORT_IMX; 1829} 1830 1831/* 1832 * Verify the new serial_struct (for TIOCSSERIAL). 1833 * The only change we allow are to the flags and type, and 1834 * even then only between PORT_IMX and PORT_UNKNOWN 1835 */ 1836static int 1837imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1838{ 1839 int ret = 0; 1840 1841 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1842 ret = -EINVAL; 1843 if (port->irq != ser->irq) 1844 ret = -EINVAL; 1845 if (ser->io_type != UPIO_MEM) 1846 ret = -EINVAL; 1847 if (port->uartclk / 16 != ser->baud_base) 1848 ret = -EINVAL; 1849 if (port->mapbase != (unsigned long)ser->iomem_base) 1850 ret = -EINVAL; 1851 if (port->iobase != ser->port) 1852 ret = -EINVAL; 1853 if (ser->hub6 != 0) 1854 ret = -EINVAL; 1855 return ret; 1856} 1857 1858#if defined(CONFIG_CONSOLE_POLL) 1859 1860static int imx_uart_poll_init(struct uart_port *port) 1861{ 1862 struct imx_port *sport = (struct imx_port *)port; 1863 unsigned long flags; 1864 u32 ucr1, ucr2; 1865 int retval; 1866 1867 retval = clk_prepare_enable(sport->clk_ipg); 1868 if (retval) 1869 return retval; 1870 retval = clk_prepare_enable(sport->clk_per); 1871 if (retval) 1872 clk_disable_unprepare(sport->clk_ipg); 1873 1874 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1875 1876 uart_port_lock_irqsave(&sport->port, &flags); 1877 1878 /* 1879 * Be careful about the order of enabling bits here. First enable the 1880 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1881 * This prevents that a character that already sits in the RX fifo is 1882 * triggering an irq but the try to fetch it from there results in an 1883 * exception because UARTEN or RXEN is still off. 1884 */ 1885 ucr1 = imx_uart_readl(sport, UCR1); 1886 ucr2 = imx_uart_readl(sport, UCR2); 1887 1888 if (imx_uart_is_imx1(sport)) 1889 ucr1 |= IMX1_UCR1_UARTCLKEN; 1890 1891 ucr1 |= UCR1_UARTEN; 1892 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1893 1894 ucr2 |= UCR2_RXEN | UCR2_TXEN; 1895 ucr2 &= ~UCR2_ATEN; 1896 1897 imx_uart_writel(sport, ucr1, UCR1); 1898 imx_uart_writel(sport, ucr2, UCR2); 1899 1900 /* now enable irqs */ 1901 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1902 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1903 1904 uart_port_unlock_irqrestore(&sport->port, flags); 1905 1906 return 0; 1907} 1908 1909static int imx_uart_poll_get_char(struct uart_port *port) 1910{ 1911 struct imx_port *sport = (struct imx_port *)port; 1912 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1913 return NO_POLL_CHAR; 1914 1915 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1916} 1917 1918static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1919{ 1920 struct imx_port *sport = (struct imx_port *)port; 1921 unsigned int status; 1922 1923 /* drain */ 1924 do { 1925 status = imx_uart_readl(sport, USR1); 1926 } while (~status & USR1_TRDY); 1927 1928 /* write */ 1929 imx_uart_writel(sport, c, URTX0); 1930 1931 /* flush */ 1932 do { 1933 status = imx_uart_readl(sport, USR2); 1934 } while (~status & USR2_TXDC); 1935} 1936#endif 1937 1938/* called with port.lock taken and irqs off or from .probe without locking */ 1939static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios, 1940 struct serial_rs485 *rs485conf) 1941{ 1942 struct imx_port *sport = (struct imx_port *)port; 1943 u32 ucr2; 1944 1945 if (rs485conf->flags & SER_RS485_ENABLED) { 1946 /* Enable receiver if low-active RTS signal is requested */ 1947 if (sport->have_rtscts && !sport->have_rtsgpio && 1948 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1949 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1950 1951 /* disable transmitter */ 1952 ucr2 = imx_uart_readl(sport, UCR2); 1953 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1954 imx_uart_rts_active(sport, &ucr2); 1955 else 1956 imx_uart_rts_inactive(sport, &ucr2); 1957 imx_uart_writel(sport, ucr2, UCR2); 1958 } 1959 1960 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1961 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1962 rs485conf->flags & SER_RS485_RX_DURING_TX) 1963 imx_uart_start_rx(port); 1964 1965 return 0; 1966} 1967 1968static const struct uart_ops imx_uart_pops = { 1969 .tx_empty = imx_uart_tx_empty, 1970 .set_mctrl = imx_uart_set_mctrl, 1971 .get_mctrl = imx_uart_get_mctrl, 1972 .stop_tx = imx_uart_stop_tx, 1973 .start_tx = imx_uart_start_tx, 1974 .stop_rx = imx_uart_stop_rx, 1975 .enable_ms = imx_uart_enable_ms, 1976 .break_ctl = imx_uart_break_ctl, 1977 .startup = imx_uart_startup, 1978 .shutdown = imx_uart_shutdown, 1979 .flush_buffer = imx_uart_flush_buffer, 1980 .set_termios = imx_uart_set_termios, 1981 .type = imx_uart_type, 1982 .config_port = imx_uart_config_port, 1983 .verify_port = imx_uart_verify_port, 1984#if defined(CONFIG_CONSOLE_POLL) 1985 .poll_init = imx_uart_poll_init, 1986 .poll_get_char = imx_uart_poll_get_char, 1987 .poll_put_char = imx_uart_poll_put_char, 1988#endif 1989}; 1990 1991static struct imx_port *imx_uart_ports[UART_NR]; 1992 1993#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE) 1994static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch) 1995{ 1996 struct imx_port *sport = (struct imx_port *)port; 1997 1998 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1999 barrier(); 2000 2001 imx_uart_writel(sport, ch, URTX0); 2002} 2003 2004/* 2005 * Interrupts are disabled on entering 2006 */ 2007static void 2008imx_uart_console_write(struct console *co, const char *s, unsigned int count) 2009{ 2010 struct imx_port *sport = imx_uart_ports[co->index]; 2011 struct imx_port_ucrs old_ucr; 2012 unsigned long flags; 2013 unsigned int ucr1; 2014 int locked = 1; 2015 2016 if (sport->port.sysrq) 2017 locked = 0; 2018 else if (oops_in_progress) 2019 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2020 else 2021 uart_port_lock_irqsave(&sport->port, &flags); 2022 2023 /* 2024 * First, save UCR1/2/3 and then disable interrupts 2025 */ 2026 imx_uart_ucrs_save(sport, &old_ucr); 2027 ucr1 = old_ucr.ucr1; 2028 2029 if (imx_uart_is_imx1(sport)) 2030 ucr1 |= IMX1_UCR1_UARTCLKEN; 2031 ucr1 |= UCR1_UARTEN; 2032 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 2033 2034 imx_uart_writel(sport, ucr1, UCR1); 2035 2036 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 2037 2038 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 2039 2040 /* 2041 * Finally, wait for transmitter to become empty 2042 * and restore UCR1/2/3 2043 */ 2044 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 2045 2046 imx_uart_ucrs_restore(sport, &old_ucr); 2047 2048 if (locked) 2049 uart_port_unlock_irqrestore(&sport->port, flags); 2050} 2051 2052/* 2053 * If the port was already initialised (eg, by a boot loader), 2054 * try to determine the current setup. 2055 */ 2056static void 2057imx_uart_console_get_options(struct imx_port *sport, int *baud, 2058 int *parity, int *bits) 2059{ 2060 2061 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 2062 /* ok, the port was enabled */ 2063 unsigned int ucr2, ubir, ubmr, uartclk; 2064 unsigned int baud_raw; 2065 unsigned int ucfr_rfdiv; 2066 2067 ucr2 = imx_uart_readl(sport, UCR2); 2068 2069 *parity = 'n'; 2070 if (ucr2 & UCR2_PREN) { 2071 if (ucr2 & UCR2_PROE) 2072 *parity = 'o'; 2073 else 2074 *parity = 'e'; 2075 } 2076 2077 if (ucr2 & UCR2_WS) 2078 *bits = 8; 2079 else 2080 *bits = 7; 2081 2082 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 2083 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 2084 2085 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 2086 if (ucfr_rfdiv == 6) 2087 ucfr_rfdiv = 7; 2088 else 2089 ucfr_rfdiv = 6 - ucfr_rfdiv; 2090 2091 uartclk = clk_get_rate(sport->clk_per); 2092 uartclk /= ucfr_rfdiv; 2093 2094 { /* 2095 * The next code provides exact computation of 2096 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2097 * without need of float support or long long division, 2098 * which would be required to prevent 32bit arithmetic overflow 2099 */ 2100 unsigned int mul = ubir + 1; 2101 unsigned int div = 16 * (ubmr + 1); 2102 unsigned int rem = uartclk % div; 2103 2104 baud_raw = (uartclk / div) * mul; 2105 baud_raw += (rem * mul + div / 2) / div; 2106 *baud = (baud_raw + 50) / 100 * 100; 2107 } 2108 2109 if (*baud != baud_raw) 2110 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2111 baud_raw, *baud); 2112 } 2113} 2114 2115static int 2116imx_uart_console_setup(struct console *co, char *options) 2117{ 2118 struct imx_port *sport; 2119 int baud = 9600; 2120 int bits = 8; 2121 int parity = 'n'; 2122 int flow = 'n'; 2123 int retval; 2124 2125 /* 2126 * Check whether an invalid uart number has been specified, and 2127 * if so, search for the first available port that does have 2128 * console support. 2129 */ 2130 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2131 co->index = 0; 2132 sport = imx_uart_ports[co->index]; 2133 if (sport == NULL) 2134 return -ENODEV; 2135 2136 /* For setting the registers, we only need to enable the ipg clock. */ 2137 retval = clk_prepare_enable(sport->clk_ipg); 2138 if (retval) 2139 goto error_console; 2140 2141 if (options) 2142 uart_parse_options(options, &baud, &parity, &bits, &flow); 2143 else 2144 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2145 2146 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2147 2148 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2149 2150 if (retval) { 2151 clk_disable_unprepare(sport->clk_ipg); 2152 goto error_console; 2153 } 2154 2155 retval = clk_prepare_enable(sport->clk_per); 2156 if (retval) 2157 clk_disable_unprepare(sport->clk_ipg); 2158 2159error_console: 2160 return retval; 2161} 2162 2163static int 2164imx_uart_console_exit(struct console *co) 2165{ 2166 struct imx_port *sport = imx_uart_ports[co->index]; 2167 2168 clk_disable_unprepare(sport->clk_per); 2169 clk_disable_unprepare(sport->clk_ipg); 2170 2171 return 0; 2172} 2173 2174static struct uart_driver imx_uart_uart_driver; 2175static struct console imx_uart_console = { 2176 .name = DEV_NAME, 2177 .write = imx_uart_console_write, 2178 .device = uart_console_device, 2179 .setup = imx_uart_console_setup, 2180 .exit = imx_uart_console_exit, 2181 .flags = CON_PRINTBUFFER, 2182 .index = -1, 2183 .data = &imx_uart_uart_driver, 2184}; 2185 2186#define IMX_CONSOLE &imx_uart_console 2187 2188#else 2189#define IMX_CONSOLE NULL 2190#endif 2191 2192static struct uart_driver imx_uart_uart_driver = { 2193 .owner = THIS_MODULE, 2194 .driver_name = DRIVER_NAME, 2195 .dev_name = DEV_NAME, 2196 .major = SERIAL_IMX_MAJOR, 2197 .minor = MINOR_START, 2198 .nr = ARRAY_SIZE(imx_uart_ports), 2199 .cons = IMX_CONSOLE, 2200}; 2201 2202static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t) 2203{ 2204 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2205 unsigned long flags; 2206 2207 uart_port_lock_irqsave(&sport->port, &flags); 2208 if (sport->tx_state == WAIT_AFTER_RTS) 2209 imx_uart_start_tx(&sport->port); 2210 uart_port_unlock_irqrestore(&sport->port, flags); 2211 2212 return HRTIMER_NORESTART; 2213} 2214 2215static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t) 2216{ 2217 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2218 unsigned long flags; 2219 2220 uart_port_lock_irqsave(&sport->port, &flags); 2221 if (sport->tx_state == WAIT_AFTER_SEND) 2222 imx_uart_stop_tx(&sport->port); 2223 uart_port_unlock_irqrestore(&sport->port, flags); 2224 2225 return HRTIMER_NORESTART; 2226} 2227 2228static const struct serial_rs485 imx_rs485_supported = { 2229 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 2230 SER_RS485_RX_DURING_TX, 2231 .delay_rts_before_send = 1, 2232 .delay_rts_after_send = 1, 2233}; 2234 2235/* Default RX DMA buffer configuration */ 2236#define RX_DMA_PERIODS 16 2237#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4) 2238 2239static int imx_uart_probe(struct platform_device *pdev) 2240{ 2241 struct device_node *np = pdev->dev.of_node; 2242 struct imx_port *sport; 2243 void __iomem *base; 2244 u32 dma_buf_conf[2]; 2245 int ret = 0; 2246 u32 ucr1, ucr2, uts; 2247 struct resource *res; 2248 int txirq, rxirq, rtsirq; 2249 2250 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2251 if (!sport) 2252 return -ENOMEM; 2253 2254 sport->devdata = of_device_get_match_data(&pdev->dev); 2255 2256 ret = of_alias_get_id(np, "serial"); 2257 if (ret < 0) { 2258 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2259 return ret; 2260 } 2261 sport->port.line = ret; 2262 2263 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || 2264 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ 2265 2266 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); 2267 2268 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); 2269 2270 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); 2271 2272 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); 2273 2274 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { 2275 sport->rx_period_length = dma_buf_conf[0]; 2276 sport->rx_periods = dma_buf_conf[1]; 2277 } else { 2278 sport->rx_period_length = RX_DMA_PERIOD_LEN; 2279 sport->rx_periods = RX_DMA_PERIODS; 2280 } 2281 2282 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2283 dev_err(&pdev->dev, "serial%d out of range\n", 2284 sport->port.line); 2285 return -EINVAL; 2286 } 2287 2288 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2289 if (IS_ERR(base)) 2290 return PTR_ERR(base); 2291 2292 rxirq = platform_get_irq(pdev, 0); 2293 if (rxirq < 0) 2294 return rxirq; 2295 txirq = platform_get_irq_optional(pdev, 1); 2296 rtsirq = platform_get_irq_optional(pdev, 2); 2297 2298 sport->port.dev = &pdev->dev; 2299 sport->port.mapbase = res->start; 2300 sport->port.membase = base; 2301 sport->port.type = PORT_IMX; 2302 sport->port.iotype = UPIO_MEM; 2303 sport->port.irq = rxirq; 2304 sport->port.fifosize = 32; 2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); 2306 sport->port.ops = &imx_uart_pops; 2307 sport->port.rs485_config = imx_uart_rs485_config; 2308 /* RTS is required to control the RS485 transmitter */ 2309 if (sport->have_rtscts || sport->have_rtsgpio) 2310 sport->port.rs485_supported = imx_rs485_supported; 2311 sport->port.flags = UPF_BOOT_AUTOCONF; 2312 timer_setup(&sport->timer, imx_uart_timeout, 0); 2313 2314 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2315 if (IS_ERR(sport->gpios)) 2316 return PTR_ERR(sport->gpios); 2317 2318 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2319 if (IS_ERR(sport->clk_ipg)) { 2320 ret = PTR_ERR(sport->clk_ipg); 2321 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2322 return ret; 2323 } 2324 2325 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2326 if (IS_ERR(sport->clk_per)) { 2327 ret = PTR_ERR(sport->clk_per); 2328 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2329 return ret; 2330 } 2331 2332 sport->port.uartclk = clk_get_rate(sport->clk_per); 2333 2334 /* For register access, we only need to enable the ipg clock. */ 2335 ret = clk_prepare_enable(sport->clk_ipg); 2336 if (ret) { 2337 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); 2338 return ret; 2339 } 2340 2341 ret = uart_get_rs485_mode(&sport->port); 2342 if (ret) 2343 goto err_clk; 2344 2345 /* 2346 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2347 * signal cannot be set low during transmission in case the 2348 * receiver is off (limitation of the i.MX UART IP). 2349 */ 2350 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2351 sport->have_rtscts && !sport->have_rtsgpio && 2352 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2353 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2354 dev_err(&pdev->dev, 2355 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2356 2357 /* Disable interrupts before requesting them */ 2358 ucr1 = imx_uart_readl(sport, UCR1); 2359 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); 2360 imx_uart_writel(sport, ucr1, UCR1); 2361 2362 /* Disable Ageing Timer interrupt */ 2363 ucr2 = imx_uart_readl(sport, UCR2); 2364 ucr2 &= ~UCR2_ATEN; 2365 imx_uart_writel(sport, ucr2, UCR2); 2366 2367 /* 2368 * In case RS485 is enabled without GPIO RTS control, the UART IP 2369 * is used to control CTS signal. Keep both the UART and Receiver 2370 * enabled, otherwise the UART IP pulls CTS signal always HIGH no 2371 * matter how the UCR2 CTSC and CTS bits are set. To prevent any 2372 * data from being fed into the RX FIFO, enable loopback mode in 2373 * UTS register, which disconnects the RX path from external RXD 2374 * pin and connects it to the Transceiver, which is disabled, so 2375 * no data can be fed to the RX FIFO that way. 2376 */ 2377 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2378 sport->have_rtscts && !sport->have_rtsgpio) { 2379 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)); 2380 uts |= UTS_LOOP; 2381 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 2382 2383 ucr1 = imx_uart_readl(sport, UCR1); 2384 ucr1 |= UCR1_UARTEN; 2385 imx_uart_writel(sport, ucr1, UCR1); 2386 2387 ucr2 = imx_uart_readl(sport, UCR2); 2388 ucr2 |= UCR2_RXEN; 2389 imx_uart_writel(sport, ucr2, UCR2); 2390 } 2391 2392 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2393 /* 2394 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2395 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2396 * and DCD (when they are outputs) or enables the respective 2397 * irqs. So set this bit early, i.e. before requesting irqs. 2398 */ 2399 u32 ufcr = imx_uart_readl(sport, UFCR); 2400 if (!(ufcr & UFCR_DCEDTE)) 2401 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2402 2403 /* 2404 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2405 * enabled later because they cannot be cleared 2406 * (confirmed on i.MX25) which makes them unusable. 2407 */ 2408 imx_uart_writel(sport, 2409 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2410 UCR3); 2411 2412 } else { 2413 u32 ucr3 = UCR3_DSR; 2414 u32 ufcr = imx_uart_readl(sport, UFCR); 2415 if (ufcr & UFCR_DCEDTE) 2416 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2417 2418 if (!imx_uart_is_imx1(sport)) 2419 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2420 imx_uart_writel(sport, ucr3, UCR3); 2421 } 2422 2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2425 sport->trigger_start_tx.function = imx_trigger_start_tx; 2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx; 2427 2428 /* 2429 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2430 * chips only have one interrupt. 2431 */ 2432 if (txirq > 0) { 2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2434 dev_name(&pdev->dev), sport); 2435 if (ret) { 2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2437 ret); 2438 goto err_clk; 2439 } 2440 2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2442 dev_name(&pdev->dev), sport); 2443 if (ret) { 2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2445 ret); 2446 goto err_clk; 2447 } 2448 2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 2450 dev_name(&pdev->dev), sport); 2451 if (ret) { 2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n", 2453 ret); 2454 goto err_clk; 2455 } 2456 } else { 2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2458 dev_name(&pdev->dev), sport); 2459 if (ret) { 2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2461 goto err_clk; 2462 } 2463 } 2464 2465 imx_uart_ports[sport->port.line] = sport; 2466 2467 platform_set_drvdata(pdev, sport); 2468 2469 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2470 2471err_clk: 2472 clk_disable_unprepare(sport->clk_ipg); 2473 2474 return ret; 2475} 2476 2477static void imx_uart_remove(struct platform_device *pdev) 2478{ 2479 struct imx_port *sport = platform_get_drvdata(pdev); 2480 2481 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2482} 2483 2484static void imx_uart_restore_context(struct imx_port *sport) 2485{ 2486 unsigned long flags; 2487 2488 uart_port_lock_irqsave(&sport->port, &flags); 2489 if (!sport->context_saved) { 2490 uart_port_unlock_irqrestore(&sport->port, flags); 2491 return; 2492 } 2493 2494 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2495 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2496 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2497 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2498 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2499 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2500 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2501 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2502 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2503 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2504 sport->context_saved = false; 2505 uart_port_unlock_irqrestore(&sport->port, flags); 2506} 2507 2508static void imx_uart_save_context(struct imx_port *sport) 2509{ 2510 unsigned long flags; 2511 2512 /* Save necessary regs */ 2513 uart_port_lock_irqsave(&sport->port, &flags); 2514 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2515 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2516 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2517 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2518 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2519 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2520 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2521 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2522 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2523 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2524 sport->context_saved = true; 2525 uart_port_unlock_irqrestore(&sport->port, flags); 2526} 2527 2528static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2529{ 2530 u32 ucr3; 2531 2532 ucr3 = imx_uart_readl(sport, UCR3); 2533 if (on) { 2534 imx_uart_writel(sport, USR1_AWAKE, USR1); 2535 ucr3 |= UCR3_AWAKEN; 2536 } else { 2537 ucr3 &= ~UCR3_AWAKEN; 2538 } 2539 imx_uart_writel(sport, ucr3, UCR3); 2540 2541 if (sport->have_rtscts) { 2542 u32 ucr1 = imx_uart_readl(sport, UCR1); 2543 if (on) { 2544 imx_uart_writel(sport, USR1_RTSD, USR1); 2545 ucr1 |= UCR1_RTSDEN; 2546 } else { 2547 ucr1 &= ~UCR1_RTSDEN; 2548 } 2549 imx_uart_writel(sport, ucr1, UCR1); 2550 } 2551} 2552 2553static int imx_uart_suspend_noirq(struct device *dev) 2554{ 2555 struct imx_port *sport = dev_get_drvdata(dev); 2556 2557 imx_uart_save_context(sport); 2558 2559 clk_disable(sport->clk_ipg); 2560 2561 pinctrl_pm_select_sleep_state(dev); 2562 2563 return 0; 2564} 2565 2566static int imx_uart_resume_noirq(struct device *dev) 2567{ 2568 struct imx_port *sport = dev_get_drvdata(dev); 2569 int ret; 2570 2571 pinctrl_pm_select_default_state(dev); 2572 2573 ret = clk_enable(sport->clk_ipg); 2574 if (ret) 2575 return ret; 2576 2577 imx_uart_restore_context(sport); 2578 2579 return 0; 2580} 2581 2582static int imx_uart_suspend(struct device *dev) 2583{ 2584 struct imx_port *sport = dev_get_drvdata(dev); 2585 int ret; 2586 2587 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2588 disable_irq(sport->port.irq); 2589 2590 ret = clk_prepare_enable(sport->clk_ipg); 2591 if (ret) 2592 return ret; 2593 2594 /* enable wakeup from i.MX UART */ 2595 imx_uart_enable_wakeup(sport, true); 2596 2597 return 0; 2598} 2599 2600static int imx_uart_resume(struct device *dev) 2601{ 2602 struct imx_port *sport = dev_get_drvdata(dev); 2603 2604 /* disable wakeup from i.MX UART */ 2605 imx_uart_enable_wakeup(sport, false); 2606 2607 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2608 enable_irq(sport->port.irq); 2609 2610 clk_disable_unprepare(sport->clk_ipg); 2611 2612 return 0; 2613} 2614 2615static int imx_uart_freeze(struct device *dev) 2616{ 2617 struct imx_port *sport = dev_get_drvdata(dev); 2618 2619 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2620 2621 return clk_prepare_enable(sport->clk_ipg); 2622} 2623 2624static int imx_uart_thaw(struct device *dev) 2625{ 2626 struct imx_port *sport = dev_get_drvdata(dev); 2627 2628 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2629 2630 clk_disable_unprepare(sport->clk_ipg); 2631 2632 return 0; 2633} 2634 2635static const struct dev_pm_ops imx_uart_pm_ops = { 2636 .suspend_noirq = imx_uart_suspend_noirq, 2637 .resume_noirq = imx_uart_resume_noirq, 2638 .freeze_noirq = imx_uart_suspend_noirq, 2639 .thaw_noirq = imx_uart_resume_noirq, 2640 .restore_noirq = imx_uart_resume_noirq, 2641 .suspend = imx_uart_suspend, 2642 .resume = imx_uart_resume, 2643 .freeze = imx_uart_freeze, 2644 .thaw = imx_uart_thaw, 2645 .restore = imx_uart_thaw, 2646}; 2647 2648static struct platform_driver imx_uart_platform_driver = { 2649 .probe = imx_uart_probe, 2650 .remove_new = imx_uart_remove, 2651 2652 .driver = { 2653 .name = "imx-uart", 2654 .of_match_table = imx_uart_dt_ids, 2655 .pm = &imx_uart_pm_ops, 2656 }, 2657}; 2658 2659static int __init imx_uart_init(void) 2660{ 2661 int ret = uart_register_driver(&imx_uart_uart_driver); 2662 2663 if (ret) 2664 return ret; 2665 2666 ret = platform_driver_register(&imx_uart_platform_driver); 2667 if (ret != 0) 2668 uart_unregister_driver(&imx_uart_uart_driver); 2669 2670 return ret; 2671} 2672 2673static void __exit imx_uart_exit(void) 2674{ 2675 platform_driver_unregister(&imx_uart_platform_driver); 2676 uart_unregister_driver(&imx_uart_uart_driver); 2677} 2678 2679module_init(imx_uart_init); 2680module_exit(imx_uart_exit); 2681 2682MODULE_AUTHOR("Sascha Hauer"); 2683MODULE_DESCRIPTION("IMX generic serial port driver"); 2684MODULE_LICENSE("GPL"); 2685MODULE_ALIAS("platform:imx-uart"); 2686