1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/delay.h> 10#include <linux/debugfs.h> 11#include <linux/init.h> 12#include <linux/interrupt.h> 13#include <linux/iopoll.h> 14#include <linux/kernel.h> 15#include <linux/nvmem-consumer.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/reset.h> 19#include <linux/thermal.h> 20#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22#include "../thermal_hwmon.h" 23 24#define LVTS_MONCTL0(__base) (__base + 0x0000) 25#define LVTS_MONCTL1(__base) (__base + 0x0004) 26#define LVTS_MONCTL2(__base) (__base + 0x0008) 27#define LVTS_MONINT(__base) (__base + 0x000C) 28#define LVTS_MONINTSTS(__base) (__base + 0x0010) 29#define LVTS_MONIDET0(__base) (__base + 0x0014) 30#define LVTS_MONIDET1(__base) (__base + 0x0018) 31#define LVTS_MONIDET2(__base) (__base + 0x001C) 32#define LVTS_MONIDET3(__base) (__base + 0x0020) 33#define LVTS_H2NTHRE(__base) (__base + 0x0024) 34#define LVTS_HTHRE(__base) (__base + 0x0028) 35#define LVTS_OFFSETH(__base) (__base + 0x0030) 36#define LVTS_OFFSETL(__base) (__base + 0x0034) 37#define LVTS_MSRCTL0(__base) (__base + 0x0038) 38#define LVTS_MSRCTL1(__base) (__base + 0x003C) 39#define LVTS_TSSEL(__base) (__base + 0x0040) 40#define LVTS_CALSCALE(__base) (__base + 0x0048) 41#define LVTS_ID(__base) (__base + 0x004C) 42#define LVTS_CONFIG(__base) (__base + 0x0050) 43#define LVTS_EDATA00(__base) (__base + 0x0054) 44#define LVTS_EDATA01(__base) (__base + 0x0058) 45#define LVTS_EDATA02(__base) (__base + 0x005C) 46#define LVTS_EDATA03(__base) (__base + 0x0060) 47#define LVTS_MSR0(__base) (__base + 0x0090) 48#define LVTS_MSR1(__base) (__base + 0x0094) 49#define LVTS_MSR2(__base) (__base + 0x0098) 50#define LVTS_MSR3(__base) (__base + 0x009C) 51#define LVTS_IMMD0(__base) (__base + 0x00A0) 52#define LVTS_IMMD1(__base) (__base + 0x00A4) 53#define LVTS_IMMD2(__base) (__base + 0x00A8) 54#define LVTS_IMMD3(__base) (__base + 0x00AC) 55#define LVTS_PROTCTL(__base) (__base + 0x00C0) 56#define LVTS_PROTTA(__base) (__base + 0x00C4) 57#define LVTS_PROTTB(__base) (__base + 0x00C8) 58#define LVTS_PROTTC(__base) (__base + 0x00CC) 59#define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61#define LVTS_PERIOD_UNIT 0 62#define LVTS_GROUP_INTERVAL 0 63#define LVTS_FILTER_INTERVAL 0 64#define LVTS_SENSOR_INTERVAL 0 65#define LVTS_HW_FILTER 0x0 66#define LVTS_TSSEL_CONF 0x13121110 67#define LVTS_CALSCALE_CONF 0x300 68#define LVTS_MONINT_CONF 0x8300318C 69 70#define LVTS_MONINT_OFFSET_SENSOR0 0xC 71#define LVTS_MONINT_OFFSET_SENSOR1 0x180 72#define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75#define LVTS_INT_SENSOR0 0x0009001F 76#define LVTS_INT_SENSOR1 0x001203E0 77#define LVTS_INT_SENSOR2 0x00247C00 78#define LVTS_INT_SENSOR3 0x1FC00000 79 80#define LVTS_SENSOR_MAX 4 81#define LVTS_GOLDEN_TEMP_MAX 62 82#define LVTS_GOLDEN_TEMP_DEFAULT 50 83#define LVTS_COEFF_A_MT8195 -250460 84#define LVTS_COEFF_B_MT8195 250460 85#define LVTS_COEFF_A_MT7988 -204650 86#define LVTS_COEFF_B_MT7988 204650 87 88#define LVTS_MSR_IMMEDIATE_MODE 0 89#define LVTS_MSR_FILTERED_MODE 1 90 91#define LVTS_MSR_READ_TIMEOUT_US 400 92#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94#define LVTS_HW_SHUTDOWN_MT7988 105000 95#define LVTS_HW_SHUTDOWN_MT8192 105000 96#define LVTS_HW_SHUTDOWN_MT8195 105000 97 98#define LVTS_MINIMUM_THRESHOLD 20000 99 100static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 101static int golden_temp_offset; 102 103struct lvts_sensor_data { 104 int dt_id; 105}; 106 107struct lvts_ctrl_data { 108 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 109 int cal_offset[LVTS_SENSOR_MAX]; 110 int hw_tshut_temp; 111 int num_lvts_sensor; 112 int offset; 113 int mode; 114}; 115 116struct lvts_data { 117 const struct lvts_ctrl_data *lvts_ctrl; 118 int num_lvts_ctrl; 119 int temp_factor; 120 int temp_offset; 121}; 122 123struct lvts_sensor { 124 struct thermal_zone_device *tz; 125 void __iomem *msr; 126 void __iomem *base; 127 int id; 128 int dt_id; 129 int low_thresh; 130 int high_thresh; 131}; 132 133struct lvts_ctrl { 134 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 135 const struct lvts_data *lvts_data; 136 u32 calibration[LVTS_SENSOR_MAX]; 137 u32 hw_tshut_raw_temp; 138 int num_lvts_sensor; 139 int mode; 140 void __iomem *base; 141 int low_thresh; 142 int high_thresh; 143}; 144 145struct lvts_domain { 146 struct lvts_ctrl *lvts_ctrl; 147 struct reset_control *reset; 148 struct clk *clk; 149 int num_lvts_ctrl; 150 void __iomem *base; 151 size_t calib_len; 152 u8 *calib; 153#ifdef CONFIG_DEBUG_FS 154 struct dentry *dom_dentry; 155#endif 156}; 157 158#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 159 160#define LVTS_DEBUG_FS_REGS(__reg) \ 161{ \ 162 .name = __stringify(__reg), \ 163 .offset = __reg(0), \ 164} 165 166static const struct debugfs_reg32 lvts_regs[] = { 167 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 168 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 169 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 170 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 171 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 172 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 173 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 174 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 175 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 176 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 177 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 178 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 179 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 180 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 181 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 182 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 183 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 184 LVTS_DEBUG_FS_REGS(LVTS_ID), 185 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 186 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 187 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 188 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 189 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 190 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 191 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 192 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 193 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 194 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 195 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 196 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 197 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 198 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 199 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 200 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 201 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 202 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 203}; 204 205static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 206{ 207 struct debugfs_regset32 *regset; 208 struct lvts_ctrl *lvts_ctrl; 209 struct dentry *dentry; 210 char name[64]; 211 int i; 212 213 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 214 if (IS_ERR(lvts_td->dom_dentry)) 215 return 0; 216 217 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 218 219 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 220 221 sprintf(name, "controller%d", i); 222 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 223 if (IS_ERR(dentry)) 224 continue; 225 226 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 227 if (!regset) 228 continue; 229 230 regset->base = lvts_ctrl->base; 231 regset->regs = lvts_regs; 232 regset->nregs = ARRAY_SIZE(lvts_regs); 233 234 debugfs_create_regset32("registers", 0400, dentry, regset); 235 } 236 237 return 0; 238} 239 240static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 241{ 242 debugfs_remove_recursive(lvts_td->dom_dentry); 243} 244 245#else 246 247static inline int lvts_debugfs_init(struct device *dev, 248 struct lvts_domain *lvts_td) 249{ 250 return 0; 251} 252 253static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 254 255#endif 256 257static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 258{ 259 int temperature; 260 261 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 262 temperature += golden_temp_offset; 263 264 return temperature; 265} 266 267static u32 lvts_temp_to_raw(int temperature, int temp_factor) 268{ 269 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 270 271 raw_temp = div_s64(raw_temp, -temp_factor); 272 273 return raw_temp; 274} 275 276static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 277{ 278 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 279 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 280 sensors[lvts_sensor->id]); 281 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 282 void __iomem *msr = lvts_sensor->msr; 283 u32 value; 284 int rc; 285 286 /* 287 * Measurement registers: 288 * 289 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 290 * 291 * Bits: 292 * 293 * 32-17: Unused 294 * 16 : Valid temperature 295 * 15-0 : Raw temperature 296 */ 297 rc = readl_poll_timeout(msr, value, value & BIT(16), 298 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 299 300 /* 301 * As the thermal zone temperature will read before the 302 * hardware sensor is fully initialized, we have to check the 303 * validity of the temperature returned when reading the 304 * measurement register. The thermal controller will set the 305 * valid bit temperature only when it is totally initialized. 306 * 307 * Otherwise, we may end up with garbage values out of the 308 * functionning temperature and directly jump to a system 309 * shutdown. 310 */ 311 if (rc) 312 return -EAGAIN; 313 314 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 315 316 return 0; 317} 318 319static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 320{ 321 u32 masks[] = { 322 LVTS_MONINT_OFFSET_SENSOR0, 323 LVTS_MONINT_OFFSET_SENSOR1, 324 LVTS_MONINT_OFFSET_SENSOR2, 325 LVTS_MONINT_OFFSET_SENSOR3, 326 }; 327 u32 value = 0; 328 int i; 329 330 value = readl(LVTS_MONINT(lvts_ctrl->base)); 331 332 for (i = 0; i < ARRAY_SIZE(masks); i++) { 333 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 334 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 335 value |= masks[i]; 336 else 337 value &= ~masks[i]; 338 } 339 340 writel(value, LVTS_MONINT(lvts_ctrl->base)); 341} 342 343static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 344{ 345 int i; 346 347 if (high > lvts_ctrl->high_thresh) 348 return true; 349 350 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 351 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 352 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 353 return false; 354 355 return true; 356} 357 358static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 359{ 360 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 361 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 362 sensors[lvts_sensor->id]); 363 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 364 void __iomem *base = lvts_sensor->base; 365 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 366 lvts_data->temp_factor); 367 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 368 bool should_update_thresh; 369 370 lvts_sensor->low_thresh = low; 371 lvts_sensor->high_thresh = high; 372 373 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 374 if (should_update_thresh) { 375 lvts_ctrl->high_thresh = high; 376 lvts_ctrl->low_thresh = low; 377 } 378 lvts_update_irq_mask(lvts_ctrl); 379 380 if (!should_update_thresh) 381 return 0; 382 383 /* 384 * Low offset temperature threshold 385 * 386 * LVTS_OFFSETL 387 * 388 * Bits: 389 * 390 * 14-0 : Raw temperature for threshold 391 */ 392 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 393 thermal_zone_device_type(tz), low); 394 writel(raw_low, LVTS_OFFSETL(base)); 395 396 /* 397 * High offset temperature threshold 398 * 399 * LVTS_OFFSETH 400 * 401 * Bits: 402 * 403 * 14-0 : Raw temperature for threshold 404 */ 405 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 406 thermal_zone_device_type(tz), high); 407 writel(raw_high, LVTS_OFFSETH(base)); 408 409 return 0; 410} 411 412static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 413{ 414 irqreturn_t iret = IRQ_NONE; 415 u32 value; 416 u32 masks[] = { 417 LVTS_INT_SENSOR0, 418 LVTS_INT_SENSOR1, 419 LVTS_INT_SENSOR2, 420 LVTS_INT_SENSOR3 421 }; 422 int i; 423 424 /* 425 * Interrupt monitoring status 426 * 427 * LVTS_MONINTST 428 * 429 * Bits: 430 * 431 * 31 : Interrupt for stage 3 432 * 30 : Interrupt for stage 2 433 * 29 : Interrupt for state 1 434 * 28 : Interrupt using filter on sensor 3 435 * 436 * 27 : Interrupt using immediate on sensor 3 437 * 26 : Interrupt normal to hot on sensor 3 438 * 25 : Interrupt high offset on sensor 3 439 * 24 : Interrupt low offset on sensor 3 440 * 441 * 23 : Interrupt hot threshold on sensor 3 442 * 22 : Interrupt cold threshold on sensor 3 443 * 21 : Interrupt using filter on sensor 2 444 * 20 : Interrupt using filter on sensor 1 445 * 446 * 19 : Interrupt using filter on sensor 0 447 * 18 : Interrupt using immediate on sensor 2 448 * 17 : Interrupt using immediate on sensor 1 449 * 16 : Interrupt using immediate on sensor 0 450 * 451 * 15 : Interrupt device access timeout interrupt 452 * 14 : Interrupt normal to hot on sensor 2 453 * 13 : Interrupt high offset interrupt on sensor 2 454 * 12 : Interrupt low offset interrupt on sensor 2 455 * 456 * 11 : Interrupt hot threshold on sensor 2 457 * 10 : Interrupt cold threshold on sensor 2 458 * 9 : Interrupt normal to hot on sensor 1 459 * 8 : Interrupt high offset interrupt on sensor 1 460 * 461 * 7 : Interrupt low offset interrupt on sensor 1 462 * 6 : Interrupt hot threshold on sensor 1 463 * 5 : Interrupt cold threshold on sensor 1 464 * 4 : Interrupt normal to hot on sensor 0 465 * 466 * 3 : Interrupt high offset interrupt on sensor 0 467 * 2 : Interrupt low offset interrupt on sensor 0 468 * 1 : Interrupt hot threshold on sensor 0 469 * 0 : Interrupt cold threshold on sensor 0 470 * 471 * We are interested in the sensor(s) responsible of the 472 * interrupt event. We update the thermal framework with the 473 * thermal zone associated with the sensor. The framework will 474 * take care of the rest whatever the kind of interrupt, we 475 * are only interested in which sensor raised the interrupt. 476 * 477 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 478 * => 0x1FC00000 479 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 480 * => 0x00247C00 481 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 482 * => 0X001203E0 483 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 484 * => 0x0009001F 485 */ 486 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 487 488 /* 489 * Let's figure out which sensors raised the interrupt 490 * 491 * NOTE: the masks array must be ordered with the index 492 * corresponding to the sensor id eg. index=0, mask for 493 * sensor0. 494 */ 495 for (i = 0; i < ARRAY_SIZE(masks); i++) { 496 497 if (!(value & masks[i])) 498 continue; 499 500 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 501 THERMAL_TRIP_VIOLATED); 502 iret = IRQ_HANDLED; 503 } 504 505 /* 506 * Write back to clear the interrupt status (W1C) 507 */ 508 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 509 510 return iret; 511} 512 513/* 514 * Temperature interrupt handler. Even if the driver supports more 515 * interrupt modes, we use the interrupt when the temperature crosses 516 * the hot threshold the way up and the way down (modulo the 517 * hysteresis). 518 * 519 * Each thermal domain has a couple of interrupts, one for hardware 520 * reset and another one for all the thermal events happening on the 521 * different sensors. 522 * 523 * The interrupt is configured for thermal events when crossing the 524 * hot temperature limit. At each interrupt, we check in every 525 * controller if there is an interrupt pending. 526 */ 527static irqreturn_t lvts_irq_handler(int irq, void *data) 528{ 529 struct lvts_domain *lvts_td = data; 530 irqreturn_t aux, iret = IRQ_NONE; 531 int i; 532 533 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 534 535 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 536 if (aux != IRQ_HANDLED) 537 continue; 538 539 iret = IRQ_HANDLED; 540 } 541 542 return iret; 543} 544 545static struct thermal_zone_device_ops lvts_ops = { 546 .get_temp = lvts_get_temp, 547 .set_trips = lvts_set_trips, 548}; 549 550static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 551 const struct lvts_ctrl_data *lvts_ctrl_data) 552{ 553 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 554 void __iomem *msr_regs[] = { 555 LVTS_MSR0(lvts_ctrl->base), 556 LVTS_MSR1(lvts_ctrl->base), 557 LVTS_MSR2(lvts_ctrl->base), 558 LVTS_MSR3(lvts_ctrl->base) 559 }; 560 561 void __iomem *imm_regs[] = { 562 LVTS_IMMD0(lvts_ctrl->base), 563 LVTS_IMMD1(lvts_ctrl->base), 564 LVTS_IMMD2(lvts_ctrl->base), 565 LVTS_IMMD3(lvts_ctrl->base) 566 }; 567 568 int i; 569 570 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 571 572 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 573 574 /* 575 * At this point, we don't know which id matches which 576 * sensor. Let's set arbitrally the id from the index. 577 */ 578 lvts_sensor[i].id = i; 579 580 /* 581 * The thermal zone registration will set the trip 582 * point interrupt in the thermal controller 583 * register. But this one will be reset in the 584 * initialization after. So we need to post pone the 585 * thermal zone creation after the controller is 586 * setup. For this reason, we store the device tree 587 * node id from the data in the sensor structure 588 */ 589 lvts_sensor[i].dt_id = dt_id; 590 591 /* 592 * We assign the base address of the thermal 593 * controller as a back pointer. So it will be 594 * accessible from the different thermal framework ops 595 * as we pass the lvts_sensor pointer as thermal zone 596 * private data. 597 */ 598 lvts_sensor[i].base = lvts_ctrl->base; 599 600 /* 601 * Each sensor has its own register address to read from. 602 */ 603 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 604 imm_regs[i] : msr_regs[i]; 605 606 lvts_sensor[i].low_thresh = INT_MIN; 607 lvts_sensor[i].high_thresh = INT_MIN; 608 }; 609 610 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 611 612 return 0; 613} 614 615/* 616 * The efuse blob values follows the sensor enumeration per thermal 617 * controller. The decoding of the stream is as follow: 618 * 619 * MT8192 : 620 * Stream index map for MCU Domain mt8192 : 621 * 622 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 623 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 624 * 625 * <-----sensor#2-----> <-----sensor#3-----> 626 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 627 * 628 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 629 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 630 * 631 * Stream index map for AP Domain mt8192 : 632 * 633 * <-----sensor#0-----> <-----sensor#1-----> 634 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 635 * 636 * <-----sensor#2-----> <-----sensor#3-----> 637 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 638 * 639 * <-----sensor#4-----> <-----sensor#5-----> 640 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 641 * 642 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 643 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 644 * 645 * MT8195 : 646 * Stream index map for MCU Domain mt8195 : 647 * 648 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 649 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 650 * 651 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 652 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 653 * 654 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 655 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 656 * 657 * Stream index map for AP Domain mt8195 : 658 * 659 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 660 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 661 * 662 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 663 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 664 * 665 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 666 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 667 * 668 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 669 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 670 * 671 * The data description gives the offset of the calibration data in 672 * this bytes stream for each sensor. 673 */ 674static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 675 const struct lvts_ctrl_data *lvts_ctrl_data, 676 u8 *efuse_calibration) 677{ 678 int i; 679 680 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 681 memcpy(&lvts_ctrl->calibration[i], 682 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 683 684 return 0; 685} 686 687/* 688 * The efuse bytes stream can be split into different chunk of 689 * nvmems. This function reads and concatenate those into a single 690 * buffer so it can be read sequentially when initializing the 691 * calibration data. 692 */ 693static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 694 const struct lvts_data *lvts_data) 695{ 696 struct device_node *np = dev_of_node(dev); 697 struct nvmem_cell *cell; 698 struct property *prop; 699 const char *cell_name; 700 701 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 702 size_t len; 703 u8 *efuse; 704 705 cell = of_nvmem_cell_get(np, cell_name); 706 if (IS_ERR(cell)) { 707 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 708 return PTR_ERR(cell); 709 } 710 711 efuse = nvmem_cell_read(cell, &len); 712 713 nvmem_cell_put(cell); 714 715 if (IS_ERR(efuse)) { 716 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 717 return PTR_ERR(efuse); 718 } 719 720 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 721 lvts_td->calib_len + len, GFP_KERNEL); 722 if (!lvts_td->calib) { 723 kfree(efuse); 724 return -ENOMEM; 725 } 726 727 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 728 729 lvts_td->calib_len += len; 730 731 kfree(efuse); 732 } 733 734 return 0; 735} 736 737static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset) 738{ 739 u32 gt; 740 741 gt = (*value) >> 24; 742 743 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 744 golden_temp = gt; 745 746 golden_temp_offset = golden_temp * 500 + temp_offset; 747 748 return 0; 749} 750 751static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 752 const struct lvts_data *lvts_data) 753{ 754 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 755 struct lvts_ctrl *lvts_ctrl; 756 int i, ret; 757 758 /* 759 * Create the calibration bytes stream from efuse data 760 */ 761 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 762 if (ret) 763 return ret; 764 765 /* 766 * The golden temp information is contained in the first chunk 767 * of efuse data. 768 */ 769 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset); 770 if (ret) 771 return ret; 772 773 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 774 if (!lvts_ctrl) 775 return -ENOMEM; 776 777 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 778 779 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 780 lvts_ctrl[i].lvts_data = lvts_data; 781 782 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 783 &lvts_data->lvts_ctrl[i]); 784 if (ret) 785 return ret; 786 787 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 788 &lvts_data->lvts_ctrl[i], 789 lvts_td->calib); 790 if (ret) 791 return ret; 792 793 /* 794 * The mode the ctrl will use to read the temperature 795 * (filtered or immediate) 796 */ 797 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 798 799 /* 800 * The temperature to raw temperature must be done 801 * after initializing the calibration. 802 */ 803 lvts_ctrl[i].hw_tshut_raw_temp = 804 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, 805 lvts_data->temp_factor); 806 807 lvts_ctrl[i].low_thresh = INT_MIN; 808 lvts_ctrl[i].high_thresh = INT_MIN; 809 } 810 811 /* 812 * We no longer need the efuse bytes stream, let's free it 813 */ 814 devm_kfree(dev, lvts_td->calib); 815 816 lvts_td->lvts_ctrl = lvts_ctrl; 817 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 818 819 return 0; 820} 821 822/* 823 * At this point the configuration register is the only place in the 824 * driver where we write multiple values. Per hardware constraint, 825 * each write in the configuration register must be separated by a 826 * delay of 2 us. 827 */ 828static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 829{ 830 int i; 831 832 /* 833 * Configuration register 834 */ 835 for (i = 0; i < nr_cmds; i++) { 836 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 837 usleep_range(2, 4); 838 } 839} 840 841static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 842{ 843 /* 844 * LVTS_PROTCTL : Thermal Protection Sensor Selection 845 * 846 * Bits: 847 * 848 * 19-18 : Sensor to base the protection on 849 * 17-16 : Strategy: 850 * 00 : Average of 4 sensors 851 * 01 : Max of 4 sensors 852 * 10 : Selected sensor with bits 19-18 853 * 11 : Reserved 854 */ 855 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 856 857 /* 858 * LVTS_PROTTA : Stage 1 temperature threshold 859 * LVTS_PROTTB : Stage 2 temperature threshold 860 * LVTS_PROTTC : Stage 3 temperature threshold 861 * 862 * Bits: 863 * 864 * 14-0: Raw temperature threshold 865 * 866 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 867 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 868 */ 869 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 870 871 /* 872 * LVTS_MONINT : Interrupt configuration register 873 * 874 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 875 * register, except we set the bits to enable the interrupt. 876 */ 877 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 878 879 return 0; 880} 881 882static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 883{ 884 int ret; 885 886 ret = reset_control_assert(reset); 887 if (ret) 888 return ret; 889 890 return reset_control_deassert(reset); 891} 892 893/* 894 * Enable or disable the clocks of a specified thermal controller 895 */ 896static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 897{ 898 /* 899 * LVTS_CLKEN : Internal LVTS clock 900 * 901 * Bits: 902 * 903 * 0 : enable / disable clock 904 */ 905 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 906 907 return 0; 908} 909 910static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 911{ 912 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 913 914 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 915 916 /* 917 * LVTS_ID : Get ID and status of the thermal controller 918 * 919 * Bits: 920 * 921 * 0-5 : thermal controller id 922 * 7 : thermal controller connection is valid 923 */ 924 id = readl(LVTS_ID(lvts_ctrl->base)); 925 if (!(id & BIT(7))) 926 return -EIO; 927 928 return 0; 929} 930 931static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 932{ 933 /* 934 * Write device mask: 0xC1030000 935 */ 936 u32 cmds[] = { 937 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 938 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 939 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 940 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 941 }; 942 943 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 944 945 return 0; 946} 947 948static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 949{ 950 int i; 951 void __iomem *lvts_edata[] = { 952 LVTS_EDATA00(lvts_ctrl->base), 953 LVTS_EDATA01(lvts_ctrl->base), 954 LVTS_EDATA02(lvts_ctrl->base), 955 LVTS_EDATA03(lvts_ctrl->base) 956 }; 957 958 /* 959 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 960 * 961 * Bits: 962 * 963 * 20-0 : Efuse value for normalization data 964 */ 965 for (i = 0; i < LVTS_SENSOR_MAX; i++) 966 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 967 968 return 0; 969} 970 971static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 972{ 973 u32 value; 974 975 /* 976 * LVTS_TSSEL : Sensing point index numbering 977 * 978 * Bits: 979 * 980 * 31-24: ADC Sense 3 981 * 23-16: ADC Sense 2 982 * 15-8 : ADC Sense 1 983 * 7-0 : ADC Sense 0 984 */ 985 value = LVTS_TSSEL_CONF; 986 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 987 988 /* 989 * LVTS_CALSCALE : ADC voltage round 990 */ 991 value = 0x300; 992 value = LVTS_CALSCALE_CONF; 993 994 /* 995 * LVTS_MSRCTL0 : Sensor filtering strategy 996 * 997 * Filters: 998 * 999 * 000 : One sample 1000 * 001 : Avg 2 samples 1001 * 010 : 4 samples, drop min and max, avg 2 samples 1002 * 011 : 6 samples, drop min and max, avg 4 samples 1003 * 100 : 10 samples, drop min and max, avg 8 samples 1004 * 101 : 18 samples, drop min and max, avg 16 samples 1005 * 1006 * Bits: 1007 * 1008 * 0-2 : Sensor0 filter 1009 * 3-5 : Sensor1 filter 1010 * 6-8 : Sensor2 filter 1011 * 9-11 : Sensor3 filter 1012 */ 1013 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1014 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1015 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1016 1017 /* 1018 * LVTS_MONCTL1 : Period unit and group interval configuration 1019 * 1020 * The clock source of LVTS thermal controller is 26MHz. 1021 * 1022 * The period unit is a time base for all the interval delays 1023 * specified in the registers. By default we use 12. The time 1024 * conversion is done by multiplying by 256 and 1/26.10^6 1025 * 1026 * An interval delay multiplied by the period unit gives the 1027 * duration in seconds. 1028 * 1029 * - Filter interval delay is a delay between two samples of 1030 * the same sensor. 1031 * 1032 * - Sensor interval delay is a delay between two samples of 1033 * different sensors. 1034 * 1035 * - Group interval delay is a delay between different rounds. 1036 * 1037 * For example: 1038 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1039 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1040 * and then 1041 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1042 * Filter interval delay = 1 * Period unit = 118.149us 1043 * Sensor interval delay = 2 * Period unit = 236.298us 1044 * Group interval delay = 1 * Period unit = 118.149us 1045 * 1046 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1047 * <--> Filter interval delay 1048 * <--> Sensor interval delay 1049 * <--> Group interval delay 1050 * Bits: 1051 * 29 - 20 : Group interval 1052 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1053 * or an interrupt everytime the hot threshold is crossed (0) 1054 * 9 - 0 : Period unit 1055 * 1056 */ 1057 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1058 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1059 1060 /* 1061 * LVTS_MONCTL2 : Filtering and sensor interval 1062 * 1063 * Bits: 1064 * 1065 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1066 * the same sensor, filter interval 1067 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1068 * 1069 */ 1070 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1071 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1072 1073 return lvts_irq_init(lvts_ctrl); 1074} 1075 1076static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1077{ 1078 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1079 struct thermal_zone_device *tz; 1080 u32 sensor_map = 0; 1081 int i; 1082 /* 1083 * Bitmaps to enable each sensor on immediate and filtered modes, as 1084 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1085 */ 1086 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1087 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1088 1089 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1090 sensor_imm_bitmap : sensor_filt_bitmap; 1091 1092 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1093 1094 int dt_id = lvts_sensors[i].dt_id; 1095 1096 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1097 &lvts_ops); 1098 if (IS_ERR(tz)) { 1099 /* 1100 * This thermal zone is not described in the 1101 * device tree. It is not an error from the 1102 * thermal OF code POV, we just continue. 1103 */ 1104 if (PTR_ERR(tz) == -ENODEV) 1105 continue; 1106 1107 return PTR_ERR(tz); 1108 } 1109 1110 devm_thermal_add_hwmon_sysfs(dev, tz); 1111 1112 /* 1113 * The thermal zone pointer will be needed in the 1114 * interrupt handler, we store it in the sensor 1115 * structure. The thermal domain structure will be 1116 * passed to the interrupt handler private data as the 1117 * interrupt is shared for all the controller 1118 * belonging to the thermal domain. 1119 */ 1120 lvts_sensors[i].tz = tz; 1121 1122 /* 1123 * This sensor was correctly associated with a thermal 1124 * zone, let's set the corresponding bit in the sensor 1125 * map, so we can enable the temperature monitoring in 1126 * the hardware thermal controller. 1127 */ 1128 sensor_map |= sensor_bitmap[i]; 1129 } 1130 1131 /* 1132 * The initialization of the thermal zones give us 1133 * which sensor point to enable. If any thermal zone 1134 * was not described in the device tree, it won't be 1135 * enabled here in the sensor map. 1136 */ 1137 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1138 /* 1139 * LVTS_MSRCTL1 : Measurement control 1140 * 1141 * Bits: 1142 * 1143 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1144 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1145 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1146 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1147 * 1148 * That configuration will ignore the filtering and the delays 1149 * introduced in MONCTL1 and MONCTL2 1150 */ 1151 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1152 } else { 1153 /* 1154 * Bits: 1155 * 9: Single point access flow 1156 * 0-3: Enable sensing point 0-3 1157 */ 1158 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1159 } 1160 1161 return 0; 1162} 1163 1164static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1165 const struct lvts_data *lvts_data) 1166{ 1167 struct lvts_ctrl *lvts_ctrl; 1168 int i, ret; 1169 1170 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1171 if (ret) 1172 return ret; 1173 1174 ret = lvts_domain_reset(dev, lvts_td->reset); 1175 if (ret) { 1176 dev_dbg(dev, "Failed to reset domain"); 1177 return ret; 1178 } 1179 1180 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1181 1182 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1183 1184 /* 1185 * Initialization steps: 1186 * 1187 * - Enable the clock 1188 * - Connect to the LVTS 1189 * - Initialize the LVTS 1190 * - Prepare the calibration data 1191 * - Select monitored sensors 1192 * [ Configure sampling ] 1193 * [ Configure the interrupt ] 1194 * - Start measurement 1195 */ 1196 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1197 if (ret) { 1198 dev_dbg(dev, "Failed to enable LVTS clock"); 1199 return ret; 1200 } 1201 1202 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1203 if (ret) { 1204 dev_dbg(dev, "Failed to connect to LVTS controller"); 1205 return ret; 1206 } 1207 1208 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1209 if (ret) { 1210 dev_dbg(dev, "Failed to initialize controller"); 1211 return ret; 1212 } 1213 1214 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1215 if (ret) { 1216 dev_dbg(dev, "Failed to calibrate controller"); 1217 return ret; 1218 } 1219 1220 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1221 if (ret) { 1222 dev_dbg(dev, "Failed to configure controller"); 1223 return ret; 1224 } 1225 1226 ret = lvts_ctrl_start(dev, lvts_ctrl); 1227 if (ret) { 1228 dev_dbg(dev, "Failed to start controller"); 1229 return ret; 1230 } 1231 } 1232 1233 return lvts_debugfs_init(dev, lvts_td); 1234} 1235 1236static int lvts_probe(struct platform_device *pdev) 1237{ 1238 const struct lvts_data *lvts_data; 1239 struct lvts_domain *lvts_td; 1240 struct device *dev = &pdev->dev; 1241 struct resource *res; 1242 int irq, ret; 1243 1244 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1245 if (!lvts_td) 1246 return -ENOMEM; 1247 1248 lvts_data = of_device_get_match_data(dev); 1249 1250 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1251 if (IS_ERR(lvts_td->clk)) 1252 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1253 1254 res = platform_get_mem_or_io(pdev, 0); 1255 if (!res) 1256 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1257 1258 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1259 if (IS_ERR(lvts_td->base)) 1260 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1261 1262 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1263 if (IS_ERR(lvts_td->reset)) 1264 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1265 1266 irq = platform_get_irq(pdev, 0); 1267 if (irq < 0) 1268 return irq; 1269 1270 golden_temp_offset = lvts_data->temp_offset; 1271 1272 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1273 if (ret) 1274 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1275 1276 /* 1277 * At this point the LVTS is initialized and enabled. We can 1278 * safely enable the interrupt. 1279 */ 1280 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1281 IRQF_ONESHOT, dev_name(dev), lvts_td); 1282 if (ret) 1283 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1284 1285 platform_set_drvdata(pdev, lvts_td); 1286 1287 return 0; 1288} 1289 1290static void lvts_remove(struct platform_device *pdev) 1291{ 1292 struct lvts_domain *lvts_td; 1293 int i; 1294 1295 lvts_td = platform_get_drvdata(pdev); 1296 1297 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1298 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1299 1300 lvts_debugfs_exit(lvts_td); 1301} 1302 1303static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1304 { 1305 .cal_offset = { 0x00, 0x04, 0x08, 0x0c }, 1306 .lvts_sensor = { 1307 { .dt_id = MT7988_CPU_0 }, 1308 { .dt_id = MT7988_CPU_1 }, 1309 { .dt_id = MT7988_ETH2P5G_0 }, 1310 { .dt_id = MT7988_ETH2P5G_1 } 1311 }, 1312 .num_lvts_sensor = 4, 1313 .offset = 0x0, 1314 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, 1315 }, 1316 { 1317 .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, 1318 .lvts_sensor = { 1319 { .dt_id = MT7988_TOPS_0}, 1320 { .dt_id = MT7988_TOPS_1}, 1321 { .dt_id = MT7988_ETHWARP_0}, 1322 { .dt_id = MT7988_ETHWARP_1} 1323 }, 1324 .num_lvts_sensor = 4, 1325 .offset = 0x100, 1326 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, 1327 } 1328}; 1329 1330static int lvts_suspend(struct device *dev) 1331{ 1332 struct lvts_domain *lvts_td; 1333 int i; 1334 1335 lvts_td = dev_get_drvdata(dev); 1336 1337 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1338 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1339 1340 clk_disable_unprepare(lvts_td->clk); 1341 1342 return 0; 1343} 1344 1345static int lvts_resume(struct device *dev) 1346{ 1347 struct lvts_domain *lvts_td; 1348 int i, ret; 1349 1350 lvts_td = dev_get_drvdata(dev); 1351 1352 ret = clk_prepare_enable(lvts_td->clk); 1353 if (ret) 1354 return ret; 1355 1356 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1357 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1358 1359 return 0; 1360} 1361 1362static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1363 { 1364 .cal_offset = { 0x04, 0x08 }, 1365 .lvts_sensor = { 1366 { .dt_id = MT8192_MCU_BIG_CPU0 }, 1367 { .dt_id = MT8192_MCU_BIG_CPU1 } 1368 }, 1369 .num_lvts_sensor = 2, 1370 .offset = 0x0, 1371 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1372 .mode = LVTS_MSR_FILTERED_MODE, 1373 }, 1374 { 1375 .cal_offset = { 0x0c, 0x10 }, 1376 .lvts_sensor = { 1377 { .dt_id = MT8192_MCU_BIG_CPU2 }, 1378 { .dt_id = MT8192_MCU_BIG_CPU3 } 1379 }, 1380 .num_lvts_sensor = 2, 1381 .offset = 0x100, 1382 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1383 .mode = LVTS_MSR_FILTERED_MODE, 1384 }, 1385 { 1386 .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, 1387 .lvts_sensor = { 1388 { .dt_id = MT8192_MCU_LITTLE_CPU0 }, 1389 { .dt_id = MT8192_MCU_LITTLE_CPU1 }, 1390 { .dt_id = MT8192_MCU_LITTLE_CPU2 }, 1391 { .dt_id = MT8192_MCU_LITTLE_CPU3 } 1392 }, 1393 .num_lvts_sensor = 4, 1394 .offset = 0x200, 1395 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1396 .mode = LVTS_MSR_FILTERED_MODE, 1397 } 1398}; 1399 1400static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1401 { 1402 .cal_offset = { 0x24, 0x28 }, 1403 .lvts_sensor = { 1404 { .dt_id = MT8192_AP_VPU0 }, 1405 { .dt_id = MT8192_AP_VPU1 } 1406 }, 1407 .num_lvts_sensor = 2, 1408 .offset = 0x0, 1409 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1410 }, 1411 { 1412 .cal_offset = { 0x2c, 0x30 }, 1413 .lvts_sensor = { 1414 { .dt_id = MT8192_AP_GPU0 }, 1415 { .dt_id = MT8192_AP_GPU1 } 1416 }, 1417 .num_lvts_sensor = 2, 1418 .offset = 0x100, 1419 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1420 }, 1421 { 1422 .cal_offset = { 0x34, 0x38 }, 1423 .lvts_sensor = { 1424 { .dt_id = MT8192_AP_INFRA }, 1425 { .dt_id = MT8192_AP_CAM }, 1426 }, 1427 .num_lvts_sensor = 2, 1428 .offset = 0x200, 1429 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1430 }, 1431 { 1432 .cal_offset = { 0x3c, 0x40, 0x44 }, 1433 .lvts_sensor = { 1434 { .dt_id = MT8192_AP_MD0 }, 1435 { .dt_id = MT8192_AP_MD1 }, 1436 { .dt_id = MT8192_AP_MD2 } 1437 }, 1438 .num_lvts_sensor = 3, 1439 .offset = 0x300, 1440 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, 1441 } 1442}; 1443 1444static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1445 { 1446 .cal_offset = { 0x04, 0x07 }, 1447 .lvts_sensor = { 1448 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1449 { .dt_id = MT8195_MCU_BIG_CPU1 } 1450 }, 1451 .num_lvts_sensor = 2, 1452 .offset = 0x0, 1453 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1454 }, 1455 { 1456 .cal_offset = { 0x0d, 0x10 }, 1457 .lvts_sensor = { 1458 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1459 { .dt_id = MT8195_MCU_BIG_CPU3 } 1460 }, 1461 .num_lvts_sensor = 2, 1462 .offset = 0x100, 1463 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1464 }, 1465 { 1466 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1467 .lvts_sensor = { 1468 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1469 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1470 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1471 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1472 }, 1473 .num_lvts_sensor = 4, 1474 .offset = 0x200, 1475 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1476 } 1477}; 1478 1479static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1480 { 1481 .cal_offset = { 0x25, 0x28 }, 1482 .lvts_sensor = { 1483 { .dt_id = MT8195_AP_VPU0 }, 1484 { .dt_id = MT8195_AP_VPU1 } 1485 }, 1486 .num_lvts_sensor = 2, 1487 .offset = 0x0, 1488 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1489 }, 1490 { 1491 .cal_offset = { 0x2e, 0x31 }, 1492 .lvts_sensor = { 1493 { .dt_id = MT8195_AP_GPU0 }, 1494 { .dt_id = MT8195_AP_GPU1 } 1495 }, 1496 .num_lvts_sensor = 2, 1497 .offset = 0x100, 1498 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1499 }, 1500 { 1501 .cal_offset = { 0x37, 0x3a, 0x3d }, 1502 .lvts_sensor = { 1503 { .dt_id = MT8195_AP_VDEC }, 1504 { .dt_id = MT8195_AP_IMG }, 1505 { .dt_id = MT8195_AP_INFRA }, 1506 }, 1507 .num_lvts_sensor = 3, 1508 .offset = 0x200, 1509 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1510 }, 1511 { 1512 .cal_offset = { 0x43, 0x46 }, 1513 .lvts_sensor = { 1514 { .dt_id = MT8195_AP_CAM0 }, 1515 { .dt_id = MT8195_AP_CAM1 } 1516 }, 1517 .num_lvts_sensor = 2, 1518 .offset = 0x300, 1519 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1520 } 1521}; 1522 1523static const struct lvts_data mt7988_lvts_ap_data = { 1524 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1525 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1526 .temp_factor = LVTS_COEFF_A_MT7988, 1527 .temp_offset = LVTS_COEFF_B_MT7988, 1528}; 1529 1530static const struct lvts_data mt8192_lvts_mcu_data = { 1531 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1532 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1533}; 1534 1535static const struct lvts_data mt8192_lvts_ap_data = { 1536 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1537 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1538}; 1539 1540static const struct lvts_data mt8195_lvts_mcu_data = { 1541 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1542 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1543 .temp_factor = LVTS_COEFF_A_MT8195, 1544 .temp_offset = LVTS_COEFF_B_MT8195, 1545}; 1546 1547static const struct lvts_data mt8195_lvts_ap_data = { 1548 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1549 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1550 .temp_factor = LVTS_COEFF_A_MT8195, 1551 .temp_offset = LVTS_COEFF_B_MT8195, 1552}; 1553 1554static const struct of_device_id lvts_of_match[] = { 1555 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1556 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1557 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1558 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1559 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1560 {}, 1561}; 1562MODULE_DEVICE_TABLE(of, lvts_of_match); 1563 1564static const struct dev_pm_ops lvts_pm_ops = { 1565 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1566}; 1567 1568static struct platform_driver lvts_driver = { 1569 .probe = lvts_probe, 1570 .remove_new = lvts_remove, 1571 .driver = { 1572 .name = "mtk-lvts-thermal", 1573 .of_match_table = lvts_of_match, 1574 .pm = &lvts_pm_ops, 1575 }, 1576}; 1577module_platform_driver(lvts_driver); 1578 1579MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1580MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1581MODULE_LICENSE("GPL"); 1582