1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DDK750_SII164_H__
3#define DDK750_SII164_H__
4
5#define USE_DVICHIP
6
7/* Hot Plug detection mode structure */
8enum sii164_hot_plug_mode {
9	SII164_HOTPLUG_DISABLE = 0,	/* Disable Hot Plug output bit
10					 * (always high).
11					 */
12
13	SII164_HOTPLUG_USE_MDI,         /* Use Monitor Detect Interrupt bit. */
14	SII164_HOTPLUG_USE_RSEN,        /* Use Receiver Sense detect bit. */
15	SII164_HOTPLUG_USE_HTPLG        /* Use Hot Plug detect bit. */
16};
17
18/* Silicon Image SiI164 chip prototype */
19long sii164_init_chip(unsigned char edgeSelect,
20		      unsigned char busSelect,
21		      unsigned char dualEdgeClkSelect,
22		      unsigned char hsyncEnable,
23		      unsigned char vsyncEnable,
24		      unsigned char deskewEnable,
25		      unsigned char deskewSetting,
26		      unsigned char continuousSyncEnable,
27		      unsigned char pllFilterEnable,
28		      unsigned char pllFilterValue);
29
30unsigned short sii164_get_vendor_id(void);
31unsigned short sii164GetDeviceID(void);
32
33#ifdef SII164_FULL_FUNCTIONS
34void sii164ResetChip(void);
35char *sii164GetChipString(void);
36void sii164SetPower(unsigned char powerUp);
37void sii164EnableHotPlugDetection(unsigned char enableHotPlug);
38unsigned char sii164IsConnected(void);
39unsigned char sii164CheckInterrupt(void);
40void sii164ClearInterrupt(void);
41#endif
42/*
43 * below register definition is used for
44 * Silicon Image SiI164 DVI controller chip
45 */
46/*
47 * Vendor ID registers
48 */
49#define SII164_VENDOR_ID_LOW                        0x00
50#define SII164_VENDOR_ID_HIGH                       0x01
51
52/*
53 * Device ID registers
54 */
55#define SII164_DEVICE_ID_LOW                        0x02
56#define SII164_DEVICE_ID_HIGH                       0x03
57
58/*
59 * Device Revision
60 */
61#define SII164_DEVICE_REVISION                      0x04
62
63/*
64 * Frequency Limitation registers
65 */
66#define SII164_FREQUENCY_LIMIT_LOW                  0x06
67#define SII164_FREQUENCY_LIMIT_HIGH                 0x07
68
69/*
70 * Power Down and Input Signal Configuration registers
71 */
72#define SII164_CONFIGURATION                        0x08
73
74/* Power down (PD) */
75#define SII164_CONFIGURATION_POWER_DOWN             0x00
76#define SII164_CONFIGURATION_POWER_NORMAL           0x01
77#define SII164_CONFIGURATION_POWER_MASK             0x01
78
79/* Input Edge Latch Select (EDGE) */
80#define SII164_CONFIGURATION_LATCH_FALLING          0x00
81#define SII164_CONFIGURATION_LATCH_RISING           0x02
82
83/* Bus Select (BSEL) */
84#define SII164_CONFIGURATION_BUS_12BITS             0x00
85#define SII164_CONFIGURATION_BUS_24BITS             0x04
86
87/* Dual Edge Clock Select (DSEL) */
88#define SII164_CONFIGURATION_CLOCK_SINGLE           0x00
89#define SII164_CONFIGURATION_CLOCK_DUAL             0x08
90
91/* Horizontal Sync Enable (HEN) */
92#define SII164_CONFIGURATION_HSYNC_FORCE_LOW        0x00
93#define SII164_CONFIGURATION_HSYNC_AS_IS            0x10
94
95/* Vertical Sync Enable (VEN) */
96#define SII164_CONFIGURATION_VSYNC_FORCE_LOW        0x00
97#define SII164_CONFIGURATION_VSYNC_AS_IS            0x20
98
99/*
100 * Detection registers
101 */
102#define SII164_DETECT                               0x09
103
104/* Monitor Detect Interrupt (MDI) */
105#define SII164_DETECT_MONITOR_STATE_CHANGE          0x00
106#define SII164_DETECT_MONITOR_STATE_NO_CHANGE       0x01
107#define SII164_DETECT_MONITOR_STATE_CLEAR           0x01
108#define SII164_DETECT_MONITOR_STATE_MASK            0x01
109
110/* Hot Plug detect Input (HTPLG) */
111#define SII164_DETECT_HOT_PLUG_STATUS_OFF           0x00
112#define SII164_DETECT_HOT_PLUG_STATUS_ON            0x02
113#define SII164_DETECT_HOT_PLUG_STATUS_MASK          0x02
114
115/* Receiver Sense (RSEN) */
116#define SII164_DETECT_RECEIVER_SENSE_NOT_DETECTED   0x00
117#define SII164_DETECT_RECEIVER_SENSE_DETECTED       0x04
118
119/* Interrupt Generation Method (TSEL) */
120#define SII164_DETECT_INTERRUPT_BY_RSEN_PIN         0x00
121#define SII164_DETECT_INTERRUPT_BY_HTPLG_PIN        0x08
122#define SII164_DETECT_INTERRUPT_MASK                0x08
123
124/* Monitor Sense Output (MSEN) */
125#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH     0x00
126#define SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI      0x10
127#define SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN     0x20
128#define SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG    0x30
129#define SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG     0x30
130
131/*
132 * Skewing registers
133 */
134#define SII164_DESKEW                               0x0A
135
136/* General Purpose Input (CTL[3:1]) */
137#define SII164_DESKEW_GENERAL_PURPOSE_INPUT_MASK    0x0E
138
139/* De-skewing Enable bit (DKEN) */
140#define SII164_DESKEW_DISABLE                       0x00
141#define SII164_DESKEW_ENABLE                        0x10
142
143/* De-skewing Setting (DK[3:1])*/
144#define SII164_DESKEW_1_STEP                        0x00
145#define SII164_DESKEW_2_STEP                        0x20
146#define SII164_DESKEW_3_STEP                        0x40
147#define SII164_DESKEW_4_STEP                        0x60
148#define SII164_DESKEW_5_STEP                        0x80
149#define SII164_DESKEW_6_STEP                        0xA0
150#define SII164_DESKEW_7_STEP                        0xC0
151#define SII164_DESKEW_8_STEP                        0xE0
152
153/*
154 * User Configuration Data registers (CFG 7:0)
155 */
156#define SII164_USER_CONFIGURATION                   0x0B
157
158/*
159 * PLL registers
160 */
161#define SII164_PLL                                  0x0C
162
163/* PLL Filter Value (PLLF) */
164#define SII164_PLL_FILTER_VALUE_MASK                0x0E
165
166/* PLL Filter Enable (PFEN) */
167#define SII164_PLL_FILTER_DISABLE                   0x00
168#define SII164_PLL_FILTER_ENABLE                    0x01
169
170/* Sync Continuous (SCNT) */
171#define SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE   0x00
172#define SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE    0x80
173
174#endif
175