1/* SPDX-License-Identifier: GPL-2.0 */
2/******************************************************************************
3 *
4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
5 *
6 * Modifications for inclusion into the Linux staging tree are
7 * Copyright(c) 2010 Larry Finger. All rights reserved.
8 *
9 * Contact information:
10 * WLAN FAE <wlanfae@realtek.com>
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 ******************************************************************************/
14#ifndef __RTL8712_SYSCFG_BITDEF_H__
15#define __RTL8712_SYSCFG_BITDEF_H__
16
17/*SYS_PWR_CTRL*/
18/*SRCTRL0*/
19/*SRCTRL1*/
20/*SYS_CLKR*/
21
22/*SYS_IOS_CTRL*/
23#define iso_LDR2RP_SHT		8 /* EE Loader to Retention Path*/
24#define iso_LDR2RP		BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
25
26/*SYS_CTRL*/
27#define FEN_DIO_SDIO_SHT	0
28#define FEN_DIO_SDIO		BIT(FEN_DIO_SDIO_SHT)
29#define FEN_SDIO_SHT		1
30#define FEN_SDIO		BIT(FEN_SDIO_SHT)
31#define FEN_USBA_SHT		2
32#define FEN_USBA		BIT(FEN_USBA_SHT)
33#define FEN_UPLL_SHT		3
34#define FEN_UPLL		BIT(FEN_UPLL_SHT)
35#define FEN_USBD_SHT		4
36#define FEN_USBD		BIT(FEN_USBD_SHT)
37#define FEN_DIO_PCIE_SHT	5
38#define FEN_DIO_PCIE		BIT(FEN_DIO_PCIE_SHT)
39#define FEN_PCIEA_SHT		6
40#define FEN_PCIEA		BIT(FEN_PCIEA_SHT)
41#define FEN_PPLL_SHT		7
42#define FEN_PPLL		BIT(FEN_PPLL_SHT)
43#define FEN_PCIED_SHT		8
44#define FEN_PCIED		BIT(FEN_PCIED_SHT)
45#define FEN_CPUEN_SHT		10
46#define FEN_CPUEN		BIT(FEN_CPUEN_SHT)
47#define FEN_DCORE_SHT		11
48#define FEN_DCORE		BIT(FEN_DCORE_SHT)
49#define FEN_ELDR_SHT		12
50#define FEN_ELDR		BIT(FEN_ELDR_SHT)
51#define PWC_DV2LDR_SHT		13
52#define PWC_DV2LDR		BIT(PWC_DV2LDR_SHT) /* Loader Power Enable*/
53
54/*=== SYS_CLKR ===*/
55#define SYS_CLKSEL_SHT		0
56#define SYS_CLKSEL		BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/
57#define PS_CLKSEL_SHT		1
58#define PS_CLKSEL		BIT(PS_CLKSEL_SHT) /*System power save
59						    * clock select.
60						    */
61#define CPU_CLKSEL_SHT		2
62#define CPU_CLKSEL		BIT(CPU_CLKSEL_SHT) /* System Clock select,
63						     * 1: AFE source,
64						     * 0: System clock(L-Bus)
65						     */
66#define INT32K_EN_SHT		3
67#define INT32K_EN		BIT(INT32K_EN_SHT)
68#define MACSLP_SHT		4
69#define MACSLP			BIT(MACSLP_SHT)
70#define MAC_CLK_EN_SHT		11
71#define MAC_CLK_EN		BIT(MAC_CLK_EN_SHT) /* MAC Clock Enable.*/
72#define SYS_CLK_EN_SHT		12
73#define SYS_CLK_EN		BIT(SYS_CLK_EN_SHT)
74#define RING_CLK_EN_SHT		13
75#define RING_CLK_EN		BIT(RING_CLK_EN_SHT)
76#define SWHW_SEL_SHT		14
77#define SWHW_SEL		BIT(SWHW_SEL_SHT) /* Load done,
78						   * control path switch.
79						   */
80#define FWHW_SEL_SHT		15
81#define FWHW_SEL		BIT(FWHW_SEL_SHT) /* Sleep exit,
82						   * control path switch.
83						   */
84
85/*9346CR*/
86#define	_VPDIDX_MSK		0xFF00
87#define	_VPDIDX_SHT		8
88#define	_EEM_MSK		0x00C0
89#define	_EEM_SHT		6
90#define	_EEM0			BIT(6)
91#define	_EEM1			BIT(7)
92#define	_EEPROM_EN		BIT(5)
93#define	_9356SEL		BIT(4)
94#define	_EECS			BIT(3)
95#define	_EESK			BIT(2)
96#define	_EEDI			BIT(1)
97#define	_EEDO			BIT(0)
98
99/*AFE_MISC*/
100#define	AFE_MISC_USB_MBEN_SHT	7
101#define	AFE_MISC_USB_MBEN	BIT(AFE_MISC_USB_MBEN_SHT)
102#define	AFE_MISC_USB_BGEN_SHT	6
103#define	AFE_MISC_USB_BGEN	BIT(AFE_MISC_USB_BGEN_SHT)
104#define	AFE_MISC_LD12_VDAJ_SHT	4
105#define	AFE_MISC_LD12_VDAJ_MSK	0X0030
106#define	AFE_MISC_LD12_VDAJ	BIT(AFE_MISC_LD12_VDAJ_SHT)
107#define	AFE_MISC_I32_EN_SHT	3
108#define	AFE_MISC_I32_EN		BIT(AFE_MISC_I32_EN_SHT)
109#define	AFE_MISC_E32_EN_SHT	2
110#define	AFE_MISC_E32_EN		BIT(AFE_MISC_E32_EN_SHT)
111#define	AFE_MISC_MBEN_SHT	1
112#define	AFE_MISC_MBEN		BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro
113						       * Block's Mbias.
114						       */
115#define	AFE_MISC_BGEN_SHT	0
116#define	AFE_MISC_BGEN		BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro
117						       * Block's Bandgap.
118						       */
119
120/*--------------------------------------------------------------------------*/
121/*       SPS1_CTRL bits				(Offset 0x18-1E, 56bits)*/
122/*--------------------------------------------------------------------------*/
123#define	SPS1_SWEN		BIT(1)	/* Enable vsps18 SW Macro Block.*/
124#define	SPS1_LDEN		BIT(0)	/* Enable VSPS12 LDO Macro block.*/
125
126/*----------------------------------------------------------------------------*/
127/*       LDOA15_CTRL bits		(Offset 0x20, 8bits)*/
128/*----------------------------------------------------------------------------*/
129#define	LDA15_EN		BIT(0)	/* Enable LDOA15 Macro Block*/
130
131/*----------------------------------------------------------------------------*/
132/*       8192S LDOV12D_CTRL bit		(Offset 0x21, 8bits)*/
133/*----------------------------------------------------------------------------*/
134#define	LDV12_EN		BIT(0)	/* Enable LDOVD12 Macro Block*/
135#define	LDV12_SDBY		BIT(1)	/* LDOVD12 standby mode*/
136
137/*CLK_PS_CTRL*/
138#define	_CLK_GATE_EN		BIT(0)
139
140/* EFUSE_CTRL*/
141#define EF_FLAG			BIT(31)		/* Access Flag, Write:1;
142						 *	        Read:0
143						 */
144#define EF_PGPD			0x70000000	/* E-fuse Program time*/
145#define EF_RDT			0x0F000000	/* E-fuse read time: in the
146						 * unit of cycle time
147						 */
148#define EF_PDN_EN		BIT(19)		/* EFuse Power down enable*/
149#define ALD_EN			BIT(18)		/* Autoload Enable*/
150#define EF_ADDR			0x0003FF00	/* Access Address*/
151#define EF_DATA			0x000000FF	/* Access Data*/
152
153/* EFUSE_TEST*/
154#define LDOE25_EN		BIT(31)		/* Enable LDOE25 Macro Block*/
155
156/* EFUSE_CLK_CTRL*/
157#define EFUSE_CLK_EN		BIT(1)		/* E-Fuse Clock Enable*/
158#define EFUSE_CLK_SEL		BIT(0)		/* E-Fuse Clock Select,
159						 * 0:500K, 1:40M
160						 */
161
162#endif	/*__RTL8712_SYSCFG_BITDEF_H__*/
163
164