1/* SPDX-License-Identifier: GPL-2.0 */
2/******************************************************************************
3 *
4 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
5 *
6 * Modifications for inclusion into the Linux staging tree are
7 * Copyright(c) 2010 Larry Finger. All rights reserved.
8 *
9 * Contact information:
10 * WLAN FAE <wlanfae@realtek.com>
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 ******************************************************************************/
14#ifndef __RTL8712_GP_BITDEF_H__
15#define __RTL8712_GP_BITDEF_H__
16
17/*GPIO_CTRL*/
18#define	_GPIO_MOD_MSK			0xFF000000
19#define	_GPIO_MOD_SHT			24
20#define	_GPIO_IO_SEL_MSK		0x00FF0000
21#define	_GPIO_IO_SEL_SHT		16
22#define	_GPIO_OUT_MSK			0x0000FF00
23#define	_GPIO_OUT_SHT			8
24#define	_GPIO_IN_MSK			0x000000FF
25#define	_GPIO_IN_SHT			0
26
27/*SYS_PINMUX_CFG*/
28#define	_GPIOSEL_MSK			0x0003
29#define	_GPIOSEL_SHT			0
30
31/*LED_CFG*/
32#define _LED1SV				BIT(7)
33#define _LED1CM_MSK			0x0070
34#define _LED1CM_SHT			4
35#define _LED0SV				BIT(3)
36#define _LED0CM_MSK			0x0007
37#define _LED0CM_SHT			0
38
39/*PHY_REG*/
40#define _HST_RDRDY_SHT			0
41#define _HST_RDRDY_MSK			0xFF
42#define _HST_RDRDY			BIT(_HST_RDRDY_SHT)
43#define _CPU_WTBUSY_SHT			1
44#define _CPU_WTBUSY_MSK			0xFF
45#define _CPU_WTBUSY			BIT(_CPU_WTBUSY_SHT)
46
47/* 11. General Purpose Registers   (Offset: 0x02E0 - 0x02FF)*/
48
49/*       8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/
50
51/*----------------------------------------------------------------------------*/
52
53#define		GPIOMUX_EN	BIT(3)	/* When this bit is set to "1",
54					 * GPIO PINs will switch to MAC
55					 * GPIO Function
56					 */
57#define		GPIOSEL_GPIO	0	/* UART or JTAG or pure GPIO*/
58#define		GPIOSEL_PHYDBG	1	/* PHYDBG*/
59#define		GPIOSEL_BT	2	/* BT_coex*/
60#define		GPIOSEL_WLANDBG	3	/* WLANDBG*/
61#define		GPIOSEL_GPIO_MASK	(~(BIT(0) | BIT(1)))
62/* HW Radio OFF switch (GPIO BIT) */
63#define		HAL_8192S_HW_GPIO_OFF_BIT	BIT(3)
64#define		HAL_8192S_HW_GPIO_OFF_MASK	0xF7
65#define		HAL_8192S_HW_GPIO_WPS_BIT	BIT(4)
66
67#endif	/*__RTL8712_GP_BITDEF_H__*/
68
69