1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * register description for HopeRf rf69 radio module 4 * 5 * Copyright (C) 2016 Wolf-Entwicklungen 6 * Marcus Wolf <linux@wolf-entwicklungen.de> 7 */ 8 9/*******************************************/ 10/* RF69 register addresses */ 11/*******************************************/ 12#define REG_FIFO 0x00 13#define REG_OPMODE 0x01 14#define REG_DATAMODUL 0x02 15#define REG_BITRATE_MSB 0x03 16#define REG_BITRATE_LSB 0x04 17#define REG_FDEV_MSB 0x05 18#define REG_FDEV_LSB 0x06 19#define REG_FRF_MSB 0x07 20#define REG_FRF_MID 0x08 21#define REG_FRF_LSB 0x09 22#define REG_OSC1 0x0A 23#define REG_AFCCTRL 0x0B 24#define REG_LOWBAT 0x0C 25#define REG_LISTEN1 0x0D 26#define REG_LISTEN2 0x0E 27#define REG_LISTEN3 0x0F 28#define REG_VERSION 0x10 29#define REG_PALEVEL 0x11 30#define REG_PARAMP 0x12 31#define REG_OCP 0x13 32#define REG_AGCREF 0x14 /* not available on RF69 */ 33#define REG_AGCTHRESH1 0x15 /* not available on RF69 */ 34#define REG_AGCTHRESH2 0x16 /* not available on RF69 */ 35#define REG_AGCTHRESH3 0x17 /* not available on RF69 */ 36#define REG_LNA 0x18 37#define REG_RXBW 0x19 38#define REG_AFCBW 0x1A 39#define REG_OOKPEAK 0x1B 40#define REG_OOKAVG 0x1C 41#define REG_OOKFIX 0x1D 42#define REG_AFCFEI 0x1E 43#define REG_AFCMSB 0x1F 44#define REG_AFCLSB 0x20 45#define REG_FEIMSB 0x21 46#define REG_FEILSB 0x22 47#define REG_RSSICONFIG 0x23 48#define REG_RSSIVALUE 0x24 49#define REG_DIOMAPPING1 0x25 50#define REG_DIOMAPPING2 0x26 51#define REG_IRQFLAGS1 0x27 52#define REG_IRQFLAGS2 0x28 53#define REG_RSSITHRESH 0x29 54#define REG_RXTIMEOUT1 0x2A 55#define REG_RXTIMEOUT2 0x2B 56#define REG_PREAMBLE_MSB 0x2C 57#define REG_PREAMBLE_LSB 0x2D 58#define REG_SYNC_CONFIG 0x2E 59#define REG_SYNCVALUE1 0x2F 60#define REG_SYNCVALUE2 0x30 61#define REG_SYNCVALUE3 0x31 62#define REG_SYNCVALUE4 0x32 63#define REG_SYNCVALUE5 0x33 64#define REG_SYNCVALUE6 0x34 65#define REG_SYNCVALUE7 0x35 66#define REG_SYNCVALUE8 0x36 67#define REG_PACKETCONFIG1 0x37 68#define REG_PAYLOAD_LENGTH 0x38 69#define REG_NODEADRS 0x39 70#define REG_BROADCASTADRS 0x3A 71#define REG_AUTOMODES 0x3B 72#define REG_FIFO_THRESH 0x3C 73#define REG_PACKETCONFIG2 0x3D 74#define REG_AESKEY1 0x3E 75#define REG_AESKEY2 0x3F 76#define REG_AESKEY3 0x40 77#define REG_AESKEY4 0x41 78#define REG_AESKEY5 0x42 79#define REG_AESKEY6 0x43 80#define REG_AESKEY7 0x44 81#define REG_AESKEY8 0x45 82#define REG_AESKEY9 0x46 83#define REG_AESKEY10 0x47 84#define REG_AESKEY11 0x48 85#define REG_AESKEY12 0x49 86#define REG_AESKEY13 0x4A 87#define REG_AESKEY14 0x4B 88#define REG_AESKEY15 0x4C 89#define REG_AESKEY16 0x4D 90#define REG_TEMP1 0x4E 91#define REG_TEMP2 0x4F 92#define REG_TESTLNA 0x58 93#define REG_TESTPA1 0x5A /* only present on RFM69HW */ 94#define REG_TESTPA2 0x5C /* only present on RFM69HW */ 95#define REG_TESTDAGC 0x6F 96#define REG_TESTAFC 0x71 97 98/******************************************************/ 99/* RF69/SX1231 bit definition */ 100/******************************************************/ 101/* write bit */ 102#define WRITE_BIT 0x80 103 104/* RegOpMode */ 105#define MASK_OPMODE_SEQUENCER_OFF 0x80 106#define MASK_OPMODE_LISTEN_ON 0x40 107#define MASK_OPMODE_LISTEN_ABORT 0x20 108#define MASK_OPMODE_MODE 0x1C 109 110#define OPMODE_MODE_SLEEP 0x00 111#define OPMODE_MODE_STANDBY 0x04 /* default */ 112#define OPMODE_MODE_SYNTHESIZER 0x08 113#define OPMODE_MODE_TRANSMIT 0x0C 114#define OPMODE_MODE_RECEIVE 0x10 115 116/* RegDataModul */ 117#define MASK_DATAMODUL_MODE 0x06 118#define MASK_DATAMODUL_MODULATION_TYPE 0x18 119#define MASK_DATAMODUL_MODULATION_SHAPE 0x03 120 121#define DATAMODUL_MODE_PACKET 0x00 /* default */ 122#define DATAMODUL_MODE_CONTINUOUS 0x40 123#define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 124 125#define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ 126#define DATAMODUL_MODULATION_TYPE_OOK 0x08 127 128#define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ 129#define DATAMODUL_MODULATION_SHAPE_1_0 0x01 130#define DATAMODUL_MODULATION_SHAPE_0_5 0x02 131#define DATAMODUL_MODULATION_SHAPE_0_3 0x03 132#define DATAMODUL_MODULATION_SHAPE_BR 0x01 133#define DATAMODUL_MODULATION_SHAPE_2BR 0x02 134 135/* RegFDevMsb (0x05)*/ 136#define FDEVMASB_MASK 0x3f 137 138/* 139 * // RegOsc1 140 * #define OSC1_RCCAL_START 0x80 141 * #define OSC1_RCCAL_DONE 0x40 142 * 143 * // RegLowBat 144 * #define LOWBAT_MONITOR 0x10 145 * #define LOWBAT_ON 0x08 146 * #define LOWBAT_OFF 0x00 // Default 147 * 148 * #define LOWBAT_TRIM_1695 0x00 149 * #define LOWBAT_TRIM_1764 0x01 150 * #define LOWBAT_TRIM_1835 0x02 // Default 151 * #define LOWBAT_TRIM_1905 0x03 152 * #define LOWBAT_TRIM_1976 0x04 153 * #define LOWBAT_TRIM_2045 0x05 154 * #define LOWBAT_TRIM_2116 0x06 155 * #define LOWBAT_TRIM_2185 0x07 156 * 157 * 158 * // RegListen1 159 * #define LISTEN1_RESOL_64 0x50 160 * #define LISTEN1_RESOL_4100 0xA0 // Default 161 * #define LISTEN1_RESOL_262000 0xF0 162 * 163 * #define LISTEN1_CRITERIA_RSSI 0x00 // Default 164 * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 165 * 166 * #define LISTEN1_END_00 0x00 167 * #define LISTEN1_END_01 0x02 // Default 168 * #define LISTEN1_END_10 0x04 169 * 170 * 171 * // RegListen2 172 * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default 173 * 174 * // RegListen3 175 * #define LISTEN3_COEFRX_VALUE 0x20 // Default 176 */ 177 178// RegPaLevel 179#define MASK_PALEVEL_PA0 0x80 180#define MASK_PALEVEL_PA1 0x40 181#define MASK_PALEVEL_PA2 0x20 182#define MASK_PALEVEL_OUTPUT_POWER 0x1F 183 184// RegPaRamp 185#define PARAMP_3400 0x00 186#define PARAMP_2000 0x01 187#define PARAMP_1000 0x02 188#define PARAMP_500 0x03 189#define PARAMP_250 0x04 190#define PARAMP_125 0x05 191#define PARAMP_100 0x06 192#define PARAMP_62 0x07 193#define PARAMP_50 0x08 194#define PARAMP_40 0x09 /* default */ 195#define PARAMP_31 0x0A 196#define PARAMP_25 0x0B 197#define PARAMP_20 0x0C 198#define PARAMP_15 0x0D 199#define PARAMP_12 0x0E 200#define PARAMP_10 0x0F 201 202#define MASK_PARAMP 0x0F 203 204/* 205 * // RegOcp 206 * #define OCP_OFF 0x0F 207 * #define OCP_ON 0x1A // Default 208 * 209 * #define OCP_TRIM_45 0x00 210 * #define OCP_TRIM_50 0x01 211 * #define OCP_TRIM_55 0x02 212 * #define OCP_TRIM_60 0x03 213 * #define OCP_TRIM_65 0x04 214 * #define OCP_TRIM_70 0x05 215 * #define OCP_TRIM_75 0x06 216 * #define OCP_TRIM_80 0x07 217 * #define OCP_TRIM_85 0x08 218 * #define OCP_TRIM_90 0x09 219 * #define OCP_TRIM_95 0x0A 220 * #define OCP_TRIM_100 0x0B // Default 221 * #define OCP_TRIM_105 0x0C 222 * #define OCP_TRIM_110 0x0D 223 * #define OCP_TRIM_115 0x0E 224 * #define OCP_TRIM_120 0x0F 225 */ 226 227/* RegLna (0x18) */ 228#define MASK_LNA_ZIN 0x80 229#define MASK_LNA_CURRENT_GAIN 0x38 230#define MASK_LNA_GAIN 0x07 231 232#define LNA_GAIN_AUTO 0x00 /* default */ 233#define LNA_GAIN_MAX 0x01 234#define LNA_GAIN_MAX_MINUS_6 0x02 235#define LNA_GAIN_MAX_MINUS_12 0x03 236#define LNA_GAIN_MAX_MINUS_24 0x04 237#define LNA_GAIN_MAX_MINUS_36 0x05 238#define LNA_GAIN_MAX_MINUS_48 0x06 239 240/* RegRxBw (0x19) and RegAfcBw (0x1A) */ 241#define MASK_BW_DCC_FREQ 0xE0 242#define MASK_BW_MANTISSE 0x18 243#define MASK_BW_EXPONENT 0x07 244 245#define BW_DCC_16_PERCENT 0x00 246#define BW_DCC_8_PERCENT 0x20 247#define BW_DCC_4_PERCENT 0x40 /* default */ 248#define BW_DCC_2_PERCENT 0x60 249#define BW_DCC_1_PERCENT 0x80 250#define BW_DCC_0_5_PERCENT 0xA0 251#define BW_DCC_0_25_PERCENT 0xC0 252#define BW_DCC_0_125_PERCENT 0xE0 253 254#define BW_MANT_16 0x00 255#define BW_MANT_20 0x08 256#define BW_MANT_24 0x10 /* default */ 257 258/* RegOokPeak (0x1B) */ 259#define MASK_OOKPEAK_THRESTYPE 0xc0 260#define MASK_OOKPEAK_THRESSTEP 0x38 261#define MASK_OOKPEAK_THRESDEC 0x07 262 263#define OOKPEAK_THRESHTYPE_FIXED 0x00 264#define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ 265#define OOKPEAK_THRESHTYPE_AVERAGE 0x80 266 267#define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ 268#define OOKPEAK_THRESHSTEP_1_0_DB 0x08 269#define OOKPEAK_THRESHSTEP_1_5_DB 0x10 270#define OOKPEAK_THRESHSTEP_2_0_DB 0x18 271#define OOKPEAK_THRESHSTEP_3_0_DB 0x20 272#define OOKPEAK_THRESHSTEP_4_0_DB 0x28 273#define OOKPEAK_THRESHSTEP_5_0_DB 0x30 274#define OOKPEAK_THRESHSTEP_6_0_DB 0x38 275 276#define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ 277#define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 278#define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 279#define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 280#define OOKPEAK_THRESHDEC_TWICE 0x04 281#define OOKPEAK_THRESHDEC_4_TIMES 0x05 282#define OOKPEAK_THRESHDEC_8_TIMES 0x06 283#define OOKPEAK_THRESHDEC_16_TIMES 0x07 284 285/* 286 * // RegOokAvg 287 * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 288 * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 289 * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default 290 * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 291 * 292 * 293 * // RegAfcFei 294 * #define AFCFEI_FEI_DONE 0x40 295 * #define AFCFEI_FEI_START 0x20 296 * #define AFCFEI_AFC_DONE 0x10 297 * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 298 * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 299 * 300 * #define AFCFEI_AFCAUTO_ON 0x04 301 * #define AFCFEI_AFCAUTO_OFF 0x00 // Default 302 * 303 * #define AFCFEI_AFC_CLEAR 0x02 304 * #define AFCFEI_AFC_START 0x01 305 * 306 * // RegRssiConfig 307 * #define RSSI_FASTRX_ON 0x08 308 * #define RSSI_FASTRX_OFF 0x00 // Default 309 * #define RSSI_DONE 0x02 310 * #define RSSI_START 0x01 311 */ 312 313/* RegDioMapping1 */ 314#define MASK_DIO0 0xC0 315#define MASK_DIO1 0x30 316#define MASK_DIO2 0x0C 317#define MASK_DIO3 0x03 318#define SHIFT_DIO0 6 319#define SHIFT_DIO1 4 320#define SHIFT_DIO2 2 321#define SHIFT_DIO3 0 322 323/* RegDioMapping2 */ 324#define MASK_DIO4 0xC0 325#define MASK_DIO5 0x30 326#define SHIFT_DIO4 6 327#define SHIFT_DIO5 4 328 329/* DIO numbers */ 330#define DIO0 0 331#define DIO1 1 332#define DIO2 2 333#define DIO3 3 334#define DIO4 4 335#define DIO5 5 336 337/* DIO Mapping values (packet mode) */ 338#define DIO_MODE_READY_DIO4 0x00 339#define DIO_MODE_READY_DIO5 0x03 340#define DIO_CLK_OUT 0x00 341#define DIO_DATA 0x01 342#define DIO_TIMEOUT_DIO1 0x03 343#define DIO_TIMEOUT_DIO4 0x00 344#define DIO_RSSI_DIO0 0x03 345#define DIO_RSSI_DIO3_4 0x01 346#define DIO_RX_READY 0x02 347#define DIO_PLL_LOCK 0x03 348#define DIO_TX_READY 0x01 349#define DIO_FIFO_FULL_DIO1 0x01 350#define DIO_FIFO_FULL_DIO3 0x00 351#define DIO_SYNC_ADDRESS 0x02 352#define DIO_FIFO_NOT_EMPTY_DIO1 0x02 353#define DIO_FIFO_NOT_EMPTY_FIO2 0x00 354#define DIO_AUTOMODE 0x04 355#define DIO_FIFO_LEVEL 0x00 356#define DIO_CRC_OK 0x00 357#define DIO_PAYLOAD_READY 0x01 358#define DIO_PACKET_SENT 0x00 359#define DIO_DCLK 0x00 360 361/* RegDioMapping2 CLK_OUT part */ 362#define MASK_DIOMAPPING2_CLK_OUT 0x07 363 364#define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 365#define DIOMAPPING2_CLK_OUT_DIV_2 0x01 366#define DIOMAPPING2_CLK_OUT_DIV_4 0x02 367#define DIOMAPPING2_CLK_OUT_DIV_8 0x03 368#define DIOMAPPING2_CLK_OUT_DIV_16 0x04 369#define DIOMAPPING2_CLK_OUT_DIV_32 0x05 370#define DIOMAPPING2_CLK_OUT_RC 0x06 371#define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ 372 373/* RegIrqFlags1 */ 374#define MASK_IRQFLAGS1_MODE_READY 0x80 375#define MASK_IRQFLAGS1_RX_READY 0x40 376#define MASK_IRQFLAGS1_TX_READY 0x20 377#define MASK_IRQFLAGS1_PLL_LOCK 0x10 378#define MASK_IRQFLAGS1_RSSI 0x08 379#define MASK_IRQFLAGS1_TIMEOUT 0x04 380#define MASK_IRQFLAGS1_AUTOMODE 0x02 381#define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 382 383/* RegIrqFlags2 */ 384#define MASK_IRQFLAGS2_FIFO_FULL 0x80 385#define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 386#define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 387#define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 388#define MASK_IRQFLAGS2_PACKET_SENT 0x08 389#define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 390#define MASK_IRQFLAGS2_CRC_OK 0x02 391#define MASK_IRQFLAGS2_LOW_BAT 0x01 392 393/* RegSyncConfig */ 394#define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ 395#define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 396#define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 397#define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 398 399/* RegPacketConfig1 */ 400#define MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE 0x80 401#define MASK_PACKETCONFIG1_DCFREE 0x60 402#define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ 403#define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 404#define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 405 406#define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ 407#define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 408#define PACKETCONFIG1_DCFREE_WHITENING 0x40 409#define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ 410#define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 411#define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 412 413/* 414 * // RegAutoModes 415 * #define AUTOMODES_ENTER_OFF 0x00 // Default 416 * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 417 * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 418 * #define AUTOMODES_ENTER_CRCOK 0x60 419 * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 420 * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 421 * #define AUTOMODES_ENTER_PACKETSENT 0xC0 422 * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 423 * 424 * #define AUTOMODES_EXIT_OFF 0x00 // Default 425 * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 426 * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 427 * #define AUTOMODES_EXIT_CRCOK 0x0C 428 * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 429 * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 430 * #define AUTOMODES_EXIT_PACKETSENT 0x18 431 * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C 432 * 433 * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default 434 * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 435 * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 436 * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 437 * 438 */ 439/* RegFifoThresh (0x3c) */ 440#define MASK_FIFO_THRESH_TXSTART 0x80 441#define MASK_FIFO_THRESH_VALUE 0x7F 442 443/* 444 * 445 * // RegPacketConfig2 446 * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default 447 * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 448 * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 449 * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 450 * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 451 * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 452 * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 453 * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 454 * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 455 * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 456 * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 457 * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 458 * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 459 * #define PACKET2_RXRESTART 0x04 460 * 461 * #define PACKET2_AUTORXRESTART_ON 0x02 // Default 462 * #define PACKET2_AUTORXRESTART_OFF 0x00 463 * 464 * #define PACKET2_AES_ON 0x01 465 * #define PACKET2_AES_OFF 0x00 // Default 466 * 467 * 468 * // RegTemp1 469 * #define TEMP1_MEAS_START 0x08 470 * #define TEMP1_MEAS_RUNNING 0x04 471 * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default 472 * #define TEMP1_ADCLOWPOWER_OFF 0x00 473 */ 474 475// RegTestDagc (0x6F) 476#define DAGC_NORMAL 0x00 /* Reset value */ 477#define DAGC_IMPROVED_LOWBETA1 0x20 478#define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */ 479