1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#ifndef __TEGRA_VI_H__ 7#define __TEGRA_VI_H__ 8 9#include <linux/host1x.h> 10#include <linux/list.h> 11 12#include <linux/mutex.h> 13#include <linux/spinlock.h> 14#include <linux/wait.h> 15 16#include <media/media-entity.h> 17#include <media/v4l2-async.h> 18#include <media/v4l2-ctrls.h> 19#include <media/v4l2-device.h> 20#include <media/v4l2-dev.h> 21#include <media/v4l2-subdev.h> 22#include <media/videobuf2-v4l2.h> 23 24#include "csi.h" 25 26#define V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY (V4L2_CTRL_CLASS_CAMERA | 0x1001) 27 28#define TEGRA_DEF_WIDTH 1920 29#define TEGRA_DEF_HEIGHT 1080 30#define TEGRA_IMAGE_FORMAT_DEF 32 31 32#define MAX_FORMAT_NUM 64 33 34enum tegra_vi_pg_mode { 35 TEGRA_VI_PG_DISABLED = 0, 36 TEGRA_VI_PG_DIRECT, 37 TEGRA_VI_PG_PATCH, 38}; 39 40struct tegra_vi; 41struct tegra_vi_channel; 42 43/** 44 * struct tegra_vi_ops - Tegra VI operations 45 * @vi_enable: soc-specific operations needed to enable/disable the VI peripheral 46 * @channel_host1x_syncpt_init: initialize synchronization points 47 * @channel_host1x_syncpt_free: free all synchronization points 48 * @vi_fmt_align: modify `pix` to fit the hardware alignment 49 * requirements and fill image geometry 50 * @channel_queue_setup: additional operations at the end of vb2_ops::queue_setup 51 * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up 52 * VI for capture and runs capture start and capture finish 53 * kthreads for capturing frames to buffer and returns them back. 54 * @vi_stop_streaming: stops media pipeline and subdevice streaming and returns 55 * back any queued buffers. 56 */ 57struct tegra_vi_ops { 58 int (*vi_enable)(struct tegra_vi *vi, bool on); 59 int (*channel_host1x_syncpt_init)(struct tegra_vi_channel *chan); 60 void (*channel_host1x_syncpt_free)(struct tegra_vi_channel *chan); 61 void (*vi_fmt_align)(struct v4l2_pix_format *pix, unsigned int bpp); 62 void (*channel_queue_setup)(struct tegra_vi_channel *chan); 63 int (*vi_start_streaming)(struct vb2_queue *vq, u32 count); 64 void (*vi_stop_streaming)(struct vb2_queue *vq); 65}; 66 67/** 68 * struct tegra_vi_soc - NVIDIA Tegra Video Input SoC structure 69 * 70 * @video_formats: supported video formats 71 * @nformats: total video formats 72 * @default_video_format: default video format (pointer to a @video_formats item) 73 * @ops: vi operations 74 * @hw_revision: VI hw_revision 75 * @vi_max_channels: supported max streaming channels 76 * @vi_max_clk_hz: VI clock max frequency 77 * @has_h_v_flip: the chip can do H and V flip, and the driver implements it 78 */ 79struct tegra_vi_soc { 80 const struct tegra_video_format *video_formats; 81 const unsigned int nformats; 82 const struct tegra_video_format *default_video_format; 83 const struct tegra_vi_ops *ops; 84 u32 hw_revision; 85 unsigned int vi_max_channels; 86 unsigned int vi_max_clk_hz; 87 bool has_h_v_flip:1; 88}; 89 90/** 91 * struct tegra_vi - NVIDIA Tegra Video Input device structure 92 * 93 * @dev: device struct 94 * @client: host1x_client struct 95 * @iomem: register base 96 * @clk: main clock for VI block 97 * @vdd: vdd regulator for VI hardware, normally it is avdd_dsi_csi 98 * @soc: pointer to SoC data structure 99 * @ops: vi operations 100 * @vi_chans: list head for VI channels 101 */ 102struct tegra_vi { 103 struct device *dev; 104 struct host1x_client client; 105 void __iomem *iomem; 106 struct clk *clk; 107 struct regulator *vdd; 108 const struct tegra_vi_soc *soc; 109 const struct tegra_vi_ops *ops; 110 struct list_head vi_chans; 111}; 112 113/** 114 * struct tegra_vi_channel - Tegra video channel 115 * 116 * @list: list head for this entry 117 * @video: V4L2 video device associated with the video channel 118 * @video_lock: protects the @format and @queue fields 119 * @pad: media pad for the video device entity 120 * 121 * @vi: Tegra video input device structure 122 * @frame_start_sp: host1x syncpoint pointer to synchronize programmed capture 123 * start condition with hardware frame start events through host1x 124 * syncpoint counters. (Tegra210) 125 * @mw_ack_sp: host1x syncpoint pointer to synchronize programmed memory write 126 * ack trigger condition with hardware memory write done at end of 127 * frame through host1x syncpoint counters (On Tegra20 used for the 128 * OUT_1 syncpt) 129 * @sp_incr_lock: protects cpu syncpoint increment. 130 * @next_out_sp_idx: next expected value for mw_ack_sp[0], i.e. OUT_1 (Tegra20) 131 * 132 * @kthread_start_capture: kthread to start capture of single frame when 133 * vb buffer is available. This thread programs VI CSI hardware 134 * for single frame capture and waits for frame start event from 135 * the hardware. On receiving frame start event, it wakes up 136 * kthread_finish_capture thread to wait for finishing frame data 137 * write to the memory. In case of missing frame start event, this 138 * thread returns buffer back to vb with VB2_BUF_STATE_ERROR. 139 * @start_wait: waitqueue for starting frame capture when buffer is available. 140 * @kthread_finish_capture: kthread to finish the buffer capture and return to. 141 * This thread is woken up by kthread_start_capture on receiving 142 * frame start event from the hardware and this thread waits for 143 * MW_ACK_DONE event which indicates completion of writing frame 144 * data to the memory. On receiving MW_ACK_DONE event, buffer is 145 * returned back to vb with VB2_BUF_STATE_DONE and in case of 146 * missing MW_ACK_DONE event, buffer is returned back to vb with 147 * VB2_BUF_STATE_ERROR. 148 * @done_wait: waitqueue for finishing capture data writes to memory. 149 * 150 * @format: active V4L2 pixel format 151 * @fmtinfo: format information corresponding to the active @format 152 * @queue: vb2 buffers queue 153 * @sequence: V4L2 buffers sequence number 154 * 155 * @addr_offset_u: U plane base address, relative to buffer base address (only for planar) 156 * @addr_offset_v: V plane base address, relative to buffer base address (only for planar) 157 * @start_offset: 1st Y byte to write, relative to buffer base address (for H/V flip) 158 * @start_offset_u: 1st U byte to write, relative to buffer base address (for H/V flip) 159 * @start_offset_v: 1st V byte to write, relative to buffer base address (for H/V flip) 160 * 161 * @capture: list of queued buffers for capture 162 * @start_lock: protects the capture queued list 163 * @done: list of capture done queued buffers 164 * @done_lock: protects the capture done queue list 165 * 166 * @portnos: VI channel port numbers 167 * @totalports: total number of ports used for this channel 168 * @numgangports: number of ports combined together as a gang for capture 169 * @of_node: device node of VI channel 170 * 171 * @ctrl_handler: V4L2 control handler of this video channel 172 * @syncpt_timeout_retry: syncpt timeout retry count for the capture 173 * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats 174 * @tpg_fmts_bitmap: a bitmap for supported TPG formats 175 * @pg_mode: test pattern generator mode (disabled/direct/patch) 176 * @notifier: V4L2 asynchronous subdevs notifier 177 * 178 * @hflip: Horizontal flip is enabled 179 * @vflip: Vertical flip is enabled 180 */ 181struct tegra_vi_channel { 182 struct list_head list; 183 struct video_device video; 184 /* protects the @format and @queue fields */ 185 struct mutex video_lock; 186 struct media_pad pad; 187 188 struct tegra_vi *vi; 189 struct host1x_syncpt *frame_start_sp[GANG_PORTS_MAX]; 190 struct host1x_syncpt *mw_ack_sp[GANG_PORTS_MAX]; 191 /* protects the cpu syncpoint increment */ 192 spinlock_t sp_incr_lock[GANG_PORTS_MAX]; 193 u32 next_out_sp_idx; 194 195 struct task_struct *kthread_start_capture; 196 wait_queue_head_t start_wait; 197 struct task_struct *kthread_finish_capture; 198 wait_queue_head_t done_wait; 199 200 struct v4l2_pix_format format; 201 const struct tegra_video_format *fmtinfo; 202 struct vb2_queue queue; 203 u32 sequence; 204 205 unsigned int addr_offset_u; 206 unsigned int addr_offset_v; 207 unsigned int start_offset; 208 unsigned int start_offset_u; 209 unsigned int start_offset_v; 210 211 struct list_head capture; 212 /* protects the capture queued list */ 213 spinlock_t start_lock; 214 struct list_head done; 215 /* protects the capture done queue list */ 216 spinlock_t done_lock; 217 218 unsigned char portnos[GANG_PORTS_MAX]; 219 u8 totalports; 220 u8 numgangports; 221 struct device_node *of_node; 222 223 struct v4l2_ctrl_handler ctrl_handler; 224 unsigned int syncpt_timeout_retry; 225 DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); 226 DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); 227 enum tegra_vi_pg_mode pg_mode; 228 229 struct v4l2_async_notifier notifier; 230 231 bool hflip:1; 232 bool vflip:1; 233}; 234 235/** 236 * struct tegra_channel_buffer - video channel buffer 237 * 238 * @buf: vb2 buffer base object 239 * @queue: buffer list entry in the channel queued buffers list 240 * @chan: channel that uses the buffer 241 * @addr: Tegra IOVA buffer address for VI output 242 * @mw_ack_sp_thresh: MW_ACK_DONE syncpoint threshold corresponding 243 * to the capture buffer. 244 */ 245struct tegra_channel_buffer { 246 struct vb2_v4l2_buffer buf; 247 struct list_head queue; 248 struct tegra_vi_channel *chan; 249 dma_addr_t addr; 250 u32 mw_ack_sp_thresh[GANG_PORTS_MAX]; 251}; 252 253/* 254 * VI channel input data type enum. 255 * These data type enum value gets programmed into corresponding Tegra VI 256 * channel register bits. 257 */ 258enum tegra_image_dt { 259 TEGRA_IMAGE_DT_YUV420_8 = 24, 260 TEGRA_IMAGE_DT_YUV420_10, 261 262 TEGRA_IMAGE_DT_YUV420CSPS_8 = 28, 263 TEGRA_IMAGE_DT_YUV420CSPS_10, 264 TEGRA_IMAGE_DT_YUV422_8, 265 TEGRA_IMAGE_DT_YUV422_10, 266 TEGRA_IMAGE_DT_RGB444, 267 TEGRA_IMAGE_DT_RGB555, 268 TEGRA_IMAGE_DT_RGB565, 269 TEGRA_IMAGE_DT_RGB666, 270 TEGRA_IMAGE_DT_RGB888, 271 272 TEGRA_IMAGE_DT_RAW6 = 40, 273 TEGRA_IMAGE_DT_RAW7, 274 TEGRA_IMAGE_DT_RAW8, 275 TEGRA_IMAGE_DT_RAW10, 276 TEGRA_IMAGE_DT_RAW12, 277 TEGRA_IMAGE_DT_RAW14, 278}; 279 280/** 281 * struct tegra_video_format - Tegra video format description 282 * 283 * @img_dt: MIPI CSI-2 data type (for CSI-2 only) 284 * @bit_width: format width in bits per component (for CSI/Tegra210 only) 285 * @code: media bus format code 286 * @bpp: bytes per pixel (when stored in memory) 287 * @img_fmt: image format (for CSI/Tegra210 only) 288 * @fourcc: V4L2 pixel format FCC identifier 289 */ 290struct tegra_video_format { 291 enum tegra_image_dt img_dt; 292 unsigned int bit_width; 293 unsigned int code; 294 unsigned int bpp; 295 u32 img_fmt; 296 u32 fourcc; 297}; 298 299#if defined(CONFIG_ARCH_TEGRA_2x_SOC) 300extern const struct tegra_vi_soc tegra20_vi_soc; 301#endif 302#if defined(CONFIG_ARCH_TEGRA_210_SOC) 303extern const struct tegra_vi_soc tegra210_vi_soc; 304#endif 305 306struct v4l2_subdev * 307tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan); 308struct v4l2_subdev * 309tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan); 310int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); 311void tegra_channel_release_buffers(struct tegra_vi_channel *chan, 312 enum vb2_buffer_state state); 313void tegra_channels_cleanup(struct tegra_vi *vi); 314#endif 315