1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * stf_isp.h 4 * 5 * StarFive Camera Subsystem - ISP Module 6 * 7 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. 8 */ 9 10#ifndef STF_ISP_H 11#define STF_ISP_H 12 13#include <media/v4l2-subdev.h> 14 15#include "stf-video.h" 16 17#define ISP_RAW_DATA_BITS 12 18#define SCALER_RATIO_MAX 1 19#define STF_ISP_REG_OFFSET_MAX 0x0fff 20#define STF_ISP_REG_DELAY_MAX 100 21 22/* isp registers */ 23#define ISP_REG_CSI_INPUT_EN_AND_STATUS 0x000 24#define CSI_SCD_ERR BIT(6) 25#define CSI_ITU656_ERR BIT(4) 26#define CSI_ITU656_F BIT(3) 27#define CSI_SCD_DONE BIT(2) 28#define CSI_BUSY_S BIT(1) 29#define CSI_EN_S BIT(0) 30 31#define ISP_REG_CSIINTS 0x008 32#define CSI_INTS(n) ((n) << 16) 33#define CSI_SHA_M(n) ((n) << 0) 34#define CSI_INTS_MASK GENMASK(17, 16) 35 36#define ISP_REG_CSI_MODULE_CFG 0x010 37#define CSI_DUMP_EN BIT(19) 38#define CSI_VS_EN BIT(18) 39#define CSI_SC_EN BIT(17) 40#define CSI_OBA_EN BIT(16) 41#define CSI_AWB_EN BIT(7) 42#define CSI_LCCF_EN BIT(6) 43#define CSI_OECFHM_EN BIT(5) 44#define CSI_OECF_EN BIT(4) 45#define CSI_LCBQ_EN BIT(3) 46#define CSI_OBC_EN BIT(2) 47#define CSI_DEC_EN BIT(1) 48#define CSI_DC_EN BIT(0) 49 50#define ISP_REG_SENSOR 0x014 51#define DVP_SYNC_POL(n) ((n) << 2) 52#define ITU656_EN(n) ((n) << 1) 53#define IMAGER_SEL(n) ((n) << 0) 54 55#define ISP_REG_RAW_FORMAT_CFG 0x018 56#define SMY13(n) ((n) << 14) 57#define SMY12(n) ((n) << 12) 58#define SMY11(n) ((n) << 10) 59#define SMY10(n) ((n) << 8) 60#define SMY3(n) ((n) << 6) 61#define SMY2(n) ((n) << 4) 62#define SMY1(n) ((n) << 2) 63#define SMY0(n) ((n) << 0) 64 65#define ISP_REG_PIC_CAPTURE_START_CFG 0x01c 66#define VSTART_CAP(n) ((n) << 16) 67#define HSTART_CAP(n) ((n) << 0) 68 69#define ISP_REG_PIC_CAPTURE_END_CFG 0x020 70#define VEND_CAP(n) ((n) << 16) 71#define HEND_CAP(n) ((n) << 0) 72 73#define ISP_REG_DUMP_CFG_0 0x024 74#define ISP_REG_DUMP_CFG_1 0x028 75#define DUMP_ID(n) ((n) << 24) 76#define DUMP_SHT(n) ((n) << 20) 77#define DUMP_BURST_LEN(n) ((n) << 16) 78#define DUMP_SD(n) ((n) << 0) 79#define DUMP_BURST_LEN_MASK GENMASK(17, 16) 80#define DUMP_SD_MASK GENMASK(15, 0) 81 82#define ISP_REG_DEC_CFG 0x030 83#define DEC_V_KEEP(n) ((n) << 24) 84#define DEC_V_PERIOD(n) ((n) << 16) 85#define DEC_H_KEEP(n) ((n) << 8) 86#define DEC_H_PERIOD(n) ((n) << 0) 87 88#define ISP_REG_OBC_CFG 0x034 89#define OBC_W_H(y) ((y) << 4) 90#define OBC_W_W(x) ((x) << 0) 91 92#define ISP_REG_DC_CFG_1 0x044 93#define DC_AXI_ID(n) ((n) << 0) 94 95#define ISP_REG_LCCF_CFG_0 0x050 96#define Y_DISTANCE(y) ((y) << 16) 97#define X_DISTANCE(x) ((x) << 0) 98 99#define ISP_REG_LCCF_CFG_1 0x058 100#define LCCF_MAX_DIS(n) ((n) << 0) 101 102#define ISP_REG_LCBQ_CFG_0 0x074 103#define H_LCBQ(y) ((y) << 12) 104#define W_LCBQ(x) ((x) << 8) 105 106#define ISP_REG_LCBQ_CFG_1 0x07c 107#define Y_COOR(y) ((y) << 16) 108#define X_COOR(x) ((x) << 0) 109 110#define ISP_REG_LCCF_CFG_2 0x0e0 111#define ISP_REG_LCCF_CFG_3 0x0e4 112#define ISP_REG_LCCF_CFG_4 0x0e8 113#define ISP_REG_LCCF_CFG_5 0x0ec 114#define LCCF_F2_PAR(n) ((n) << 16) 115#define LCCF_F1_PAR(n) ((n) << 0) 116 117#define ISP_REG_OECF_X0_CFG0 0x100 118#define ISP_REG_OECF_X0_CFG1 0x104 119#define ISP_REG_OECF_X0_CFG2 0x108 120#define ISP_REG_OECF_X0_CFG3 0x10c 121#define ISP_REG_OECF_X0_CFG4 0x110 122#define ISP_REG_OECF_X0_CFG5 0x114 123#define ISP_REG_OECF_X0_CFG6 0x118 124#define ISP_REG_OECF_X0_CFG7 0x11c 125 126#define ISP_REG_OECF_Y3_CFG0 0x1e0 127#define ISP_REG_OECF_Y3_CFG1 0x1e4 128#define ISP_REG_OECF_Y3_CFG2 0x1e8 129#define ISP_REG_OECF_Y3_CFG3 0x1ec 130#define ISP_REG_OECF_Y3_CFG4 0x1f0 131#define ISP_REG_OECF_Y3_CFG5 0x1f4 132#define ISP_REG_OECF_Y3_CFG6 0x1f8 133#define ISP_REG_OECF_Y3_CFG7 0x1fc 134 135#define ISP_REG_OECF_S0_CFG0 0x200 136#define ISP_REG_OECF_S3_CFG7 0x27c 137#define OCEF_PAR_H(n) ((n) << 16) 138#define OCEF_PAR_L(n) ((n) << 0) 139 140#define ISP_REG_AWB_X0_CFG_0 0x280 141#define ISP_REG_AWB_X0_CFG_1 0x284 142#define ISP_REG_AWB_X1_CFG_0 0x288 143#define ISP_REG_AWB_X1_CFG_1 0x28c 144#define ISP_REG_AWB_X2_CFG_0 0x290 145#define ISP_REG_AWB_X2_CFG_1 0x294 146#define ISP_REG_AWB_X3_CFG_0 0x298 147#define ISP_REG_AWB_X3_CFG_1 0x29c 148#define AWB_X_SYMBOL_H(n) ((n) << 16) 149#define AWB_X_SYMBOL_L(n) ((n) << 0) 150 151#define ISP_REG_AWB_Y0_CFG_0 0x2a0 152#define ISP_REG_AWB_Y0_CFG_1 0x2a4 153#define ISP_REG_AWB_Y1_CFG_0 0x2a8 154#define ISP_REG_AWB_Y1_CFG_1 0x2ac 155#define ISP_REG_AWB_Y2_CFG_0 0x2b0 156#define ISP_REG_AWB_Y2_CFG_1 0x2b4 157#define ISP_REG_AWB_Y3_CFG_0 0x2b8 158#define ISP_REG_AWB_Y3_CFG_1 0x2bc 159#define AWB_Y_SYMBOL_H(n) ((n) << 16) 160#define AWB_Y_SYMBOL_L(n) ((n) << 0) 161 162#define ISP_REG_AWB_S0_CFG_0 0x2c0 163#define ISP_REG_AWB_S0_CFG_1 0x2c4 164#define ISP_REG_AWB_S1_CFG_0 0x2c8 165#define ISP_REG_AWB_S1_CFG_1 0x2cc 166#define ISP_REG_AWB_S2_CFG_0 0x2d0 167#define ISP_REG_AWB_S2_CFG_1 0x2d4 168#define ISP_REG_AWB_S3_CFG_0 0x2d8 169#define ISP_REG_AWB_S3_CFG_1 0x2dc 170#define AWB_S_SYMBOL_H(n) ((n) << 16) 171#define AWB_S_SYMBOL_L(n) ((n) << 0) 172 173#define ISP_REG_OBCG_CFG_0 0x2e0 174#define ISP_REG_OBCG_CFG_1 0x2e4 175#define ISP_REG_OBCG_CFG_2 0x2e8 176#define ISP_REG_OBCG_CFG_3 0x2ec 177#define ISP_REG_OBCO_CFG_0 0x2f0 178#define ISP_REG_OBCO_CFG_1 0x2f4 179#define ISP_REG_OBCO_CFG_2 0x2f8 180#define ISP_REG_OBCO_CFG_3 0x2fc 181#define GAIN_D_POINT(x) ((x) << 24) 182#define GAIN_C_POINT(x) ((x) << 16) 183#define GAIN_B_POINT(x) ((x) << 8) 184#define GAIN_A_POINT(x) ((x) << 0) 185#define OFFSET_D_POINT(x) ((x) << 24) 186#define OFFSET_C_POINT(x) ((x) << 16) 187#define OFFSET_B_POINT(x) ((x) << 8) 188#define OFFSET_A_POINT(x) ((x) << 0) 189 190#define ISP_REG_ISP_CTRL_0 0xa00 191#define ISPC_LINE BIT(27) 192#define ISPC_SC BIT(26) 193#define ISPC_CSI BIT(25) 194#define ISPC_ISP BIT(24) 195#define ISPC_ENUO BIT(20) 196#define ISPC_ENLS BIT(17) 197#define ISPC_ENSS1 BIT(12) 198#define ISPC_ENSS0 BIT(11) 199#define ISPC_RST BIT(1) 200#define ISPC_EN BIT(0) 201#define ISPC_RST_MASK BIT(1) 202#define ISPC_INT_ALL_MASK GENMASK(27, 24) 203 204#define ISP_REG_ISP_CTRL_1 0xa08 205#define CTRL_SAT(n) ((n) << 28) 206#define CTRL_DBC BIT(22) 207#define CTRL_CTC BIT(21) 208#define CTRL_YHIST BIT(20) 209#define CTRL_YCURVE BIT(19) 210#define CTRL_CTM BIT(18) 211#define CTRL_BIYUV BIT(17) 212#define CTRL_SCE BIT(8) 213#define CTRL_EE BIT(7) 214#define CTRL_CCE BIT(5) 215#define CTRL_RGE BIT(4) 216#define CTRL_CME BIT(3) 217#define CTRL_AE BIT(2) 218#define CTRL_CE BIT(1) 219#define CTRL_SAT_MASK GENMASK(31, 28) 220 221#define ISP_REG_PIPELINE_XY_SIZE 0xa0c 222#define H_ACT_CAP(n) ((n) << 16) 223#define W_ACT_CAP(n) ((n) << 0) 224 225#define ISP_REG_ICTC 0xa10 226#define GF_MODE(n) ((n) << 30) 227#define MAXGT(n) ((n) << 16) 228#define MINGT(n) ((n) << 0) 229 230#define ISP_REG_IDBC 0xa14 231#define BADGT(n) ((n) << 16) 232#define BADXT(n) ((n) << 0) 233 234#define ISP_REG_ICFAM 0xa1c 235#define CROSS_COV(n) ((n) << 4) 236#define HV_W(n) ((n) << 0) 237 238#define ISP_REG_CS_GAIN 0xa30 239#define CMAD(n) ((n) << 16) 240#define CMAB(n) ((n) << 0) 241 242#define ISP_REG_CS_THRESHOLD 0xa34 243#define CMD(n) ((n) << 16) 244#define CMB(n) ((n) << 0) 245 246#define ISP_REG_CS_OFFSET 0xa38 247#define VOFF(n) ((n) << 16) 248#define UOFF(n) ((n) << 0) 249 250#define ISP_REG_CS_HUE_F 0xa3c 251#define SIN(n) ((n) << 16) 252#define COS(n) ((n) << 0) 253 254#define ISP_REG_CS_SCALE 0xa40 255 256#define ISP_REG_IESHD 0xa50 257#define SHAD_UP_M BIT(1) 258#define SHAD_UP_EN BIT(0) 259 260#define ISP_REG_YADJ0 0xa54 261#define YOIR(n) ((n) << 16) 262#define YIMIN(n) ((n) << 0) 263 264#define ISP_REG_YADJ1 0xa58 265#define YOMAX(n) ((n) << 16) 266#define YOMIN(n) ((n) << 0) 267 268#define ISP_REG_Y_PLANE_START_ADDR 0xa80 269#define ISP_REG_UV_PLANE_START_ADDR 0xa84 270#define ISP_REG_STRIDE 0xa88 271 272#define ISP_REG_ITIIWSR 0xb20 273#define ITI_HSIZE(n) ((n) << 16) 274#define ITI_WSIZE(n) ((n) << 0) 275 276#define ISP_REG_ITIDWLSR 0xb24 277#define ISP_REG_ITIPDFR 0xb38 278#define ISP_REG_ITIDRLSR 0xb3C 279 280#define ISP_REG_DNYUV_YSWR0 0xc00 281#define ISP_REG_DNYUV_YSWR1 0xc04 282#define ISP_REG_DNYUV_CSWR0 0xc08 283#define ISP_REG_DNYUV_CSWR1 0xc0c 284#define YUVSW5(n) ((n) << 20) 285#define YUVSW4(n) ((n) << 16) 286#define YUVSW3(n) ((n) << 12) 287#define YUVSW2(n) ((n) << 8) 288#define YUVSW1(n) ((n) << 4) 289#define YUVSW0(n) ((n) << 0) 290 291#define ISP_REG_DNYUV_YDR0 0xc10 292#define ISP_REG_DNYUV_YDR1 0xc14 293#define ISP_REG_DNYUV_YDR2 0xc18 294#define ISP_REG_DNYUV_CDR0 0xc1c 295#define ISP_REG_DNYUV_CDR1 0xc20 296#define ISP_REG_DNYUV_CDR2 0xc24 297#define CURVE_D_H(n) ((n) << 16) 298#define CURVE_D_L(n) ((n) << 0) 299 300#define ISP_REG_ICAMD_0 0xc40 301#define ISP_REG_ICAMD_12 0xc70 302#define ISP_REG_ICAMD_20 0xc90 303#define ISP_REG_ICAMD_24 0xca0 304#define ISP_REG_ICAMD_25 0xca4 305#define DNRM_F(n) ((n) << 16) 306#define CCM_M_DAT(n) ((n) << 0) 307 308#define ISP_REG_GAMMA_VAL0 0xe00 309#define ISP_REG_GAMMA_VAL1 0xe04 310#define ISP_REG_GAMMA_VAL2 0xe08 311#define ISP_REG_GAMMA_VAL3 0xe0c 312#define ISP_REG_GAMMA_VAL4 0xe10 313#define ISP_REG_GAMMA_VAL5 0xe14 314#define ISP_REG_GAMMA_VAL6 0xe18 315#define ISP_REG_GAMMA_VAL7 0xe1c 316#define ISP_REG_GAMMA_VAL8 0xe20 317#define ISP_REG_GAMMA_VAL9 0xe24 318#define ISP_REG_GAMMA_VAL10 0xe28 319#define ISP_REG_GAMMA_VAL11 0xe2c 320#define ISP_REG_GAMMA_VAL12 0xe30 321#define ISP_REG_GAMMA_VAL13 0xe34 322#define ISP_REG_GAMMA_VAL14 0xe38 323#define GAMMA_S_VAL(n) ((n) << 16) 324#define GAMMA_VAL(n) ((n) << 0) 325 326#define ISP_REG_R2Y_0 0xe40 327#define ISP_REG_R2Y_1 0xe44 328#define ISP_REG_R2Y_2 0xe48 329#define ISP_REG_R2Y_3 0xe4c 330#define ISP_REG_R2Y_4 0xe50 331#define ISP_REG_R2Y_5 0xe54 332#define ISP_REG_R2Y_6 0xe58 333#define ISP_REG_R2Y_7 0xe5c 334#define ISP_REG_R2Y_8 0xe60 335 336#define ISP_REG_SHARPEN0 0xe80 337#define ISP_REG_SHARPEN1 0xe84 338#define ISP_REG_SHARPEN2 0xe88 339#define ISP_REG_SHARPEN3 0xe8c 340#define ISP_REG_SHARPEN4 0xe90 341#define ISP_REG_SHARPEN5 0xe94 342#define ISP_REG_SHARPEN6 0xe98 343#define ISP_REG_SHARPEN7 0xe9c 344#define ISP_REG_SHARPEN8 0xea0 345#define ISP_REG_SHARPEN9 0xea4 346#define ISP_REG_SHARPEN10 0xea8 347#define ISP_REG_SHARPEN11 0xeac 348#define ISP_REG_SHARPEN12 0xeb0 349#define ISP_REG_SHARPEN13 0xeb4 350#define ISP_REG_SHARPEN14 0xeb8 351#define S_DELTA(n) ((n) << 16) 352#define S_WEIGHT(n) ((n) << 8) 353 354#define ISP_REG_SHARPEN_FS0 0xebc 355#define ISP_REG_SHARPEN_FS1 0xec0 356#define ISP_REG_SHARPEN_FS2 0xec4 357#define ISP_REG_SHARPEN_FS3 0xec8 358#define ISP_REG_SHARPEN_FS4 0xecc 359#define ISP_REG_SHARPEN_FS5 0xed0 360#define S_FACTOR(n) ((n) << 24) 361#define S_SLOPE(n) ((n) << 0) 362 363#define ISP_REG_SHARPEN_WN 0xed4 364#define PDIRF(n) ((n) << 28) 365#define NDIRF(n) ((n) << 24) 366#define WSUM(n) ((n) << 0) 367 368#define ISP_REG_IUVS1 0xed8 369#define UVDIFF2(n) ((n) << 16) 370#define UVDIFF1(n) ((n) << 0) 371 372#define ISP_REG_IUVS2 0xedc 373#define UVF(n) ((n) << 24) 374#define UVSLOPE(n) ((n) << 0) 375 376#define ISP_REG_IUVCKS1 0xee0 377#define UVCKDIFF2(n) ((n) << 16) 378#define UVCKDIFF1(n) ((n) << 0) 379 380#define ISP_REG_IUVCKS2 0xee4 381 382#define ISP_REG_ISHRPET 0xee8 383#define TH(n) ((n) << 8) 384#define EN(n) ((n) << 0) 385 386#define ISP_REG_YCURVE_0 0xf00 387#define ISP_REG_YCURVE_63 0xffc 388 389#define IMAGE_MAX_WIDTH 1920 390#define IMAGE_MAX_HEIGH 1080 391 392/* pad id for media framework */ 393enum stf_isp_pad_id { 394 STF_ISP_PAD_SINK = 0, 395 STF_ISP_PAD_SRC, 396 STF_ISP_PAD_MAX 397}; 398 399struct stf_isp_format { 400 u32 code; 401 u8 bpp; 402}; 403 404struct stf_isp_format_table { 405 const struct stf_isp_format *fmts; 406 int nfmts; 407}; 408 409struct stf_isp_dev { 410 struct stfcamss *stfcamss; 411 struct v4l2_subdev subdev; 412 struct media_pad pads[STF_ISP_PAD_MAX]; 413 const struct stf_isp_format_table *formats; 414 unsigned int nformats; 415 struct v4l2_subdev *source_subdev; 416 const struct stf_isp_format *current_fmt; 417}; 418 419int stf_isp_reset(struct stf_isp_dev *isp_dev); 420void stf_isp_init_cfg(struct stf_isp_dev *isp_dev); 421void stf_isp_settings(struct stf_isp_dev *isp_dev, 422 struct v4l2_rect *crop, u32 mcode); 423void stf_isp_stream_set(struct stf_isp_dev *isp_dev); 424int stf_isp_init(struct stfcamss *stfcamss); 425int stf_isp_register(struct stf_isp_dev *isp_dev, struct v4l2_device *v4l2_dev); 426int stf_isp_unregister(struct stf_isp_dev *isp_dev); 427 428#endif /* STF_ISP_H */ 429