1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __ATMEL_ISC_REGS_H 3#define __ATMEL_ISC_REGS_H 4 5#include <linux/bitops.h> 6 7/* ISC Control Enable Register 0 */ 8#define ISC_CTRLEN 0x00000000 9 10/* ISC Control Disable Register 0 */ 11#define ISC_CTRLDIS 0x00000004 12 13/* ISC Control Status Register 0 */ 14#define ISC_CTRLSR 0x00000008 15 16#define ISC_CTRL_CAPTURE BIT(0) 17#define ISC_CTRL_UPPRO BIT(1) 18#define ISC_CTRL_HISREQ BIT(2) 19#define ISC_CTRL_HISCLR BIT(3) 20 21/* ISC Parallel Front End Configuration 0 Register */ 22#define ISC_PFE_CFG0 0x0000000c 23 24#define ISC_PFE_CFG0_HPOL_LOW BIT(0) 25#define ISC_PFE_CFG0_VPOL_LOW BIT(1) 26#define ISC_PFE_CFG0_PPOL_LOW BIT(2) 27#define ISC_PFE_CFG0_CCIR656 BIT(9) 28#define ISC_PFE_CFG0_CCIR_CRC BIT(10) 29#define ISC_PFE_CFG0_MIPI BIT(14) 30 31#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) 32#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) 33 34#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28) 35#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28) 36#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28) 37#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28) 38#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28) 39#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28) 40 41#define ISC_PFE_CFG0_COLEN BIT(12) 42#define ISC_PFE_CFG0_ROWEN BIT(13) 43 44/* ISC Parallel Front End Configuration 1 Register */ 45#define ISC_PFE_CFG1 0x00000010 46 47#define ISC_PFE_CFG1_COLMIN(v) ((v)) 48#define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0) 49#define ISC_PFE_CFG1_COLMAX(v) ((v) << 16) 50#define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16) 51 52/* ISC Parallel Front End Configuration 2 Register */ 53#define ISC_PFE_CFG2 0x00000014 54 55#define ISC_PFE_CFG2_ROWMIN(v) ((v)) 56#define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0) 57#define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16) 58#define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16) 59 60/* ISC Clock Enable Register */ 61#define ISC_CLKEN 0x00000018 62 63/* ISC Clock Disable Register */ 64#define ISC_CLKDIS 0x0000001c 65 66/* ISC Clock Status Register */ 67#define ISC_CLKSR 0x00000020 68#define ISC_CLKSR_SIP BIT(31) 69 70#define ISC_CLK(n) BIT(n) 71 72/* ISC Clock Configuration Register */ 73#define ISC_CLKCFG 0x00000024 74#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16) 75#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16) 76#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8) 77#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8)) 78 79/* ISC Interrupt Enable Register */ 80#define ISC_INTEN 0x00000028 81 82/* ISC Interrupt Disable Register */ 83#define ISC_INTDIS 0x0000002c 84 85/* ISC Interrupt Mask Register */ 86#define ISC_INTMASK 0x00000030 87 88/* ISC Interrupt Status Register */ 89#define ISC_INTSR 0x00000034 90 91#define ISC_INT_DDONE BIT(8) 92#define ISC_INT_HISDONE BIT(12) 93 94/* ISC DPC Control Register */ 95#define ISC_DPC_CTRL 0x40 96 97#define ISC_DPC_CTRL_DPCEN BIT(0) 98#define ISC_DPC_CTRL_GDCEN BIT(1) 99#define ISC_DPC_CTRL_BLCEN BIT(2) 100 101/* ISC DPC Config Register */ 102#define ISC_DPC_CFG 0x44 103 104#define ISC_DPC_CFG_BAYSEL_SHIFT 0 105 106#define ISC_DPC_CFG_EITPOL BIT(4) 107 108#define ISC_DPC_CFG_TA_ENABLE BIT(14) 109#define ISC_DPC_CFG_TC_ENABLE BIT(13) 110#define ISC_DPC_CFG_TM_ENABLE BIT(12) 111 112#define ISC_DPC_CFG_RE_MODE BIT(17) 113 114#define ISC_DPC_CFG_GDCCLP_SHIFT 20 115#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) 116 117#define ISC_DPC_CFG_BLOFF_SHIFT 24 118#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) 119 120#define ISC_DPC_CFG_BAYCFG_SHIFT 0 121#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) 122/* ISC DPC Threshold Median Register */ 123#define ISC_DPC_THRESHM 0x48 124 125/* ISC DPC Threshold Closest Register */ 126#define ISC_DPC_THRESHC 0x4C 127 128/* ISC DPC Threshold Average Register */ 129#define ISC_DPC_THRESHA 0x50 130 131/* ISC DPC STatus Register */ 132#define ISC_DPC_SR 0x54 133 134/* ISC White Balance Control Register */ 135#define ISC_WB_CTRL 0x00000058 136 137/* ISC White Balance Configuration Register */ 138#define ISC_WB_CFG 0x0000005c 139 140/* ISC White Balance Offset for R, GR Register */ 141#define ISC_WB_O_RGR 0x00000060 142 143/* ISC White Balance Offset for B, GB Register */ 144#define ISC_WB_O_BGB 0x00000064 145 146/* ISC White Balance Gain for R, GR Register */ 147#define ISC_WB_G_RGR 0x00000068 148 149/* ISC White Balance Gain for B, GB Register */ 150#define ISC_WB_G_BGB 0x0000006c 151 152/* ISC Color Filter Array Control Register */ 153#define ISC_CFA_CTRL 0x00000070 154 155/* ISC Color Filter Array Configuration Register */ 156#define ISC_CFA_CFG 0x00000074 157#define ISC_CFA_CFG_EITPOL BIT(4) 158 159#define ISC_BAY_CFG_GRGR 0x0 160#define ISC_BAY_CFG_RGRG 0x1 161#define ISC_BAY_CFG_GBGB 0x2 162#define ISC_BAY_CFG_BGBG 0x3 163 164/* ISC Color Correction Control Register */ 165#define ISC_CC_CTRL 0x00000078 166 167/* ISC Color Correction RR RG Register */ 168#define ISC_CC_RR_RG 0x0000007c 169 170/* ISC Color Correction RB OR Register */ 171#define ISC_CC_RB_OR 0x00000080 172 173/* ISC Color Correction GR GG Register */ 174#define ISC_CC_GR_GG 0x00000084 175 176/* ISC Color Correction GB OG Register */ 177#define ISC_CC_GB_OG 0x00000088 178 179/* ISC Color Correction BR BG Register */ 180#define ISC_CC_BR_BG 0x0000008c 181 182/* ISC Color Correction BB OB Register */ 183#define ISC_CC_BB_OB 0x00000090 184 185/* ISC Gamma Correction Control Register */ 186#define ISC_GAM_CTRL 0x00000094 187 188#define ISC_GAM_CTRL_BIPART BIT(4) 189 190/* ISC_Gamma Correction Blue Entry Register */ 191#define ISC_GAM_BENTRY 0x00000098 192 193/* ISC_Gamma Correction Green Entry Register */ 194#define ISC_GAM_GENTRY 0x00000198 195 196/* ISC_Gamma Correction Green Entry Register */ 197#define ISC_GAM_RENTRY 0x00000298 198 199/* ISC VHXS Control Register */ 200#define ISC_VHXS_CTRL 0x398 201 202/* ISC VHXS Source Size Register */ 203#define ISC_VHXS_SS 0x39C 204 205/* ISC VHXS Destination Size Register */ 206#define ISC_VHXS_DS 0x3A0 207 208/* ISC Vertical Factor Register */ 209#define ISC_VXS_FACT 0x3a4 210 211/* ISC Horizontal Factor Register */ 212#define ISC_HXS_FACT 0x3a8 213 214/* ISC Vertical Config Register */ 215#define ISC_VXS_CFG 0x3ac 216 217/* ISC Horizontal Config Register */ 218#define ISC_HXS_CFG 0x3b0 219 220/* ISC Vertical Tap Register */ 221#define ISC_VXS_TAP 0x3b4 222 223/* ISC Horizontal Tap Register */ 224#define ISC_HXS_TAP 0x434 225 226/* Offset for CSC register specific to sama5d2 product */ 227#define ISC_SAMA5D2_CSC_OFFSET 0 228/* Offset for CSC register specific to sama7g5 product */ 229#define ISC_SAMA7G5_CSC_OFFSET 0x11c 230 231/* Color Space Conversion Control Register */ 232#define ISC_CSC_CTRL 0x00000398 233 234/* Color Space Conversion YR YG Register */ 235#define ISC_CSC_YR_YG 0x0000039c 236 237/* Color Space Conversion YB OY Register */ 238#define ISC_CSC_YB_OY 0x000003a0 239 240/* Color Space Conversion CBR CBG Register */ 241#define ISC_CSC_CBR_CBG 0x000003a4 242 243/* Color Space Conversion CBB OCB Register */ 244#define ISC_CSC_CBB_OCB 0x000003a8 245 246/* Color Space Conversion CRR CRG Register */ 247#define ISC_CSC_CRR_CRG 0x000003ac 248 249/* Color Space Conversion CRB OCR Register */ 250#define ISC_CSC_CRB_OCR 0x000003b0 251 252/* Offset for CBC register specific to sama5d2 product */ 253#define ISC_SAMA5D2_CBC_OFFSET 0 254/* Offset for CBC register specific to sama7g5 product */ 255#define ISC_SAMA7G5_CBC_OFFSET 0x11c 256 257/* Contrast And Brightness Control Register */ 258#define ISC_CBC_CTRL 0x000003b4 259 260/* Contrast And Brightness Configuration Register */ 261#define ISC_CBC_CFG 0x000003b8 262 263/* Brightness Register */ 264#define ISC_CBC_BRIGHT 0x000003bc 265#define ISC_CBC_BRIGHT_MASK GENMASK(10, 0) 266 267/* Contrast Register */ 268#define ISC_CBC_CONTRAST 0x000003c0 269#define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) 270 271/* Hue Register */ 272#define ISC_CBCHS_HUE 0x4e0 273/* Saturation Register */ 274#define ISC_CBCHS_SAT 0x4e4 275 276/* Offset for SUB422 register specific to sama5d2 product */ 277#define ISC_SAMA5D2_SUB422_OFFSET 0 278/* Offset for SUB422 register specific to sama7g5 product */ 279#define ISC_SAMA7G5_SUB422_OFFSET 0x124 280 281/* Subsampling 4:4:4 to 4:2:2 Control Register */ 282#define ISC_SUB422_CTRL 0x000003c4 283 284/* Offset for SUB420 register specific to sama5d2 product */ 285#define ISC_SAMA5D2_SUB420_OFFSET 0 286/* Offset for SUB420 register specific to sama7g5 product */ 287#define ISC_SAMA7G5_SUB420_OFFSET 0x124 288/* Subsampling 4:2:2 to 4:2:0 Control Register */ 289#define ISC_SUB420_CTRL 0x000003cc 290 291/* Offset for RLP register specific to sama5d2 product */ 292#define ISC_SAMA5D2_RLP_OFFSET 0 293/* Offset for RLP register specific to sama7g5 product */ 294#define ISC_SAMA7G5_RLP_OFFSET 0x124 295/* Rounding, Limiting and Packing Configuration Register */ 296#define ISC_RLP_CFG 0x000003d0 297 298#define ISC_RLP_CFG_MODE_DAT8 0x0 299#define ISC_RLP_CFG_MODE_DAT9 0x1 300#define ISC_RLP_CFG_MODE_DAT10 0x2 301#define ISC_RLP_CFG_MODE_DAT11 0x3 302#define ISC_RLP_CFG_MODE_DAT12 0x4 303#define ISC_RLP_CFG_MODE_DATY8 0x5 304#define ISC_RLP_CFG_MODE_DATY10 0x6 305#define ISC_RLP_CFG_MODE_ARGB444 0x7 306#define ISC_RLP_CFG_MODE_ARGB555 0x8 307#define ISC_RLP_CFG_MODE_RGB565 0x9 308#define ISC_RLP_CFG_MODE_ARGB32 0xa 309#define ISC_RLP_CFG_MODE_YYCC 0xb 310#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc 311#define ISC_RLP_CFG_MODE_YCYC 0xd 312#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) 313 314#define ISC_RLP_CFG_LSH BIT(5) 315 316#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) 317#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) 318#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) 319#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) 320 321#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) 322 323/* Offset for HIS register specific to sama5d2 product */ 324#define ISC_SAMA5D2_HIS_OFFSET 0 325/* Offset for HIS register specific to sama7g5 product */ 326#define ISC_SAMA7G5_HIS_OFFSET 0x124 327/* Histogram Control Register */ 328#define ISC_HIS_CTRL 0x000003d4 329 330#define ISC_HIS_CTRL_EN BIT(0) 331#define ISC_HIS_CTRL_DIS 0x0 332 333/* Histogram Configuration Register */ 334#define ISC_HIS_CFG 0x000003d8 335 336#define ISC_HIS_CFG_MODE_GR 0x0 337#define ISC_HIS_CFG_MODE_R 0x1 338#define ISC_HIS_CFG_MODE_GB 0x2 339#define ISC_HIS_CFG_MODE_B 0x3 340#define ISC_HIS_CFG_MODE_Y 0x4 341#define ISC_HIS_CFG_MODE_RAW 0x5 342#define ISC_HIS_CFG_MODE_YCCIR656 0x6 343 344#define ISC_HIS_CFG_BAYSEL_SHIFT 4 345 346#define ISC_HIS_CFG_RAR BIT(8) 347 348/* Offset for DMA register specific to sama5d2 product */ 349#define ISC_SAMA5D2_DMA_OFFSET 0 350/* Offset for DMA register specific to sama7g5 product */ 351#define ISC_SAMA7G5_DMA_OFFSET 0x13c 352 353/* DMA Configuration Register */ 354#define ISC_DCFG 0x000003e0 355#define ISC_DCFG_IMODE_PACKED8 0x0 356#define ISC_DCFG_IMODE_PACKED16 0x1 357#define ISC_DCFG_IMODE_PACKED32 0x2 358#define ISC_DCFG_IMODE_YC422SP 0x3 359#define ISC_DCFG_IMODE_YC422P 0x4 360#define ISC_DCFG_IMODE_YC420SP 0x5 361#define ISC_DCFG_IMODE_YC420P 0x6 362#define ISC_DCFG_IMODE_MASK GENMASK(2, 0) 363 364#define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4) 365#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) 366#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) 367#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) 368#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) 369#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) 370 371#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) 372#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) 373#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) 374#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) 375#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) 376#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) 377 378/* DMA Control Register */ 379#define ISC_DCTRL 0x000003e4 380 381#define ISC_DCTRL_DVIEW_PACKED (0x0 << 1) 382#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1) 383#define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1) 384#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1) 385 386#define ISC_DCTRL_IE_IS (0x0 << 4) 387 388/* DMA Descriptor Address Register */ 389#define ISC_DNDA 0x000003e8 390 391/* DMA Address 0 Register */ 392#define ISC_DAD0 0x000003ec 393 394/* DMA Address 1 Register */ 395#define ISC_DAD1 0x000003f4 396 397/* DMA Address 2 Register */ 398#define ISC_DAD2 0x000003fc 399 400/* Offset for version register specific to sama5d2 product */ 401#define ISC_SAMA5D2_VERSION_OFFSET 0 402#define ISC_SAMA7G5_VERSION_OFFSET 0x13c 403/* Version Register */ 404#define ISC_VERSION 0x0000040c 405 406/* Offset for version register specific to sama5d2 product */ 407#define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 408/* Offset for version register specific to sama7g5 product */ 409#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c 410/* Histogram Entry */ 411#define ISC_HIS_ENTRY 0x00000410 412 413#endif 414