1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef HRT_GDC_v2_defs_h_ 17#define HRT_GDC_v2_defs_h_ 18 19#define HRT_GDC_IS_V2 20 21#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ 22#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ 23 24#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ 25#define HRT_GDC_BLI_COEF_ONE BIT(HRT_GDC_BLI_FRAC_BITS) 26 27#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ 28#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS - 2)) /* We represent signed 10 bit coefficients. */ 29/* The supported range is [-256, .., +256] */ 30/* in 14-bit signed notation, */ 31/* We need all ten bits (MSB must be zero). */ 32/* -s is inserted to solve this issue, and */ 33/* therefore "1" is equal to +256. */ 34#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) 35 36#define HRT_GDC_LUT_BYTES (HRT_GDC_N * 4 * 2) /* 1024 addresses, 4 coefficients per address, */ 37/* 2 bytes per coefficient */ 38 39#define _HRT_GDC_REG_ALIGN 4 40 41// 31 30 29 25 24 0 42// |-----|---|--------|------------------------| 43// | CMD | C | Reg_ID | Value | 44 45// There are just two commands possible for the GDC block: 46// 1 - Configure reg 47// 0 - Data token 48 49// C - Reserved bit 50// Used in protocol to indicate whether it is C-run or other type of runs 51// In case of C-run, this bit has a value of 1, for all the other runs, it is 0. 52 53// Reg_ID - Address of the register to be configured 54 55// Value - Value to store to the addressed register, maximum of 24 bits 56 57// Configure reg command is not followed by any other token. 58// The address of the register and the data to be filled in is contained in the same token 59 60// When the first data token is received, it must be: 61// 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, 62// 2. P0'X (device configured in one of the tetragon modes) 63// After the first data token is received, pre-defined number of tokens with the following meaning follow: 64// 1. two tokens: SRC address ; DST address 65// 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address 66 67#define HRT_GDC_CONFIG_CMD 1 68#define HRT_GDC_DATA_CMD 0 69 70#define HRT_GDC_CMD_POS 31 71#define HRT_GDC_CMD_BITS 1 72#define HRT_GDC_CRUN_POS 30 73#define HRT_GDC_REG_ID_POS 25 74#define HRT_GDC_REG_ID_BITS 5 75#define HRT_GDC_DATA_POS 0 76#define HRT_GDC_DATA_BITS 25 77 78#define HRT_GDC_FRYIPXFRX_BITS 26 79#define HRT_GDC_P0X_BITS 23 80 81#define HRT_GDC_MAX_OXDIM (8192 - 64) 82#define HRT_GDC_MAX_OYDIM 4095 83#define HRT_GDC_MAX_IXDIM (8192 - 64) 84#define HRT_GDC_MAX_IYDIM 4095 85#define HRT_GDC_MAX_DS_FAC 16 86#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC * HRT_GDC_N - 1) 87#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX 88 89/* GDC lookup tables entries are 10 bits values, but they're 90 stored 2 by 2 as 32 bit values, yielding 16 bits per entry. 91 A GDC lookup table contains 64 * 4 elements */ 92 93#define HRT_GDC_PERF_1_1_pix 0 94#define HRT_GDC_PERF_2_1_pix 1 95#define HRT_GDC_PERF_1_2_pix 2 96#define HRT_GDC_PERF_2_2_pix 3 97 98#define HRT_GDC_NND_MODE 0 99#define HRT_GDC_BLI_MODE 1 100#define HRT_GDC_BCI_MODE 2 101#define HRT_GDC_LUT_MODE 3 102 103#define HRT_GDC_SCAN_STB 0 104#define HRT_GDC_SCAN_STR 1 105 106#define HRT_GDC_MODE_SCALING 0 107#define HRT_GDC_MODE_TETRAGON 1 108 109#define HRT_GDC_LUT_COEFF_OFFSET 16 110#define HRT_GDC_FRY_BIT_OFFSET 16 111// FRYIPXFRX is the only register where we store two values in one field, 112// to save one token in the scaling protocol. 113// Like this, we have three tokens in the scaling protocol, 114// Otherwise, we would have had four. 115// The register bit-map is: 116// 31 26 25 16 15 10 9 0 117// |------|----------|------|----------| 118// | XXXX | FRY | IPX | FRX | 119 120#define HRT_GDC_CE_FSM0_POS 0 121#define HRT_GDC_CE_FSM0_LEN 2 122#define HRT_GDC_CE_OPY_POS 2 123#define HRT_GDC_CE_OPY_LEN 14 124#define HRT_GDC_CE_OPX_POS 16 125#define HRT_GDC_CE_OPX_LEN 16 126// CHK_ENGINE register bit-map: 127// 31 16 15 2 1 0 128// |----------------|-----------|----| 129// | OPX | OPY |FSM0| 130// However, for the time being at least, 131// this implementation is meaningless in hss model, 132// So, we just return 0 133 134#define HRT_GDC_CHK_ENGINE_IDX 0 135#define HRT_GDC_WOIX_IDX 1 136#define HRT_GDC_WOIY_IDX 2 137#define HRT_GDC_BPP_IDX 3 138#define HRT_GDC_FRYIPXFRX_IDX 4 139#define HRT_GDC_OXDIM_IDX 5 140#define HRT_GDC_OYDIM_IDX 6 141#define HRT_GDC_SRC_ADDR_IDX 7 142#define HRT_GDC_SRC_END_ADDR_IDX 8 143#define HRT_GDC_SRC_WRAP_ADDR_IDX 9 144#define HRT_GDC_SRC_STRIDE_IDX 10 145#define HRT_GDC_DST_ADDR_IDX 11 146#define HRT_GDC_DST_STRIDE_IDX 12 147#define HRT_GDC_DX_IDX 13 148#define HRT_GDC_DY_IDX 14 149#define HRT_GDC_P0X_IDX 15 150#define HRT_GDC_P0Y_IDX 16 151#define HRT_GDC_P1X_IDX 17 152#define HRT_GDC_P1Y_IDX 18 153#define HRT_GDC_P2X_IDX 19 154#define HRT_GDC_P2Y_IDX 20 155#define HRT_GDC_P3X_IDX 21 156#define HRT_GDC_P3Y_IDX 22 157#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc 158#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT 159#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) 160#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon 161 162#define HRT_GDC_LUT_IDX 32 163 164#endif /* HRT_GDC_v2_defs_h_ */ 165