1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef _dma_v2_defs_h 17#define _dma_v2_defs_h 18 19#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels 20#define _DMA_V2_CONNECTIONS_ID Connections 21#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths 22#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth 23#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat 24#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass 25#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst 26#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept 27#define _DMA_V2_DEV_SRMD_ID DevSRMD 28#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters 29#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth 30#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth 31#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat 32#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass 33#define _DMA_V2_NO_PACK_ID has_no_pack 34 35#define _DMA_V2_REG_ALIGN 4 36#define _DMA_V2_REG_ADDR_BITS 2 37 38/* Command word */ 39#define _DMA_V2_CMD_IDX 0 40#define _DMA_V2_CMD_BITS 6 41#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) 42#define _DMA_V2_CHANNEL_BITS 5 43 44/* The command to set a parameter contains the PARAM field next */ 45#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) 46#define _DMA_V2_PARAM_BITS 4 47 48/* Commands to read, write or init specific blocks contain these 49 three values */ 50#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) 51#define _DMA_V2_SPEC_DEV_A_XB_BITS 8 52#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) 53#define _DMA_V2_SPEC_DEV_B_XB_BITS 8 54#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) 55#define _DMA_V2_SPEC_YB_BITS (32 - _DMA_V2_SPEC_DEV_B_XB_BITS - _DMA_V2_SPEC_DEV_A_XB_BITS - _DMA_V2_CMD_BITS - _DMA_V2_CHANNEL_BITS) 56 57/* */ 58#define _DMA_V2_CMD_CTRL_IDX 4 59#define _DMA_V2_CMD_CTRL_BITS 4 60 61/* Packing setup word */ 62#define _DMA_V2_CONNECTION_IDX 0 63#define _DMA_V2_CONNECTION_BITS 4 64#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) 65#define _DMA_V2_EXTENSION_BITS 1 66 67/* Elements packing word */ 68#define _DMA_V2_ELEMENTS_IDX 0 69#define _DMA_V2_ELEMENTS_BITS 8 70#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) 71#define _DMA_V2_LEFT_CROPPING_BITS 8 72 73#define _DMA_V2_WIDTH_IDX 0 74#define _DMA_V2_WIDTH_BITS 16 75 76#define _DMA_V2_HEIGHT_IDX 0 77#define _DMA_V2_HEIGHT_BITS 16 78 79#define _DMA_V2_STRIDE_IDX 0 80#define _DMA_V2_STRIDE_BITS 32 81 82/* Command IDs */ 83#define _DMA_V2_MOVE_B2A_COMMAND 0 84#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 85#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 86#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 87#define _DMA_V2_MOVE_A2B_COMMAND 4 88#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 89#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 90#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 91#define _DMA_V2_INIT_A_COMMAND 8 92#define _DMA_V2_INIT_A_BLOCK_COMMAND 9 93#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 94#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 95#define _DMA_V2_INIT_B_COMMAND 12 96#define _DMA_V2_INIT_B_BLOCK_COMMAND 13 97#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 98#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 99#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) 100#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) 101#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) 102#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) 103#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) 104#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) 105#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) 106#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) 107#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 108#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 109#define _DMA_V2_SET_CRUN_COMMAND 62 110 111/* Channel Parameter IDs */ 112#define _DMA_V2_PACKING_SETUP_PARAM 0 113#define _DMA_V2_STRIDE_A_PARAM 1 114#define _DMA_V2_ELEM_CROPPING_A_PARAM 2 115#define _DMA_V2_WIDTH_A_PARAM 3 116#define _DMA_V2_STRIDE_B_PARAM 4 117#define _DMA_V2_ELEM_CROPPING_B_PARAM 5 118#define _DMA_V2_WIDTH_B_PARAM 6 119#define _DMA_V2_HEIGHT_PARAM 7 120#define _DMA_V2_QUEUED_CMDS 8 121 122/* Parameter Constants */ 123#define _DMA_V2_ZERO_EXTEND 0 124#define _DMA_V2_SIGN_EXTEND 1 125 126/* SLAVE address map */ 127#define _DMA_V2_SEL_FSM_CMD 0 128#define _DMA_V2_SEL_CH_REG 1 129#define _DMA_V2_SEL_CONN_GROUP 2 130#define _DMA_V2_SEL_DEV_INTERF 3 131 132#define _DMA_V2_ADDR_SEL_COMP_IDX 12 133#define _DMA_V2_ADDR_SEL_COMP_BITS 4 134#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 135#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 136#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS + _DMA_V2_ADDR_SEL_CH_REG_IDX) 137#define _DMA_V2_ADDR_SEL_PARAM_BITS 4 138 139#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 140#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 141#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) 142#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 143 144#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 145#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 146#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX + _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) 147#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 148 149#define _DMA_V2_FSM_GROUP_CMD_IDX 0 150#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 151#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 152#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 153#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 154#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 155#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 156#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 157 158#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 159#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 160#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 161#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 162#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 163#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 164#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 165#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 166#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 167#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 168#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 169#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 170#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 171#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 172#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 173#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 174#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 175 176#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 177#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 178#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 179#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 180 181#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 182#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 183#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 184#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 185#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 186 187#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 188#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 189#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 190#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 191#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 192 193#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 194#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 195#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 196#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 197#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 198#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 199 200#endif /* _dma_v2_defs_h */ 201