1139749Simp// SPDX-License-Identifier: GPL-2.0-only 246495Swpaul/* 346495Swpaul * Marvell Armada-3700 SPI controller driver 446495Swpaul * 546495Swpaul * Copyright (C) 2016 Marvell Ltd. 646495Swpaul * 746495Swpaul * Author: Wilson Ding <dingwei@marvell.com> 846495Swpaul * Author: Romain Perier <romain.perier@free-electrons.com> 946495Swpaul */ 1046495Swpaul 1146495Swpaul#include <linux/clk.h> 1246495Swpaul#include <linux/completion.h> 1346495Swpaul#include <linux/delay.h> 1446495Swpaul#include <linux/err.h> 1546495Swpaul#include <linux/interrupt.h> 1646495Swpaul#include <linux/io.h> 1746495Swpaul#include <linux/kernel.h> 1846495Swpaul#include <linux/module.h> 1946495Swpaul#include <linux/of.h> 2046495Swpaul#include <linux/platform_device.h> 2146495Swpaul#include <linux/pinctrl/consumer.h> 2246495Swpaul#include <linux/spi/spi.h> 2346495Swpaul 2446495Swpaul#define DRIVER_NAME "armada_3700_spi" 2546495Swpaul 2646495Swpaul#define A3700_SPI_MAX_SPEED_HZ 100000000 2746495Swpaul#define A3700_SPI_MAX_PRESCALE 30 2846495Swpaul#define A3700_SPI_TIMEOUT 10 2946495Swpaul 3046495Swpaul/* SPI Register Offest */ 3146495Swpaul#define A3700_SPI_IF_CTRL_REG 0x00 3250477Speter#define A3700_SPI_IF_CFG_REG 0x04 3346495Swpaul#define A3700_SPI_DATA_OUT_REG 0x08 3446495Swpaul#define A3700_SPI_DATA_IN_REG 0x0C 3590580Sbrooks#define A3700_SPI_IF_INST_REG 0x10 3690580Sbrooks#define A3700_SPI_IF_ADDR_REG 0x14 3746495Swpaul#define A3700_SPI_IF_RMODE_REG 0x18 38109323Ssam#define A3700_SPI_IF_HDR_CNT_REG 0x1C 39109323Ssam#define A3700_SPI_IF_DIN_CNT_REG 0x20 40109323Ssam#define A3700_SPI_IF_TIME_REG 0x24 41109323Ssam#define A3700_SPI_INT_STAT_REG 0x28 42109323Ssam#define A3700_SPI_INT_MASK_REG 0x2C 43109323Ssam 4446495Swpaul/* A3700_SPI_IF_CTRL_REG */ 4590580Sbrooks#define A3700_SPI_EN BIT(16) 4682256Snsayer#define A3700_SPI_ADDR_NOT_CONFIG BIT(12) 4782256Snsayer#define A3700_SPI_WFIFO_OVERFLOW BIT(11) 4882256Snsayer#define A3700_SPI_WFIFO_UNDERFLOW BIT(10) 4974906Salfred#define A3700_SPI_RFIFO_OVERFLOW BIT(9) 5082256Snsayer#define A3700_SPI_RFIFO_UNDERFLOW BIT(8) 5182256Snsayer#define A3700_SPI_WFIFO_FULL BIT(7) 5274998Swpaul#define A3700_SPI_WFIFO_EMPTY BIT(6) 5374998Swpaul#define A3700_SPI_RFIFO_FULL BIT(5) 54181209Simp#define A3700_SPI_RFIFO_EMPTY BIT(4) 55181209Simp#define A3700_SPI_WFIFO_RDY BIT(3) 5674906Salfred#define A3700_SPI_RFIFO_RDY BIT(2) 5746495Swpaul#define A3700_SPI_XFER_RDY BIT(1) 58109323Ssam#define A3700_SPI_XFER_DONE BIT(0) 5946495Swpaul 6093567Simp/* A3700_SPI_IF_CFG_REG */ 6193567Simp#define A3700_SPI_WFIFO_THRS BIT(28) 6293567Simp#define A3700_SPI_RFIFO_THRS BIT(24) 6393567Simp#define A3700_SPI_AUTO_CS BIT(20) 6493567Simp#define A3700_SPI_DMA_RD_EN BIT(18) 6593567Simp#define A3700_SPI_FIFO_MODE BIT(17) 6653702Swpaul#define A3700_SPI_SRST BIT(16) 6746495Swpaul#define A3700_SPI_XFER_START BIT(15) 6846495Swpaul#define A3700_SPI_XFER_STOP BIT(14) 6946495Swpaul#define A3700_SPI_INST_PIN BIT(13) 7046495Swpaul#define A3700_SPI_ADDR_PIN BIT(12) 7193567Simp#define A3700_SPI_DATA_PIN1 BIT(11) 7246495Swpaul#define A3700_SPI_DATA_PIN0 BIT(10) 7346495Swpaul#define A3700_SPI_FIFO_FLUSH BIT(9) 7446495Swpaul#define A3700_SPI_RW_EN BIT(8) 7546495Swpaul#define A3700_SPI_CLK_POL BIT(7) 7646611Swpaul#define A3700_SPI_CLK_PHA BIT(6) 7746611Swpaul#define A3700_SPI_BYTE_LEN BIT(5) 7846611Swpaul#define A3700_SPI_CLK_PRESCALE BIT(0) 7946611Swpaul#define A3700_SPI_CLK_PRESCALE_MASK (0x1f) 8091691Simp#define A3700_SPI_CLK_EVEN_OFFS (0x10) 8146495Swpaul 8291691Simp#define A3700_SPI_WFIFO_THRS_BIT 28 8346495Swpaul#define A3700_SPI_RFIFO_THRS_BIT 24 8491691Simp#define A3700_SPI_FIFO_THRS_MASK 0x7 8591691Simp 8691691Simp#define A3700_SPI_DATA_PIN_MASK 0x3 8791691Simp 8891691Simp/* A3700_SPI_IF_HDR_CNT_REG */ 8991691Simp#define A3700_SPI_DUMMY_CNT_BIT 12 9091691Simp#define A3700_SPI_DUMMY_CNT_MASK 0x7 9191691Simp#define A3700_SPI_RMODE_CNT_BIT 8 9291691Simp#define A3700_SPI_RMODE_CNT_MASK 0x3 9391691Simp#define A3700_SPI_ADDR_CNT_BIT 4 9491691Simp#define A3700_SPI_ADDR_CNT_MASK 0x7 9591691Simp#define A3700_SPI_INSTR_CNT_BIT 0 9691691Simp#define A3700_SPI_INSTR_CNT_MASK 0x3 9791691Simp 9890580Sbrooks/* A3700_SPI_IF_TIME_REG */ 9990580Sbrooks#define A3700_SPI_CLK_CAPT_EDGE BIT(7) 10090580Sbrooks 10190580Sbrooksstruct a3700_spi { 10246495Swpaul struct spi_controller *host; 10346495Swpaul void __iomem *base; 10446495Swpaul struct clk *clk; 10590580Sbrooks unsigned int irq; 10690580Sbrooks unsigned int flags; 10790580Sbrooks bool xmit_data; 10890580Sbrooks const u8 *tx_buf; 10990580Sbrooks u8 *rx_buf; 11090580Sbrooks size_t buf_len; 11190580Sbrooks u8 byte_len; 11290580Sbrooks u32 wait_mask; 11390580Sbrooks struct completion done; 11446495Swpaul}; 11590580Sbrooks 11690580Sbrooksstatic u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) 11790580Sbrooks{ 11890580Sbrooks return readl(a3700_spi->base + offset); 11990580Sbrooks} 12090580Sbrooks 12190580Sbrooksstatic void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) 12290580Sbrooks{ 12390580Sbrooks writel(data, a3700_spi->base + offset); 12446495Swpaul} 12574906Salfred 12690580Sbrooksstatic void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) 12774906Salfred{ 12874906Salfred u32 val; 12990580Sbrooks 13074906Salfred val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 131101245Simp val &= ~A3700_SPI_AUTO_CS; 132101245Simp spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 133101245Simp} 134101245Simp 135101245Simpstatic void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) 136101245Simp{ 137101245Simp u32 val; 138101245Simp 139101245Simp val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 140101245Simp val |= (A3700_SPI_EN << cs); 141101245Simp spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 142101245Simp} 143101245Simp 14446495Swpaulstatic void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, 14546495Swpaul unsigned int cs) 14646495Swpaul{ 14746495Swpaul u32 val; 14846495Swpaul 14946495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 15046495Swpaul val &= ~(A3700_SPI_EN << cs); 15146495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 15246495Swpaul} 15346495Swpaul 15446495Swpaulstatic int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, 15546495Swpaul unsigned int pin_mode, bool receiving) 15646495Swpaul{ 15746495Swpaul u32 val; 15846495Swpaul 15946495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 160298955Spfg val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); 16146495Swpaul val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); 16246495Swpaul 16346495Swpaul switch (pin_mode) { 16446495Swpaul case SPI_NBITS_SINGLE: 16546495Swpaul break; 16646495Swpaul case SPI_NBITS_DUAL: 16746495Swpaul val |= A3700_SPI_DATA_PIN0; 16846495Swpaul break; 16946495Swpaul case SPI_NBITS_QUAD: 17046495Swpaul val |= A3700_SPI_DATA_PIN1; 17146495Swpaul /* RX during address reception uses 4-pin */ 17246495Swpaul if (receiving) 17346495Swpaul val |= A3700_SPI_ADDR_PIN; 17446495Swpaul break; 17546495Swpaul default: 17646495Swpaul dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode); 17746495Swpaul return -EINVAL; 17846495Swpaul } 17946495Swpaul 18046495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 18146495Swpaul 18246495Swpaul return 0; 18346495Swpaul} 18493567Simp 18546495Swpaulstatic void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable) 18646495Swpaul{ 18746495Swpaul u32 val; 18846495Swpaul 18993567Simp val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 19046495Swpaul if (enable) 19146495Swpaul val |= A3700_SPI_FIFO_MODE; 19246495Swpaul else 19346495Swpaul val &= ~A3700_SPI_FIFO_MODE; 19446495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 19546495Swpaul} 19646495Swpaul 19746495Swpaulstatic void a3700_spi_mode_set(struct a3700_spi *a3700_spi, 19846495Swpaul unsigned int mode_bits) 19946495Swpaul{ 20046495Swpaul u32 val; 20146495Swpaul 20246495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 20346495Swpaul 20446495Swpaul if (mode_bits & SPI_CPOL) 20546495Swpaul val |= A3700_SPI_CLK_POL; 20646495Swpaul else 20746495Swpaul val &= ~A3700_SPI_CLK_POL; 20846495Swpaul 20946495Swpaul if (mode_bits & SPI_CPHA) 21046495Swpaul val |= A3700_SPI_CLK_PHA; 21146495Swpaul else 21246495Swpaul val &= ~A3700_SPI_CLK_PHA; 213105076Simp 21446495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 215101245Simp} 216105076Simp 217105076Simpstatic void a3700_spi_clock_set(struct a3700_spi *a3700_spi, 218105076Simp unsigned int speed_hz) 21946495Swpaul{ 22046495Swpaul u32 val; 22146495Swpaul u32 prescale; 22246495Swpaul 223105076Simp prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); 224105076Simp 225105076Simp /* For prescaler values over 15, we can only set it by steps of 2. 226105076Simp * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to 227105076Simp * 30. We only use this range from 16 to 30. 228105076Simp */ 229105076Simp if (prescale > 15) 230105076Simp prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2); 23146495Swpaul 23246495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 23346495Swpaul val = val & ~A3700_SPI_CLK_PRESCALE_MASK; 23446495Swpaul 23546495Swpaul val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); 23646495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 23746495Swpaul 23846495Swpaul if (prescale <= 2) { 23946495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); 24046495Swpaul val |= A3700_SPI_CLK_CAPT_EDGE; 24146495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); 24246495Swpaul } 24346495Swpaul} 24446495Swpaul 24546495Swpaulstatic void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) 24646495Swpaul{ 24746495Swpaul u32 val; 24846495Swpaul 24946495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 25046495Swpaul if (len == 4) 25146495Swpaul val |= A3700_SPI_BYTE_LEN; 25246495Swpaul else 25346495Swpaul val &= ~A3700_SPI_BYTE_LEN; 25446495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 25546495Swpaul 25646495Swpaul a3700_spi->byte_len = len; 25746495Swpaul} 25846495Swpaul 25946495Swpaulstatic int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) 26046495Swpaul{ 26146495Swpaul int timeout = A3700_SPI_TIMEOUT; 26246495Swpaul u32 val; 26346495Swpaul 26446495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 26546495Swpaul val |= A3700_SPI_FIFO_FLUSH; 26646495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 26746495Swpaul 26846495Swpaul while (--timeout) { 26946495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 27046495Swpaul if (!(val & A3700_SPI_FIFO_FLUSH)) 27146495Swpaul return 0; 27246495Swpaul udelay(1); 27346495Swpaul } 27446495Swpaul 27546495Swpaul return -ETIMEDOUT; 27646495Swpaul} 27746495Swpaul 27846495Swpaulstatic void a3700_spi_init(struct a3700_spi *a3700_spi) 27946495Swpaul{ 28046495Swpaul struct spi_controller *host = a3700_spi->host; 28146495Swpaul u32 val; 28246495Swpaul int i; 28346495Swpaul 28446495Swpaul /* Reset SPI unit */ 28546495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 28646495Swpaul val |= A3700_SPI_SRST; 28746495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 28846495Swpaul 28946495Swpaul udelay(A3700_SPI_TIMEOUT); 29046495Swpaul 29146495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 29246495Swpaul val &= ~A3700_SPI_SRST; 29346495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 29446495Swpaul 29546495Swpaul /* Disable AUTO_CS and deactivate all chip-selects */ 29646495Swpaul a3700_spi_auto_cs_unset(a3700_spi); 29746495Swpaul for (i = 0; i < host->num_chipselect; i++) 298298955Spfg a3700_spi_deactivate_cs(a3700_spi, i); 29946495Swpaul 30046495Swpaul /* Enable FIFO mode */ 30146495Swpaul a3700_spi_fifo_mode_set(a3700_spi, true); 30246495Swpaul 30346495Swpaul /* Set SPI mode */ 30446495Swpaul a3700_spi_mode_set(a3700_spi, host->mode_bits); 30593567Simp 30646495Swpaul /* Reset counters */ 30746495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 30846495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); 30946495Swpaul 31046495Swpaul /* Mask the interrupts and clear cause bits */ 31146495Swpaul spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 31246495Swpaul spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); 31346495Swpaul} 31446495Swpaul 31546495Swpaulstatic irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) 31646495Swpaul{ 31746495Swpaul struct spi_controller *host = dev_id; 31846495Swpaul struct a3700_spi *a3700_spi; 319101245Simp u32 cause; 320101245Simp 321101245Simp a3700_spi = spi_controller_get_devdata(host); 322101245Simp 323101245Simp /* Get interrupt causes */ 324101245Simp cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); 325101245Simp 326101245Simp if (!cause || !(a3700_spi->wait_mask & cause)) 327101245Simp return IRQ_NONE; 328101245Simp 329101245Simp /* mask and acknowledge the SPI interrupts */ 330101245Simp spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 331101245Simp spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); 332101245Simp 333101245Simp /* Wake up the transfer */ 334181209Simp complete(&a3700_spi->done); 33574906Salfred 33674906Salfred return IRQ_HANDLED; 33746495Swpaul} 33846495Swpaul 33946495Swpaulstatic bool a3700_spi_wait_completion(struct spi_device *spi) 34046495Swpaul{ 34146495Swpaul struct a3700_spi *a3700_spi; 34246495Swpaul unsigned int timeout; 343109323Ssam unsigned int ctrl_reg; 34446495Swpaul unsigned long timeout_jiffies; 34546495Swpaul 346109323Ssam a3700_spi = spi_controller_get_devdata(spi->controller); 34746495Swpaul 34846495Swpaul /* SPI interrupt is edge-triggered, which means an interrupt will 34946495Swpaul * be generated only when detecting a specific status bit changed 35046495Swpaul * from '0' to '1'. So when we start waiting for a interrupt, we 35146495Swpaul * need to check status bit in control reg first, if it is already 1, 352109323Ssam * then we do not need to wait for interrupt 35346495Swpaul */ 35446495Swpaul ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 35546495Swpaul if (a3700_spi->wait_mask & ctrl_reg) 35646495Swpaul return true; 35746495Swpaul 35846495Swpaul reinit_completion(&a3700_spi->done); 35946495Swpaul 36046495Swpaul spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 361109323Ssam a3700_spi->wait_mask); 36246495Swpaul 36346495Swpaul timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); 36446495Swpaul timeout = wait_for_completion_timeout(&a3700_spi->done, 36546495Swpaul timeout_jiffies); 36646495Swpaul 36793567Simp a3700_spi->wait_mask = 0; 36887383Simp 369109323Ssam if (timeout) 37087383Simp return true; 37187383Simp 37287383Simp /* there might be the case that right after we checked the 37393825Simp * status bits in this routine and before start to wait for 37493825Simp * interrupt by wait_for_completion_timeout, the interrupt 37593825Simp * happens, to avoid missing it we need to double check 37693825Simp * status bits in control reg, if it is already 1, then 37794158Simp * consider that we have the interrupt successfully and 37893825Simp * return true. 37993825Simp */ 38093825Simp ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 38193825Simp if (a3700_spi->wait_mask & ctrl_reg) 38293825Simp return true; 38393825Simp 38493825Simp spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 38593825Simp 38693825Simp /* Timeout was reached */ 38793825Simp return false; 38893825Simp} 38993825Simp 39093825Simpstatic bool a3700_spi_transfer_wait(struct spi_device *spi, 39193825Simp unsigned int bit_mask) 39293825Simp{ 39393825Simp struct a3700_spi *a3700_spi; 39493825Simp 39593825Simp a3700_spi = spi_controller_get_devdata(spi->controller); 39693825Simp a3700_spi->wait_mask = bit_mask; 39793825Simp 39893825Simp return a3700_spi_wait_completion(spi); 39993825Simp} 40093825Simp 40193825Simpstatic void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, 40293825Simp unsigned int bytes) 40393825Simp{ 40493825Simp u32 val; 40593825Simp 40693825Simp val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 40793825Simp val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); 40893825Simp val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; 40993825Simp val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); 41093825Simp val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; 41193825Simp spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 412101355Simp} 413101355Simp 41493825Simpstatic void a3700_spi_transfer_setup(struct spi_device *spi, 41593825Simp struct spi_transfer *xfer) 41693825Simp{ 41793825Simp struct a3700_spi *a3700_spi; 418101355Simp 419101355Simp a3700_spi = spi_controller_get_devdata(spi->controller); 42093825Simp 42193825Simp a3700_spi_clock_set(a3700_spi, xfer->speed_hz); 42293825Simp 42393825Simp /* Use 4 bytes long transfers. Each transfer method has its way to deal 424101355Simp * with the remaining bytes for non 4-bytes aligned transfers. 425101360Simp */ 42693825Simp a3700_spi_bytelen_set(a3700_spi, 4); 42793825Simp 42893825Simp /* Initialize the working buffers */ 42993825Simp a3700_spi->tx_buf = xfer->tx_buf; 430101355Simp a3700_spi->rx_buf = xfer->rx_buf; 431101355Simp a3700_spi->buf_len = xfer->len; 43293825Simp} 43393825Simp 434181209Simpstatic void a3700_spi_set_cs(struct spi_device *spi, bool enable) 435181209Simp{ 436181209Simp struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller); 437181209Simp 43893825Simp if (!enable) 43993825Simp a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0)); 440101355Simp else 441101355Simp a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0)); 44293825Simp} 44393825Simp 44487383Simpstatic void a3700_spi_header_set(struct a3700_spi *a3700_spi) 44546495Swpaul{ 44646495Swpaul unsigned int addr_cnt; 44746495Swpaul u32 val = 0; 44846495Swpaul 44946495Swpaul /* Clear the header registers */ 450101357Simp spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); 451101357Simp spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); 45246495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); 45346495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 45446495Swpaul 45546495Swpaul /* Set header counters */ 45646495Swpaul if (a3700_spi->tx_buf) { 457109323Ssam /* 45846495Swpaul * when tx data is not 4 bytes aligned, there will be unexpected 45946495Swpaul * bytes out of SPI output register, since it always shifts out 46046495Swpaul * as whole 4 bytes. This might cause incorrect transaction with 46146495Swpaul * some devices. To avoid that, use SPI header count feature to 46246495Swpaul * transfer up to 3 bytes of data first, and then make the rest 46346495Swpaul * of data 4-byte aligned. 464109323Ssam */ 46546495Swpaul addr_cnt = a3700_spi->buf_len % 4; 46646495Swpaul if (addr_cnt) { 46746495Swpaul val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) 46846495Swpaul << A3700_SPI_ADDR_CNT_BIT; 46946495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); 47046495Swpaul 47193564Simp /* Update the buffer length to be transferred */ 47246495Swpaul a3700_spi->buf_len -= addr_cnt; 473109323Ssam 47446495Swpaul /* transfer 1~3 bytes through address count */ 47546495Swpaul val = 0; 47646495Swpaul while (addr_cnt--) { 47746495Swpaul val = (val << 8) | a3700_spi->tx_buf[0]; 47846495Swpaul a3700_spi->tx_buf++; 47946495Swpaul } 48046495Swpaul spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); 48146495Swpaul } 48246495Swpaul } 48346495Swpaul} 48446495Swpaul 485109323Ssamstatic int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) 486109323Ssam{ 487109323Ssam u32 val; 488109323Ssam 48946495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 49046495Swpaul return (val & A3700_SPI_WFIFO_FULL); 49146495Swpaul} 49293564Simp 49393564Simpstatic int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) 49446495Swpaul{ 49546495Swpaul u32 val; 49693564Simp 49793564Simp while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { 49893564Simp val = *(u32 *)a3700_spi->tx_buf; 49946495Swpaul spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val)); 500109323Ssam a3700_spi->buf_len -= 4; 50146495Swpaul a3700_spi->tx_buf += 4; 50246495Swpaul } 50346495Swpaul 504160991Ssam return 0; 505109323Ssam} 50646495Swpaul 50746495Swpaulstatic int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) 50893564Simp{ 50946495Swpaul u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 510109323Ssam 511109323Ssam return (val & A3700_SPI_RFIFO_EMPTY); 51246495Swpaul} 51346495Swpaul 51446495Swpaulstatic int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) 51593756Simp{ 51646495Swpaul u32 val; 517109323Ssam 51846495Swpaul while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { 519109323Ssam val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 52046495Swpaul if (a3700_spi->buf_len >= 4) { 52146495Swpaul val = le32_to_cpu(val); 52246495Swpaul memcpy(a3700_spi->rx_buf, &val, 4); 52393756Simp 52446495Swpaul a3700_spi->buf_len -= 4; 525109323Ssam a3700_spi->rx_buf += 4; 526109323Ssam } else { 527109323Ssam /* 52846495Swpaul * When remain bytes is not larger than 4, we should 52946495Swpaul * avoid memory overwriting and just write the left rx 53046495Swpaul * buffer bytes. 53146495Swpaul */ 53293756Simp while (a3700_spi->buf_len) { 53346495Swpaul *a3700_spi->rx_buf = val & 0xff; 534109323Ssam val >>= 8; 53546495Swpaul 53646495Swpaul a3700_spi->buf_len--; 53746495Swpaul a3700_spi->rx_buf++; 53846495Swpaul } 539109323Ssam } 540109323Ssam } 541109323Ssam 542109323Ssam return 0; 543109323Ssam} 544109323Ssam 545109323Ssamstatic void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) 546109323Ssam{ 54794405Simp int timeout = A3700_SPI_TIMEOUT; 54894405Simp u32 val; 54994405Simp 55094405Simp val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 55194405Simp val |= A3700_SPI_XFER_STOP; 55294405Simp spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 55398720Simp 55494405Simp while (--timeout) { 55594405Simp val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 55646495Swpaul if (!(val & A3700_SPI_XFER_START)) 55746495Swpaul break; 55846495Swpaul udelay(1); 55946495Swpaul } 56046495Swpaul 561109323Ssam a3700_spi_fifo_flush(a3700_spi); 56246495Swpaul 563109323Ssam val &= ~A3700_SPI_XFER_STOP; 564109323Ssam spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 565109323Ssam} 566109323Ssam 567109323Ssamstatic int a3700_spi_prepare_message(struct spi_controller *host, 568109323Ssam struct spi_message *message) 56946495Swpaul{ 570109323Ssam struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); 571109323Ssam struct spi_device *spi = message->spi; 57246495Swpaul int ret; 573109323Ssam 574109323Ssam ret = clk_enable(a3700_spi->clk); 575109323Ssam if (ret) { 576109323Ssam dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); 577109323Ssam return ret; 578109323Ssam } 579109323Ssam 580109323Ssam /* Flush the FIFOs */ 581109323Ssam ret = a3700_spi_fifo_flush(a3700_spi); 582109323Ssam if (ret) 583109323Ssam return ret; 584109323Ssam 585109323Ssam a3700_spi_mode_set(a3700_spi, spi->mode); 58646495Swpaul 587109323Ssam return 0; 58846495Swpaul} 589109323Ssam 590109323Ssamstatic int a3700_spi_transfer_one_fifo(struct spi_controller *host, 591109323Ssam struct spi_device *spi, 592109323Ssam struct spi_transfer *xfer) 593109323Ssam{ 594109323Ssam struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); 595109323Ssam int ret = 0, timeout = A3700_SPI_TIMEOUT; 596109323Ssam unsigned int nbits = 0, byte_len; 597109323Ssam u32 val; 598109323Ssam 599109323Ssam /* Make sure we use FIFO mode */ 600109323Ssam a3700_spi_fifo_mode_set(a3700_spi, true); 601109323Ssam 602109323Ssam /* Configure FIFO thresholds */ 603109323Ssam byte_len = xfer->bits_per_word >> 3; 604109323Ssam a3700_spi_fifo_thres_set(a3700_spi, byte_len); 605109323Ssam 606109323Ssam if (xfer->tx_buf) 607109323Ssam nbits = xfer->tx_nbits; 608109323Ssam else if (xfer->rx_buf) 609109323Ssam nbits = xfer->rx_nbits; 610109323Ssam 611109323Ssam a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); 612109323Ssam 613109323Ssam /* Flush the FIFOs */ 614109323Ssam a3700_spi_fifo_flush(a3700_spi); 615109323Ssam 616109323Ssam /* Transfer first bytes of data when buffer is not 4-byte aligned */ 617109323Ssam a3700_spi_header_set(a3700_spi); 618109323Ssam 619109323Ssam if (xfer->rx_buf) { 620109323Ssam /* Clear WFIFO, since it's last 2 bytes are shifted out during 621109323Ssam * a read operation 622109323Ssam */ 623109323Ssam spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0); 624109323Ssam 625109323Ssam /* Set read data length */ 626109323Ssam spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 627109323Ssam a3700_spi->buf_len); 628109323Ssam /* Start READ transfer */ 629109323Ssam val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 630109323Ssam val &= ~A3700_SPI_RW_EN; 631109323Ssam val |= A3700_SPI_XFER_START; 632109323Ssam spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 633109323Ssam } else if (xfer->tx_buf) { 634109323Ssam /* Start Write transfer */ 63546495Swpaul val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 63646495Swpaul val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); 637109323Ssam spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 638109323Ssam 639109323Ssam /* 640109323Ssam * If there are data to be written to the SPI device, xmit_data 641109323Ssam * flag is set true; otherwise the instruction in SPI_INSTR does 642109323Ssam * not require data to be written to the SPI device, then 643109323Ssam * xmit_data flag is set false. 644109323Ssam */ 645109323Ssam a3700_spi->xmit_data = (a3700_spi->buf_len != 0); 646109323Ssam } 647109323Ssam 648109323Ssam while (a3700_spi->buf_len) { 649109323Ssam if (a3700_spi->tx_buf) { 65046495Swpaul /* Wait wfifo ready */ 651109323Ssam if (!a3700_spi_transfer_wait(spi, 652109323Ssam A3700_SPI_WFIFO_RDY)) { 653109323Ssam dev_err(&spi->dev, 654109323Ssam "wait wfifo ready timed out\n"); 655109323Ssam ret = -ETIMEDOUT; 65646495Swpaul goto error; 657109323Ssam } 65846495Swpaul /* Fill up the wfifo */ 65946495Swpaul ret = a3700_spi_fifo_write(a3700_spi); 66046495Swpaul if (ret) 66146495Swpaul goto error; 662109323Ssam } else if (a3700_spi->rx_buf) { 66346495Swpaul /* Wait rfifo ready */ 664109323Ssam if (!a3700_spi_transfer_wait(spi, 665109323Ssam A3700_SPI_RFIFO_RDY)) { 666109323Ssam dev_err(&spi->dev, 667109323Ssam "wait rfifo ready timed out\n"); 66846495Swpaul ret = -ETIMEDOUT; 66946495Swpaul goto error; 67046495Swpaul } 67146495Swpaul /* Drain out the rfifo */ 67246495Swpaul ret = a3700_spi_fifo_read(a3700_spi); 67346495Swpaul if (ret) 674109323Ssam goto error; 675109323Ssam } 676109323Ssam } 677109323Ssam 678109323Ssam /* 679109323Ssam * Stop a write transfer in fifo mode: 680109323Ssam * - wait all the bytes in wfifo to be shifted out 681109323Ssam * - set XFER_STOP bit 68246495Swpaul * - wait XFER_START bit clear 68346495Swpaul * - clear XFER_STOP bit 684105076Simp * Stop a read transfer in fifo mode: 685105076Simp * - the hardware is to reset the XFER_START bit 686105076Simp * after the number of bytes indicated in DIN_CNT 687105076Simp * register 688119784Ssam * - just wait XFER_START bit clear 689119784Ssam */ 690119784Ssam if (a3700_spi->tx_buf) { 691119784Ssam if (a3700_spi->xmit_data) { 692119784Ssam /* 693123927Ssam * If there are data written to the SPI device, wait 694192468Ssam * until SPI_WFIFO_EMPTY is 1 to wait for all data to 695192468Ssam * transfer out of write FIFO. 696119784Ssam */ 697119784Ssam if (!a3700_spi_transfer_wait(spi, 698119784Ssam A3700_SPI_WFIFO_EMPTY)) { 699123927Ssam dev_err(&spi->dev, "wait wfifo empty timed out\n"); 700119784Ssam return -ETIMEDOUT; 701119784Ssam } 702119784Ssam } 703192468Ssam 704119784Ssam if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { 705119784Ssam dev_err(&spi->dev, "wait xfer ready timed out\n"); 706119784Ssam return -ETIMEDOUT; 707119784Ssam } 708119784Ssam 709119784Ssam val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 710345636Savos val |= A3700_SPI_XFER_STOP; 711119784Ssam spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 712119784Ssam } 713123927Ssam 714123927Ssam while (--timeout) { 715123927Ssam val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 716119784Ssam if (!(val & A3700_SPI_XFER_START)) 717119784Ssam break; 718119784Ssam udelay(1); 719123927Ssam } 720123927Ssam 721119784Ssam if (timeout == 0) { 722119784Ssam dev_err(&spi->dev, "wait transfer start clear timed out\n"); 723345636Savos ret = -ETIMEDOUT; 724119784Ssam goto error; 725 } 726 727 val &= ~A3700_SPI_XFER_STOP; 728 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 729 goto out; 730 731error: 732 a3700_spi_transfer_abort_fifo(a3700_spi); 733out: 734 spi_finalize_current_transfer(host); 735 736 return ret; 737} 738 739static int a3700_spi_transfer_one_full_duplex(struct spi_controller *host, 740 struct spi_device *spi, 741 struct spi_transfer *xfer) 742{ 743 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); 744 u32 val; 745 746 /* Disable FIFO mode */ 747 a3700_spi_fifo_mode_set(a3700_spi, false); 748 749 while (a3700_spi->buf_len) { 750 751 /* When we have less than 4 bytes to transfer, switch to 1 byte 752 * mode. This is reset after each transfer 753 */ 754 if (a3700_spi->buf_len < 4) 755 a3700_spi_bytelen_set(a3700_spi, 1); 756 757 if (a3700_spi->byte_len == 1) 758 val = *a3700_spi->tx_buf; 759 else 760 val = *(u32 *)a3700_spi->tx_buf; 761 762 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); 763 764 /* Wait for all the data to be shifted in / out */ 765 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) & 766 A3700_SPI_XFER_DONE)) 767 cpu_relax(); 768 769 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 770 771 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); 772 773 a3700_spi->buf_len -= a3700_spi->byte_len; 774 a3700_spi->tx_buf += a3700_spi->byte_len; 775 a3700_spi->rx_buf += a3700_spi->byte_len; 776 777 } 778 779 spi_finalize_current_transfer(host); 780 781 return 0; 782} 783 784static int a3700_spi_transfer_one(struct spi_controller *host, 785 struct spi_device *spi, 786 struct spi_transfer *xfer) 787{ 788 a3700_spi_transfer_setup(spi, xfer); 789 790 if (xfer->tx_buf && xfer->rx_buf) 791 return a3700_spi_transfer_one_full_duplex(host, spi, xfer); 792 793 return a3700_spi_transfer_one_fifo(host, spi, xfer); 794} 795 796static int a3700_spi_unprepare_message(struct spi_controller *host, 797 struct spi_message *message) 798{ 799 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); 800 801 clk_disable(a3700_spi->clk); 802 803 return 0; 804} 805 806static const struct of_device_id a3700_spi_dt_ids[] = { 807 { .compatible = "marvell,armada-3700-spi", .data = NULL }, 808 {}, 809}; 810 811MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); 812 813static int a3700_spi_probe(struct platform_device *pdev) 814{ 815 struct device *dev = &pdev->dev; 816 struct device_node *of_node = dev->of_node; 817 struct spi_controller *host; 818 struct a3700_spi *spi; 819 u32 num_cs = 0; 820 int irq, ret = 0; 821 822 host = spi_alloc_host(dev, sizeof(*spi)); 823 if (!host) { 824 dev_err(dev, "host allocation failed\n"); 825 ret = -ENOMEM; 826 goto out; 827 } 828 829 if (of_property_read_u32(of_node, "num-cs", &num_cs)) { 830 dev_err(dev, "could not find num-cs\n"); 831 ret = -ENXIO; 832 goto error; 833 } 834 835 host->bus_num = pdev->id; 836 host->dev.of_node = of_node; 837 host->mode_bits = SPI_MODE_3; 838 host->num_chipselect = num_cs; 839 host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); 840 host->prepare_message = a3700_spi_prepare_message; 841 host->transfer_one = a3700_spi_transfer_one; 842 host->unprepare_message = a3700_spi_unprepare_message; 843 host->set_cs = a3700_spi_set_cs; 844 host->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | 845 SPI_RX_QUAD | SPI_TX_QUAD); 846 847 platform_set_drvdata(pdev, host); 848 849 spi = spi_controller_get_devdata(host); 850 851 spi->host = host; 852 853 spi->base = devm_platform_ioremap_resource(pdev, 0); 854 if (IS_ERR(spi->base)) { 855 ret = PTR_ERR(spi->base); 856 goto error; 857 } 858 859 irq = platform_get_irq(pdev, 0); 860 if (irq < 0) { 861 ret = -ENXIO; 862 goto error; 863 } 864 spi->irq = irq; 865 866 init_completion(&spi->done); 867 868 spi->clk = devm_clk_get_prepared(dev, NULL); 869 if (IS_ERR(spi->clk)) { 870 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); 871 goto error; 872 } 873 874 host->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ, 875 clk_get_rate(spi->clk)); 876 host->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk), 877 A3700_SPI_MAX_PRESCALE); 878 879 a3700_spi_init(spi); 880 881 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, 882 dev_name(dev), host); 883 if (ret) { 884 dev_err(dev, "could not request IRQ: %d\n", ret); 885 goto error; 886 } 887 888 ret = devm_spi_register_controller(dev, host); 889 if (ret) { 890 dev_err(dev, "Failed to register host\n"); 891 goto error; 892 } 893 894 return 0; 895 896error: 897 spi_controller_put(host); 898out: 899 return ret; 900} 901 902static struct platform_driver a3700_spi_driver = { 903 .driver = { 904 .name = DRIVER_NAME, 905 .of_match_table = of_match_ptr(a3700_spi_dt_ids), 906 }, 907 .probe = a3700_spi_probe, 908}; 909 910module_platform_driver(a3700_spi_driver); 911 912MODULE_DESCRIPTION("Armada-3700 SPI driver"); 913MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); 914MODULE_LICENSE("GPL"); 915MODULE_ALIAS("platform:" DRIVER_NAME); 916