1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10#ifndef MPI3MR_H_INCLUDED 11#define MPI3MR_H_INCLUDED 12 13#include <linux/blkdev.h> 14#include <linux/blk-mq.h> 15#include <linux/blk-mq-pci.h> 16#include <linux/delay.h> 17#include <linux/dmapool.h> 18#include <linux/errno.h> 19#include <linux/init.h> 20#include <linux/io.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/miscdevice.h> 24#include <linux/module.h> 25#include <linux/pci.h> 26#include <linux/poll.h> 27#include <linux/sched.h> 28#include <linux/slab.h> 29#include <linux/types.h> 30#include <linux/uaccess.h> 31#include <linux/utsname.h> 32#include <linux/workqueue.h> 33#include <asm/unaligned.h> 34#include <scsi/scsi.h> 35#include <scsi/scsi_cmnd.h> 36#include <scsi/scsi_dbg.h> 37#include <scsi/scsi_device.h> 38#include <scsi/scsi_host.h> 39#include <scsi/scsi_tcq.h> 40#include <uapi/scsi/scsi_bsg_mpi3mr.h> 41#include <scsi/scsi_transport_sas.h> 42 43#include "mpi/mpi30_transport.h" 44#include "mpi/mpi30_cnfg.h" 45#include "mpi/mpi30_image.h" 46#include "mpi/mpi30_init.h" 47#include "mpi/mpi30_ioc.h" 48#include "mpi/mpi30_sas.h" 49#include "mpi/mpi30_pci.h" 50#include "mpi3mr_debug.h" 51 52/* Global list and lock for storing multiple adapters managed by the driver */ 53extern spinlock_t mrioc_list_lock; 54extern struct list_head mrioc_list; 55extern int prot_mask; 56extern atomic64_t event_counter; 57 58#define MPI3MR_DRIVER_VERSION "8.5.1.0.0" 59#define MPI3MR_DRIVER_RELDATE "5-December-2023" 60 61#define MPI3MR_DRIVER_NAME "mpi3mr" 62#define MPI3MR_DRIVER_LICENSE "GPL" 63#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66#define MPI3MR_NAME_LENGTH 32 67#define IOCNAME "%s: " 68 69#define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 70 71/* Definitions for internal SGL and Chain SGL buffers */ 72#define MPI3MR_PAGE_SIZE_4K 4096 73#define MPI3MR_DEFAULT_SGL_ENTRIES 256 74#define MPI3MR_MAX_SGL_ENTRIES 2048 75 76/* Definitions for MAX values for shost */ 77#define MPI3MR_MAX_CMDS_LUN 128 78#define MPI3MR_MAX_CDB_LENGTH 32 79 80/* Admin queue management definitions */ 81#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 82#define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 83#define MPI3MR_ADMIN_REQ_FRAME_SZ 128 84#define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 85 86/* Operational queue management definitions */ 87#define MPI3MR_OP_REQ_Q_QD 512 88#define MPI3MR_OP_REP_Q_QD 1024 89#define MPI3MR_OP_REP_Q_QD4K 4096 90#define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 91#define MPI3MR_OP_REP_Q_SEG_SIZE 4096 92#define MPI3MR_MAX_SEG_LIST_SIZE 4096 93 94/* Reserved Host Tag definitions */ 95#define MPI3MR_HOSTTAG_INVALID 0xFFFF 96#define MPI3MR_HOSTTAG_INITCMDS 1 97#define MPI3MR_HOSTTAG_BSG_CMDS 2 98#define MPI3MR_HOSTTAG_PEL_ABORT 3 99#define MPI3MR_HOSTTAG_PEL_WAIT 4 100#define MPI3MR_HOSTTAG_BLK_TMS 5 101#define MPI3MR_HOSTTAG_CFG_CMDS 6 102#define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 103 104#define MPI3MR_NUM_DEVRMCMD 16 105#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 106#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 107 MPI3MR_NUM_DEVRMCMD - 1) 108 109#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 110#define MPI3MR_NUM_EVTACKCMD 4 111#define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 112#define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 113 MPI3MR_NUM_EVTACKCMD - 1) 114 115/* Reduced resource count definition for crash kernel */ 116#define MPI3MR_HOST_IOS_KDUMP 128 117 118/* command/controller interaction timeout definitions in seconds */ 119#define MPI3MR_INTADMCMD_TIMEOUT 60 120#define MPI3MR_PORTENABLE_TIMEOUT 300 121#define MPI3MR_PORTENABLE_POLL_INTERVAL 5 122#define MPI3MR_ABORTTM_TIMEOUT 60 123#define MPI3MR_RESETTM_TIMEOUT 60 124#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 125#define MPI3MR_TSUPDATE_INTERVAL 900 126#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 127#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 128#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 129#define MPI3MR_RESET_ACK_TIMEOUT 30 130#define MPI3MR_MUR_TIMEOUT 120 131 132#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 133 134#define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 135 136#define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 137 138#define MPI3MR_SCMD_TIMEOUT (60 * HZ) 139#define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 140 141/* Internal admin command state definitions*/ 142#define MPI3MR_CMD_NOTUSED 0x8000 143#define MPI3MR_CMD_COMPLETE 0x0001 144#define MPI3MR_CMD_PENDING 0x0002 145#define MPI3MR_CMD_REPLY_VALID 0x0004 146#define MPI3MR_CMD_RESET 0x0008 147 148/* Definitions for Event replies and sense buffer allocated per controller */ 149#define MPI3MR_NUM_EVT_REPLIES 64 150#define MPI3MR_SENSE_BUF_SZ 256 151#define MPI3MR_SENSEBUF_FACTOR 3 152#define MPI3MR_CHAINBUF_FACTOR 3 153#define MPI3MR_CHAINBUFDIX_FACTOR 2 154 155/* Invalid target device handle */ 156#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 157 158/* Controller Reset related definitions */ 159#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 160#define MPI3MR_MAX_RESET_RETRY_COUNT 3 161 162/* ResponseCode definitions */ 163#define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 164#define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 165 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 166 167#define MPI3MR_DEFAULT_MDTS (128 * 1024) 168#define MPI3MR_DEFAULT_PGSZEXP (12) 169 170/* Command retry count definitions */ 171#define MPI3MR_DEV_RMHS_RETRY_COUNT 3 172#define MPI3MR_PEL_RETRY_COUNT 3 173 174/* Default target device queue depth */ 175#define MPI3MR_DEFAULT_SDEV_QD 32 176 177/* Definitions for Threaded IRQ poll*/ 178#define MPI3MR_IRQ_POLL_SLEEP 2 179#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 180 181/* Definitions for the controller security status*/ 182#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 183#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 184 185#define MPI3MR_INVALID_DEVICE 0x00 186#define MPI3MR_CONFIG_SECURE_DEVICE 0x04 187#define MPI3MR_HARD_SECURE_DEVICE 0x08 188#define MPI3MR_TAMPERED_DEVICE 0x0C 189 190/* SGE Flag definition */ 191#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 192 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 193 MPI3_SGE_FLAGS_END_OF_LIST) 194 195/* MSI Index from Reply Queue Index */ 196#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 197 198/* 199 * Maximum data transfer size definitions for management 200 * application commands 201 */ 202#define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 203#define MPI3MR_MAX_APP_XFER_SEGMENTS 512 204/* 205 * 2048 sectors are for data buffers and additional 512 sectors for 206 * other buffers 207 */ 208#define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 209 210#define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256 211#define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048 212 213/** 214 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 215 * Encapsulated commands. 216 * 217 * @base_addr: Physical address 218 * @length: SGE length 219 * @rsvd: Reserved 220 * @rsvd1: Reserved 221 * @sub_type: sgl sub type 222 * @type: sgl type 223 */ 224struct mpi3mr_nvme_pt_sge { 225 __le64 base_addr; 226 __le32 length; 227 u16 rsvd; 228 u8 rsvd1; 229 u8 sub_type:4; 230 u8 type:4; 231}; 232 233/** 234 * struct mpi3mr_buf_map - local structure to 235 * track kernel and user buffers associated with an BSG 236 * structure. 237 * 238 * @bsg_buf: BSG buffer virtual address 239 * @bsg_buf_len: BSG buffer length 240 * @kern_buf: Kernel buffer virtual address 241 * @kern_buf_len: Kernel buffer length 242 * @kern_buf_dma: Kernel buffer DMA address 243 * @data_dir: Data direction. 244 */ 245struct mpi3mr_buf_map { 246 void *bsg_buf; 247 u32 bsg_buf_len; 248 void *kern_buf; 249 u32 kern_buf_len; 250 dma_addr_t kern_buf_dma; 251 u8 data_dir; 252 u16 num_dma_desc; 253 struct dma_memory_desc *dma_desc; 254}; 255 256/* IOC State definitions */ 257enum mpi3mr_iocstate { 258 MRIOC_STATE_READY = 1, 259 MRIOC_STATE_RESET, 260 MRIOC_STATE_FAULT, 261 MRIOC_STATE_BECOMING_READY, 262 MRIOC_STATE_RESET_REQUESTED, 263 MRIOC_STATE_UNRECOVERABLE, 264}; 265 266/* Reset reason code definitions*/ 267enum mpi3mr_reset_reason { 268 MPI3MR_RESET_FROM_BRINGUP = 1, 269 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 270 MPI3MR_RESET_FROM_APP = 3, 271 MPI3MR_RESET_FROM_EH_HOS = 4, 272 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 273 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 274 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 275 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 276 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 277 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 278 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 279 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 280 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 281 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 282 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 283 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 284 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 285 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 286 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 287 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 288 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 289 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 290 MPI3MR_RESET_FROM_SYSFS = 23, 291 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 292 MPI3MR_RESET_FROM_FIRMWARE = 27, 293 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 294 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 295}; 296 297/* Queue type definitions */ 298enum queue_type { 299 MPI3MR_DEFAULT_QUEUE = 0, 300 MPI3MR_POLL_QUEUE, 301}; 302 303/** 304 * struct mpi3mr_compimg_ver - replica of component image 305 * version defined in mpi30_image.h in host endianness 306 * 307 */ 308struct mpi3mr_compimg_ver { 309 u16 build_num; 310 u16 cust_id; 311 u8 ph_minor; 312 u8 ph_major; 313 u8 gen_minor; 314 u8 gen_major; 315}; 316 317/** 318 * struct mpi3mr_ioc_facs - replica of component image version 319 * defined in mpi30_ioc.h in host endianness 320 * 321 */ 322struct mpi3mr_ioc_facts { 323 u32 ioc_capabilities; 324 struct mpi3mr_compimg_ver fw_ver; 325 u32 mpi_version; 326 u16 max_reqs; 327 u16 product_id; 328 u16 op_req_sz; 329 u16 reply_sz; 330 u16 exceptions; 331 u16 max_perids; 332 u16 max_pds; 333 u16 max_sasexpanders; 334 u32 max_data_length; 335 u16 max_sasinitiators; 336 u16 max_enclosures; 337 u16 max_pcie_switches; 338 u16 max_nvme; 339 u16 max_vds; 340 u16 max_hpds; 341 u16 max_advhpds; 342 u16 max_raid_pds; 343 u16 min_devhandle; 344 u16 max_devhandle; 345 u16 max_op_req_q; 346 u16 max_op_reply_q; 347 u16 shutdown_timeout; 348 u8 ioc_num; 349 u8 who_init; 350 u16 max_msix_vectors; 351 u8 personality; 352 u8 dma_mask; 353 u8 protocol_flags; 354 u8 sge_mod_mask; 355 u8 sge_mod_value; 356 u8 sge_mod_shift; 357 u8 max_dev_per_tg; 358 u16 max_io_throttle_group; 359 u16 io_throttle_data_length; 360 u16 io_throttle_low; 361 u16 io_throttle_high; 362 363}; 364 365/** 366 * struct segments - memory descriptor structure to store 367 * virtual and dma addresses for operational queue segments. 368 * 369 * @segment: virtual address 370 * @segment_dma: dma address 371 */ 372struct segments { 373 void *segment; 374 dma_addr_t segment_dma; 375}; 376 377/** 378 * struct op_req_qinfo - Operational Request Queue Information 379 * 380 * @ci: consumer index 381 * @pi: producer index 382 * @num_request: Maximum number of entries in the queue 383 * @qid: Queue Id starting from 1 384 * @reply_qid: Associated reply queue Id 385 * @num_segments: Number of discontiguous memory segments 386 * @segment_qd: Depth of each segments 387 * @q_lock: Concurrent queue access lock 388 * @q_segments: Segment descriptor pointer 389 * @q_segment_list: Segment list base virtual address 390 * @q_segment_list_dma: Segment list base DMA address 391 */ 392struct op_req_qinfo { 393 u16 ci; 394 u16 pi; 395 u16 num_requests; 396 u16 qid; 397 u16 reply_qid; 398 u16 num_segments; 399 u16 segment_qd; 400 spinlock_t q_lock; 401 struct segments *q_segments; 402 void *q_segment_list; 403 dma_addr_t q_segment_list_dma; 404}; 405 406/** 407 * struct op_reply_qinfo - Operational Reply Queue Information 408 * 409 * @ci: consumer index 410 * @qid: Queue Id starting from 1 411 * @num_replies: Maximum number of entries in the queue 412 * @num_segments: Number of discontiguous memory segments 413 * @segment_qd: Depth of each segments 414 * @q_segments: Segment descriptor pointer 415 * @q_segment_list: Segment list base virtual address 416 * @q_segment_list_dma: Segment list base DMA address 417 * @ephase: Expected phased identifier for the reply queue 418 * @pend_ios: Number of IOs pending in HW for this queue 419 * @enable_irq_poll: Flag to indicate polling is enabled 420 * @in_use: Queue is handled by poll/ISR 421 * @qtype: Type of queue (types defined in enum queue_type) 422 */ 423struct op_reply_qinfo { 424 u16 ci; 425 u16 qid; 426 u16 num_replies; 427 u16 num_segments; 428 u16 segment_qd; 429 struct segments *q_segments; 430 void *q_segment_list; 431 dma_addr_t q_segment_list_dma; 432 u8 ephase; 433 atomic_t pend_ios; 434 bool enable_irq_poll; 435 atomic_t in_use; 436 enum queue_type qtype; 437}; 438 439/** 440 * struct mpi3mr_intr_info - Interrupt cookie information 441 * 442 * @mrioc: Adapter instance reference 443 * @os_irq: irq number 444 * @msix_index: MSIx index 445 * @op_reply_q: Associated operational reply queue 446 * @name: Dev name for the irq claiming device 447 */ 448struct mpi3mr_intr_info { 449 struct mpi3mr_ioc *mrioc; 450 int os_irq; 451 u16 msix_index; 452 struct op_reply_qinfo *op_reply_q; 453 char name[MPI3MR_NAME_LENGTH]; 454}; 455 456/** 457 * struct mpi3mr_throttle_group_info - Throttle group info 458 * 459 * @io_divert: Flag indicates io divert is on or off for the TG 460 * @need_qd_reduction: Flag to indicate QD reduction is needed 461 * @qd_reduction: Queue Depth reduction in units of 10% 462 * @fw_qd: QueueDepth value reported by the firmware 463 * @modified_qd: Modified QueueDepth value due to throttling 464 * @id: Throttle Group ID. 465 * @high: High limit to turn on throttling in 512 byte blocks 466 * @low: Low limit to turn off throttling in 512 byte blocks 467 * @pend_large_data_sz: Counter to track pending large data 468 */ 469struct mpi3mr_throttle_group_info { 470 u8 io_divert; 471 u8 need_qd_reduction; 472 u8 qd_reduction; 473 u16 fw_qd; 474 u16 modified_qd; 475 u16 id; 476 u32 high; 477 u32 low; 478 atomic_t pend_large_data_sz; 479}; 480 481/* HBA port flags */ 482#define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 483 484/* IOCTL data transfer sge*/ 485#define MPI3MR_NUM_IOCTL_SGE 256 486#define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 487 488/** 489 * struct mpi3mr_hba_port - HBA's port information 490 * @port_id: Port number 491 * @flags: HBA port flags 492 */ 493struct mpi3mr_hba_port { 494 struct list_head list; 495 u8 port_id; 496 u8 flags; 497}; 498 499/** 500 * struct mpi3mr_sas_port - Internal SAS port information 501 * @port_list: List of ports belonging to a SAS node 502 * @num_phys: Number of phys associated with port 503 * @marked_responding: used while refresing the sas ports 504 * @lowest_phy: lowest phy ID of current sas port 505 * @phy_mask: phy_mask of current sas port 506 * @hba_port: HBA port entry 507 * @remote_identify: Attached device identification 508 * @rphy: SAS transport layer rphy object 509 * @port: SAS transport layer port object 510 * @phy_list: mpi3mr_sas_phy objects belonging to this port 511 */ 512struct mpi3mr_sas_port { 513 struct list_head port_list; 514 u8 num_phys; 515 u8 marked_responding; 516 int lowest_phy; 517 u64 phy_mask; 518 struct mpi3mr_hba_port *hba_port; 519 struct sas_identify remote_identify; 520 struct sas_rphy *rphy; 521 struct sas_port *port; 522 struct list_head phy_list; 523}; 524 525/** 526 * struct mpi3mr_sas_phy - Internal SAS Phy information 527 * @port_siblings: List of phys belonging to a port 528 * @identify: Phy identification 529 * @remote_identify: Attached device identification 530 * @phy: SAS transport layer Phy object 531 * @phy_id: Unique phy id within a port 532 * @handle: Firmware device handle for this phy 533 * @attached_handle: Firmware device handle for attached device 534 * @phy_belongs_to_port: Flag to indicate phy belongs to port 535 @hba_port: HBA port entry 536 */ 537struct mpi3mr_sas_phy { 538 struct list_head port_siblings; 539 struct sas_identify identify; 540 struct sas_identify remote_identify; 541 struct sas_phy *phy; 542 u8 phy_id; 543 u16 handle; 544 u16 attached_handle; 545 u8 phy_belongs_to_port; 546 struct mpi3mr_hba_port *hba_port; 547}; 548 549/** 550 * struct mpi3mr_sas_node - SAS host/expander information 551 * @list: List of sas nodes in a controller 552 * @parent_dev: Parent device class 553 * @num_phys: Number phys belonging to sas_node 554 * @sas_address: SAS address of sas_node 555 * @handle: Firmware device handle for this sas_host/expander 556 * @sas_address_parent: SAS address of parent expander or host 557 * @enclosure_handle: Firmware handle of enclosure of this node 558 * @device_info: Capabilities of this sas_host/expander 559 * @non_responding: used to refresh the expander devices during reset 560 * @host_node: Flag to indicate this is a host_node 561 * @hba_port: HBA port entry 562 * @phy: A list of phys that make up this sas_host/expander 563 * @sas_port_list: List of internal ports of this node 564 * @rphy: sas_rphy object of this expander node 565 */ 566struct mpi3mr_sas_node { 567 struct list_head list; 568 struct device *parent_dev; 569 u8 num_phys; 570 u64 sas_address; 571 u16 handle; 572 u64 sas_address_parent; 573 u16 enclosure_handle; 574 u64 enclosure_logical_id; 575 u8 non_responding; 576 u8 host_node; 577 struct mpi3mr_hba_port *hba_port; 578 struct mpi3mr_sas_phy *phy; 579 struct list_head sas_port_list; 580 struct sas_rphy *rphy; 581}; 582 583/** 584 * struct mpi3mr_enclosure_node - enclosure information 585 * @list: List of enclosures 586 * @pg0: Enclosure page 0; 587 */ 588struct mpi3mr_enclosure_node { 589 struct list_head list; 590 struct mpi3_enclosure_page0 pg0; 591}; 592 593/** 594 * struct tgt_dev_sas_sata - SAS/SATA device specific 595 * information cached from firmware given data 596 * 597 * @sas_address: World wide unique SAS address 598 * @sas_address_parent: Sas address of parent expander or host 599 * @dev_info: Device information bits 600 * @phy_id: Phy identifier provided in device page 0 601 * @attached_phy_id: Attached phy identifier provided in device page 0 602 * @sas_transport_attached: Is this device exposed to transport 603 * @pend_sas_rphy_add: Flag to check device is in process of add 604 * @hba_port: HBA port entry 605 * @rphy: SAS transport layer rphy object 606 */ 607struct tgt_dev_sas_sata { 608 u64 sas_address; 609 u64 sas_address_parent; 610 u16 dev_info; 611 u8 phy_id; 612 u8 attached_phy_id; 613 u8 sas_transport_attached; 614 u8 pend_sas_rphy_add; 615 struct mpi3mr_hba_port *hba_port; 616 struct sas_rphy *rphy; 617}; 618 619/** 620 * struct tgt_dev_pcie - PCIe device specific information cached 621 * from firmware given data 622 * 623 * @mdts: Maximum data transfer size 624 * @capb: Device capabilities 625 * @pgsz: Device page size 626 * @abort_to: Timeout for abort TM 627 * @reset_to: Timeout for Target/LUN reset TM 628 * @dev_info: Device information bits 629 */ 630struct tgt_dev_pcie { 631 u32 mdts; 632 u16 capb; 633 u8 pgsz; 634 u8 abort_to; 635 u8 reset_to; 636 u16 dev_info; 637}; 638 639/** 640 * struct tgt_dev_vd - virtual device specific information 641 * cached from firmware given data 642 * 643 * @state: State of the VD 644 * @tg_qd_reduction: Queue Depth reduction in units of 10% 645 * @tg_id: VDs throttle group ID 646 * @high: High limit to turn on throttling in 512 byte blocks 647 * @low: Low limit to turn off throttling in 512 byte blocks 648 * @tg: Pointer to throttle group info 649 */ 650struct tgt_dev_vd { 651 u8 state; 652 u8 tg_qd_reduction; 653 u16 tg_id; 654 u32 tg_high; 655 u32 tg_low; 656 struct mpi3mr_throttle_group_info *tg; 657}; 658 659 660/** 661 * union _form_spec_inf - union of device specific information 662 */ 663union _form_spec_inf { 664 struct tgt_dev_sas_sata sas_sata_inf; 665 struct tgt_dev_pcie pcie_inf; 666 struct tgt_dev_vd vd_inf; 667}; 668 669enum mpi3mr_dev_state { 670 MPI3MR_DEV_CREATED = 1, 671 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 672 MPI3MR_DEV_DELETED = 3, 673}; 674 675/** 676 * struct mpi3mr_tgt_dev - target device data structure 677 * 678 * @list: List pointer 679 * @starget: Scsi_target pointer 680 * @dev_handle: FW device handle 681 * @parent_handle: FW parent device handle 682 * @slot: Slot number 683 * @encl_handle: FW enclosure handle 684 * @perst_id: FW assigned Persistent ID 685 * @devpg0_flag: Device Page0 flag 686 * @dev_type: SAS/SATA/PCIE device type 687 * @is_hidden: Should be exposed to upper layers or not 688 * @host_exposed: Already exposed to host or not 689 * @io_unit_port: IO Unit port ID 690 * @non_stl: Is this device not to be attached with SAS TL 691 * @io_throttle_enabled: I/O throttling needed or not 692 * @wslen: Write same max length 693 * @q_depth: Device specific Queue Depth 694 * @wwid: World wide ID 695 * @enclosure_logical_id: Enclosure logical identifier 696 * @dev_spec: Device type specific information 697 * @ref_count: Reference count 698 * @state: device state 699 */ 700struct mpi3mr_tgt_dev { 701 struct list_head list; 702 struct scsi_target *starget; 703 u16 dev_handle; 704 u16 parent_handle; 705 u16 slot; 706 u16 encl_handle; 707 u16 perst_id; 708 u16 devpg0_flag; 709 u8 dev_type; 710 u8 is_hidden; 711 u8 host_exposed; 712 u8 io_unit_port; 713 u8 non_stl; 714 u8 io_throttle_enabled; 715 u16 wslen; 716 u16 q_depth; 717 u64 wwid; 718 u64 enclosure_logical_id; 719 union _form_spec_inf dev_spec; 720 struct kref ref_count; 721 enum mpi3mr_dev_state state; 722}; 723 724/** 725 * mpi3mr_tgtdev_get - k reference incrementor 726 * @s: Target device reference 727 * 728 * Increment target device reference count. 729 */ 730static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 731{ 732 kref_get(&s->ref_count); 733} 734 735/** 736 * mpi3mr_free_tgtdev - target device memory dealloctor 737 * @r: k reference pointer of the target device 738 * 739 * Free target device memory when no reference. 740 */ 741static inline void mpi3mr_free_tgtdev(struct kref *r) 742{ 743 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 744} 745 746/** 747 * mpi3mr_tgtdev_put - k reference decrementor 748 * @s: Target device reference 749 * 750 * Decrement target device reference count. 751 */ 752static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 753{ 754 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 755} 756 757 758/** 759 * struct mpi3mr_stgt_priv_data - SCSI target private structure 760 * 761 * @starget: Scsi_target pointer 762 * @dev_handle: FW device handle 763 * @perst_id: FW assigned Persistent ID 764 * @num_luns: Number of Logical Units 765 * @block_io: I/O blocked to the device or not 766 * @dev_removed: Device removed in the Firmware 767 * @dev_removedelay: Device is waiting to be removed in FW 768 * @dev_type: Device type 769 * @dev_nvme_dif: Device is NVMe DIF enabled 770 * @wslen: Write same max length 771 * @io_throttle_enabled: I/O throttling needed or not 772 * @io_divert: Flag indicates io divert is on or off for the dev 773 * @throttle_group: Pointer to throttle group info 774 * @tgt_dev: Internal target device pointer 775 * @pend_count: Counter to track pending I/Os during error 776 * handling 777 */ 778struct mpi3mr_stgt_priv_data { 779 struct scsi_target *starget; 780 u16 dev_handle; 781 u16 perst_id; 782 u32 num_luns; 783 atomic_t block_io; 784 u8 dev_removed; 785 u8 dev_removedelay; 786 u8 dev_type; 787 u8 dev_nvme_dif; 788 u16 wslen; 789 u8 io_throttle_enabled; 790 u8 io_divert; 791 struct mpi3mr_throttle_group_info *throttle_group; 792 struct mpi3mr_tgt_dev *tgt_dev; 793 u32 pend_count; 794}; 795 796/** 797 * struct mpi3mr_stgt_priv_data - SCSI device private structure 798 * 799 * @tgt_priv_data: Scsi_target private data pointer 800 * @lun_id: LUN ID of the device 801 * @ncq_prio_enable: NCQ priority enable for SATA device 802 * @pend_count: Counter to track pending I/Os during error 803 * handling 804 * @wslen: Write same max length 805 */ 806struct mpi3mr_sdev_priv_data { 807 struct mpi3mr_stgt_priv_data *tgt_priv_data; 808 u32 lun_id; 809 u8 ncq_prio_enable; 810 u32 pend_count; 811 u16 wslen; 812}; 813 814/** 815 * struct mpi3mr_drv_cmd - Internal command tracker 816 * 817 * @mutex: Command mutex 818 * @done: Completeor for wakeup 819 * @reply: Firmware reply for internal commands 820 * @sensebuf: Sensebuf for SCSI IO commands 821 * @iou_rc: IO Unit control reason code 822 * @state: Command State 823 * @dev_handle: Firmware handle for device specific commands 824 * @ioc_status: IOC status from the firmware 825 * @ioc_loginfo:IOC log info from the firmware 826 * @is_waiting: Is the command issued in block mode 827 * @is_sense: Is Sense data present 828 * @retry_count: Retry count for retriable commands 829 * @host_tag: Host tag used by the command 830 * @callback: Callback for non blocking commands 831 */ 832struct mpi3mr_drv_cmd { 833 struct mutex mutex; 834 struct completion done; 835 void *reply; 836 u8 *sensebuf; 837 u8 iou_rc; 838 u16 state; 839 u16 dev_handle; 840 u16 ioc_status; 841 u32 ioc_loginfo; 842 u8 is_waiting; 843 u8 is_sense; 844 u8 retry_count; 845 u16 host_tag; 846 847 void (*callback)(struct mpi3mr_ioc *mrioc, 848 struct mpi3mr_drv_cmd *drv_cmd); 849}; 850 851/** 852 * struct dma_memory_desc - memory descriptor structure to store 853 * virtual address, dma address and size for any generic dma 854 * memory allocations in the driver. 855 * 856 * @size: buffer size 857 * @addr: virtual address 858 * @dma_addr: dma address 859 */ 860struct dma_memory_desc { 861 u32 size; 862 void *addr; 863 dma_addr_t dma_addr; 864}; 865 866 867/** 868 * struct chain_element - memory descriptor structure to store 869 * virtual and dma addresses for chain elements. 870 * 871 * @addr: virtual address 872 * @dma_addr: dma address 873 */ 874struct chain_element { 875 void *addr; 876 dma_addr_t dma_addr; 877}; 878 879/** 880 * struct scmd_priv - SCSI command private data 881 * 882 * @host_tag: Host tag specific to operational queue 883 * @in_lld_scope: Command in LLD scope or not 884 * @meta_sg_valid: DIX command with meta data SGL or not 885 * @scmd: SCSI Command pointer 886 * @req_q_idx: Operational request queue index 887 * @chain_idx: Chain frame index 888 * @meta_chain_idx: Chain frame index of meta data SGL 889 * @mpi3mr_scsiio_req: MPI SCSI IO request 890 */ 891struct scmd_priv { 892 u16 host_tag; 893 u8 in_lld_scope; 894 u8 meta_sg_valid; 895 struct scsi_cmnd *scmd; 896 u16 req_q_idx; 897 int chain_idx; 898 int meta_chain_idx; 899 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 900}; 901 902/** 903 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 904 * private data 905 * 906 * @list: List pointer 907 * @pdev: PCI device pointer 908 * @shost: Scsi_Host pointer 909 * @id: Controller ID 910 * @cpu_count: Number of online CPUs 911 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 912 * @name: Controller ASCII name 913 * @driver_name: Driver ASCII name 914 * @sysif_regs: System interface registers virtual address 915 * @sysif_regs_phys: System interface registers physical address 916 * @bars: PCI BARS 917 * @dma_mask: DMA mask 918 * @msix_count: Number of MSIX vectors used 919 * @intr_enabled: Is interrupts enabled 920 * @num_admin_req: Number of admin requests 921 * @admin_req_q_sz: Admin request queue size 922 * @admin_req_pi: Admin request queue producer index 923 * @admin_req_ci: Admin request queue consumer index 924 * @admin_req_base: Admin request queue base virtual address 925 * @admin_req_dma: Admin request queue base dma address 926 * @admin_req_lock: Admin queue access lock 927 * @num_admin_replies: Number of admin replies 928 * @admin_reply_q_sz: Admin reply queue size 929 * @admin_reply_ci: Admin reply queue consumer index 930 * @admin_reply_ephase:Admin reply queue expected phase 931 * @admin_reply_base: Admin reply queue base virtual address 932 * @admin_reply_dma: Admin reply queue base dma address 933 * @admin_reply_q_in_use: Queue is handled by poll/ISR 934 * @ready_timeout: Controller ready timeout 935 * @intr_info: Interrupt cookie pointer 936 * @intr_info_count: Number of interrupt cookies 937 * @is_intr_info_set: Flag to indicate intr info is setup 938 * @num_queues: Number of operational queues 939 * @num_op_req_q: Number of operational request queues 940 * @req_qinfo: Operational request queue info pointer 941 * @num_op_reply_q: Number of operational reply queues 942 * @op_reply_qinfo: Operational reply queue info pointer 943 * @init_cmds: Command tracker for initialization commands 944 * @cfg_cmds: Command tracker for configuration requests 945 * @facts: Cached IOC facts data 946 * @op_reply_desc_sz: Operational reply descriptor size 947 * @num_reply_bufs: Number of reply buffers allocated 948 * @reply_buf_pool: Reply buffer pool 949 * @reply_buf: Reply buffer base virtual address 950 * @reply_buf_dma: Reply buffer DMA address 951 * @reply_buf_dma_max_address: Reply DMA address max limit 952 * @reply_free_qsz: Reply free queue size 953 * @reply_free_q_pool: Reply free queue pool 954 * @reply_free_q: Reply free queue base virtual address 955 * @reply_free_q_dma: Reply free queue base DMA address 956 * @reply_free_queue_lock: Reply free queue lock 957 * @reply_free_queue_host_index: Reply free queue host index 958 * @num_sense_bufs: Number of sense buffers 959 * @sense_buf_pool: Sense buffer pool 960 * @sense_buf: Sense buffer base virtual address 961 * @sense_buf_dma: Sense buffer base DMA address 962 * @sense_buf_q_sz: Sense buffer queue size 963 * @sense_buf_q_pool: Sense buffer queue pool 964 * @sense_buf_q: Sense buffer queue virtual address 965 * @sense_buf_q_dma: Sense buffer queue DMA address 966 * @sbq_lock: Sense buffer queue lock 967 * @sbq_host_index: Sense buffer queuehost index 968 * @event_masks: Event mask bitmap 969 * @fwevt_worker_name: Firmware event worker thread name 970 * @fwevt_worker_thread: Firmware event worker thread 971 * @fwevt_lock: Firmware event lock 972 * @fwevt_list: Firmware event list 973 * @watchdog_work_q_name: Fault watchdog worker thread name 974 * @watchdog_work_q: Fault watchdog worker thread 975 * @watchdog_work: Fault watchdog work 976 * @watchdog_lock: Fault watchdog lock 977 * @is_driver_loading: Is driver still loading 978 * @scan_started: Async scan started 979 * @scan_failed: Asycn scan failed 980 * @stop_drv_processing: Stop all command processing 981 * @device_refresh_on: Don't process the events until devices are refreshed 982 * @max_host_ios: Maximum host I/O count 983 * @max_sgl_entries: Max SGL entries per I/O 984 * @chain_buf_count: Chain buffer count 985 * @chain_buf_pool: Chain buffer pool 986 * @chain_sgl_list: Chain SGL list 987 * @chain_bitmap: Chain buffer allocator bitmap 988 * @chain_buf_lock: Chain buffer list lock 989 * @bsg_cmds: Command tracker for BSG command 990 * @host_tm_cmds: Command tracker for task management commands 991 * @dev_rmhs_cmds: Command tracker for device removal commands 992 * @evtack_cmds: Command tracker for event ack commands 993 * @devrem_bitmap: Device removal bitmap 994 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 995 * @removepend_bitmap: Remove pending bitmap 996 * @delayed_rmhs_list: Delayed device removal list 997 * @evtack_cmds_bitmap: Event Ack bitmap 998 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 999 * @ts_update_counter: Timestamp update counter 1000 * @reset_in_progress: Reset in progress flag 1001 * @unrecoverable: Controller unrecoverable flag 1002 * @prev_reset_result: Result of previous reset 1003 * @reset_mutex: Controller reset mutex 1004 * @reset_waitq: Controller reset wait queue 1005 * @prepare_for_reset: Prepare for reset event received 1006 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 1007 * @prp_list_virt: NVMe encapsulated PRP list virtual base 1008 * @prp_list_dma: NVMe encapsulated PRP list DMA 1009 * @prp_sz: NVME encapsulated PRP list size 1010 * @diagsave_timeout: Diagnostic information save timeout 1011 * @logging_level: Controller debug logging level 1012 * @flush_io_count: I/O count to flush after reset 1013 * @current_event: Firmware event currently in process 1014 * @driver_info: Driver, Kernel, OS information to firmware 1015 * @change_count: Topology change count 1016 * @pel_enabled: Persistent Event Log(PEL) enabled or not 1017 * @pel_abort_requested: PEL abort is requested or not 1018 * @pel_class: PEL Class identifier 1019 * @pel_locale: PEL Locale identifier 1020 * @pel_cmds: Command tracker for PEL wait command 1021 * @pel_abort_cmd: Command tracker for PEL abort command 1022 * @pel_newest_seqnum: Newest PEL sequenece number 1023 * @pel_seqnum_virt: PEL sequence number virtual address 1024 * @pel_seqnum_dma: PEL sequence number DMA address 1025 * @pel_seqnum_sz: PEL sequenece number size 1026 * @op_reply_q_offset: Operational reply queue offset with MSIx 1027 * @default_qcount: Total Default queues 1028 * @active_poll_qcount: Currently active poll queue count 1029 * @requested_poll_qcount: User requested poll queue count 1030 * @bsg_dev: BSG device structure 1031 * @bsg_queue: Request queue for BSG device 1032 * @stop_bsgs: Stop BSG request flag 1033 * @logdata_buf: Circular buffer to store log data entries 1034 * @logdata_buf_idx: Index of entry in buffer to store 1035 * @logdata_entry_sz: log data entry size 1036 * @pend_large_data_sz: Counter to track pending large data 1037 * @io_throttle_data_length: I/O size to track in 512b blocks 1038 * @io_throttle_high: I/O size to start throttle in 512b blocks 1039 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1040 * @num_io_throttle_group: Maximum number of throttle groups 1041 * @throttle_groups: Pointer to throttle group info structures 1042 * @cfg_page: Default memory for configuration pages 1043 * @cfg_page_dma: Configuration page DMA address 1044 * @cfg_page_sz: Default configuration page memory size 1045 * @sas_transport_enabled: SAS transport enabled or not 1046 * @scsi_device_channel: Channel ID for SCSI devices 1047 * @transport_cmds: Command tracker for SAS transport commands 1048 * @sas_hba: SAS node for the controller 1049 * @sas_expander_list: SAS node list of expanders 1050 * @sas_node_lock: Lock to protect SAS node list 1051 * @hba_port_table_list: List of HBA Ports 1052 * @enclosure_list: List of Enclosure objects 1053 * @ioctl_dma_pool: DMA pool for IOCTL data buffers 1054 * @ioctl_sge: DMA buffer descriptors for IOCTL data 1055 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain 1056 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response 1057 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not 1058 */ 1059struct mpi3mr_ioc { 1060 struct list_head list; 1061 struct pci_dev *pdev; 1062 struct Scsi_Host *shost; 1063 u8 id; 1064 int cpu_count; 1065 bool enable_segqueue; 1066 u32 irqpoll_sleep; 1067 1068 char name[MPI3MR_NAME_LENGTH]; 1069 char driver_name[MPI3MR_NAME_LENGTH]; 1070 1071 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1072 resource_size_t sysif_regs_phys; 1073 int bars; 1074 u64 dma_mask; 1075 1076 u16 msix_count; 1077 u8 intr_enabled; 1078 1079 u16 num_admin_req; 1080 u32 admin_req_q_sz; 1081 u16 admin_req_pi; 1082 u16 admin_req_ci; 1083 void *admin_req_base; 1084 dma_addr_t admin_req_dma; 1085 spinlock_t admin_req_lock; 1086 1087 u16 num_admin_replies; 1088 u32 admin_reply_q_sz; 1089 u16 admin_reply_ci; 1090 u8 admin_reply_ephase; 1091 void *admin_reply_base; 1092 dma_addr_t admin_reply_dma; 1093 atomic_t admin_reply_q_in_use; 1094 1095 u32 ready_timeout; 1096 1097 struct mpi3mr_intr_info *intr_info; 1098 u16 intr_info_count; 1099 bool is_intr_info_set; 1100 1101 u16 num_queues; 1102 u16 num_op_req_q; 1103 struct op_req_qinfo *req_qinfo; 1104 1105 u16 num_op_reply_q; 1106 struct op_reply_qinfo *op_reply_qinfo; 1107 1108 struct mpi3mr_drv_cmd init_cmds; 1109 struct mpi3mr_drv_cmd cfg_cmds; 1110 struct mpi3mr_ioc_facts facts; 1111 u16 op_reply_desc_sz; 1112 1113 u32 num_reply_bufs; 1114 struct dma_pool *reply_buf_pool; 1115 u8 *reply_buf; 1116 dma_addr_t reply_buf_dma; 1117 dma_addr_t reply_buf_dma_max_address; 1118 1119 u16 reply_free_qsz; 1120 u16 reply_sz; 1121 struct dma_pool *reply_free_q_pool; 1122 __le64 *reply_free_q; 1123 dma_addr_t reply_free_q_dma; 1124 spinlock_t reply_free_queue_lock; 1125 u32 reply_free_queue_host_index; 1126 1127 u32 num_sense_bufs; 1128 struct dma_pool *sense_buf_pool; 1129 u8 *sense_buf; 1130 dma_addr_t sense_buf_dma; 1131 1132 u16 sense_buf_q_sz; 1133 struct dma_pool *sense_buf_q_pool; 1134 __le64 *sense_buf_q; 1135 dma_addr_t sense_buf_q_dma; 1136 spinlock_t sbq_lock; 1137 u32 sbq_host_index; 1138 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1139 1140 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 1141 struct workqueue_struct *fwevt_worker_thread; 1142 spinlock_t fwevt_lock; 1143 struct list_head fwevt_list; 1144 1145 char watchdog_work_q_name[20]; 1146 struct workqueue_struct *watchdog_work_q; 1147 struct delayed_work watchdog_work; 1148 spinlock_t watchdog_lock; 1149 1150 u8 is_driver_loading; 1151 u8 scan_started; 1152 u16 scan_failed; 1153 u8 stop_drv_processing; 1154 u8 device_refresh_on; 1155 1156 u16 max_host_ios; 1157 spinlock_t tgtdev_lock; 1158 struct list_head tgtdev_list; 1159 u16 max_sgl_entries; 1160 1161 u32 chain_buf_count; 1162 struct dma_pool *chain_buf_pool; 1163 struct chain_element *chain_sgl_list; 1164 unsigned long *chain_bitmap; 1165 spinlock_t chain_buf_lock; 1166 1167 struct mpi3mr_drv_cmd bsg_cmds; 1168 struct mpi3mr_drv_cmd host_tm_cmds; 1169 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1170 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1171 unsigned long *devrem_bitmap; 1172 u16 dev_handle_bitmap_bits; 1173 unsigned long *removepend_bitmap; 1174 struct list_head delayed_rmhs_list; 1175 unsigned long *evtack_cmds_bitmap; 1176 struct list_head delayed_evtack_cmds_list; 1177 1178 u32 ts_update_counter; 1179 u8 reset_in_progress; 1180 u8 unrecoverable; 1181 int prev_reset_result; 1182 struct mutex reset_mutex; 1183 wait_queue_head_t reset_waitq; 1184 1185 u8 prepare_for_reset; 1186 u16 prepare_for_reset_timeout_counter; 1187 1188 void *prp_list_virt; 1189 dma_addr_t prp_list_dma; 1190 u32 prp_sz; 1191 1192 u16 diagsave_timeout; 1193 int logging_level; 1194 u16 flush_io_count; 1195 1196 struct mpi3mr_fwevt *current_event; 1197 struct mpi3_driver_info_layout driver_info; 1198 u16 change_count; 1199 1200 u8 pel_enabled; 1201 u8 pel_abort_requested; 1202 u8 pel_class; 1203 u16 pel_locale; 1204 struct mpi3mr_drv_cmd pel_cmds; 1205 struct mpi3mr_drv_cmd pel_abort_cmd; 1206 1207 u32 pel_newest_seqnum; 1208 void *pel_seqnum_virt; 1209 dma_addr_t pel_seqnum_dma; 1210 u32 pel_seqnum_sz; 1211 1212 u16 op_reply_q_offset; 1213 u16 default_qcount; 1214 u16 active_poll_qcount; 1215 u16 requested_poll_qcount; 1216 1217 struct device bsg_dev; 1218 struct request_queue *bsg_queue; 1219 u8 stop_bsgs; 1220 u8 *logdata_buf; 1221 u16 logdata_buf_idx; 1222 u16 logdata_entry_sz; 1223 1224 atomic_t pend_large_data_sz; 1225 u32 io_throttle_data_length; 1226 u32 io_throttle_high; 1227 u32 io_throttle_low; 1228 u16 num_io_throttle_group; 1229 struct mpi3mr_throttle_group_info *throttle_groups; 1230 1231 void *cfg_page; 1232 dma_addr_t cfg_page_dma; 1233 u16 cfg_page_sz; 1234 1235 u8 sas_transport_enabled; 1236 u8 scsi_device_channel; 1237 struct mpi3mr_drv_cmd transport_cmds; 1238 struct mpi3mr_sas_node sas_hba; 1239 struct list_head sas_expander_list; 1240 spinlock_t sas_node_lock; 1241 struct list_head hba_port_table_list; 1242 struct list_head enclosure_list; 1243 1244 struct dma_pool *ioctl_dma_pool; 1245 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 1246 struct dma_memory_desc ioctl_chain_sge; 1247 struct dma_memory_desc ioctl_resp_sge; 1248 bool ioctl_sges_allocated; 1249}; 1250 1251/** 1252 * struct mpi3mr_fwevt - Firmware event structure. 1253 * 1254 * @list: list head 1255 * @work: Work structure 1256 * @mrioc: Adapter instance reference 1257 * @event_id: MPI3 firmware event ID 1258 * @send_ack: Event acknowledgment required or not 1259 * @process_evt: Bottomhalf processing required or not 1260 * @evt_ctx: Event context to send in Ack 1261 * @event_data_size: size of the event data in bytes 1262 * @pending_at_sml: waiting for device add/remove API to complete 1263 * @discard: discard this event 1264 * @ref_count: kref count 1265 * @event_data: Actual MPI3 event data 1266 */ 1267struct mpi3mr_fwevt { 1268 struct list_head list; 1269 struct work_struct work; 1270 struct mpi3mr_ioc *mrioc; 1271 u16 event_id; 1272 bool send_ack; 1273 bool process_evt; 1274 u32 evt_ctx; 1275 u16 event_data_size; 1276 bool pending_at_sml; 1277 bool discard; 1278 struct kref ref_count; 1279 char event_data[] __aligned(4); 1280}; 1281 1282 1283/** 1284 * struct delayed_dev_rmhs_node - Delayed device removal node 1285 * 1286 * @list: list head 1287 * @handle: Device handle 1288 * @iou_rc: IO Unit Control Reason Code 1289 */ 1290struct delayed_dev_rmhs_node { 1291 struct list_head list; 1292 u16 handle; 1293 u8 iou_rc; 1294}; 1295 1296/** 1297 * struct delayed_evt_ack_node - Delayed event ack node 1298 * @list: list head 1299 * @event: MPI3 event ID 1300 * @event_ctx: event context 1301 */ 1302struct delayed_evt_ack_node { 1303 struct list_head list; 1304 u8 event; 1305 u32 event_ctx; 1306}; 1307 1308int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1309void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1310int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1311int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1312void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1313int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1314int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1315u16 admin_req_sz, u8 ignore_reset); 1316int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1317 struct op_req_qinfo *opreqq, u8 *req); 1318void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1319 dma_addr_t dma_addr); 1320void mpi3mr_build_zero_len_sge(void *paddr); 1321void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1322 dma_addr_t phys_addr); 1323void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1324 dma_addr_t phys_addr); 1325void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1326 u64 sense_buf_dma); 1327 1328void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1329void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1330void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1331 struct mpi3_event_notification_reply *event_reply); 1332void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1333 struct mpi3_default_reply_descriptor *reply_desc, 1334 u64 *reply_dma, u16 qidx); 1335void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1336void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1337 1338int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1339 u32 reset_reason, u8 snapdump); 1340void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1341void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1342 1343enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1344int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1345 u32 event_ctx); 1346 1347void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1348void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1349void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1350void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1351void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); 1352void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1353void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1354void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1355void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1356int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1357 struct op_reply_qinfo *op_reply_q); 1358int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1359void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1360void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1361int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1362 u16 handle, uint lun, u16 htag, ulong timeout, 1363 struct mpi3mr_drv_cmd *drv_cmd, 1364 u8 *resp_code, struct scsi_cmnd *scmd); 1365struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1366 struct mpi3mr_ioc *mrioc, u16 handle); 1367void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1368 struct mpi3mr_drv_cmd *drv_cmd); 1369int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1370 struct mpi3mr_drv_cmd *drv_cmd); 1371void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1372 u16 event_data_size); 1373struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1374 struct mpi3mr_ioc *mrioc, u16 handle); 1375extern const struct attribute_group *mpi3mr_host_groups[]; 1376extern const struct attribute_group *mpi3mr_dev_groups[]; 1377 1378extern struct sas_function_template mpi3mr_transport_functions; 1379extern struct scsi_transport_template *mpi3mr_transport_template; 1380 1381int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1382 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1383int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1384 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1385 u32 form_spec); 1386int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1387 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1388 u32 form_spec); 1389int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1390 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1391 u32 form_spec); 1392int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1393 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1394 u32 form_spec); 1395int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1396 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1397 u32 form_spec); 1398int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1399 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1400int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1401 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1402int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1403 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1404int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1405 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1406 1407u8 mpi3mr_is_expander_device(u16 device_info); 1408int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1409void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1410 struct mpi3mr_hba_port *hba_port); 1411struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1412 *mrioc, u16 handle); 1413struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1414 u8 port_id); 1415void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1416void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1417void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1418 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1419 struct mpi3mr_hba_port *hba_port); 1420void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1421 struct mpi3mr_tgt_dev *tgtdev); 1422int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1423 struct mpi3mr_tgt_dev *tgtdev); 1424void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1425 struct mpi3mr_tgt_dev *tgtdev); 1426struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1427 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1428void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1429 bool device_add); 1430void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1431void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1432void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1433void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1434void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1435void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1436int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1437void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1438 struct mpi3mr_sas_node *sas_expander); 1439#endif /*MPI3MR_H_INCLUDED*/ 1440