1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 *  Copyright 2018-2023 Broadcom Inc. All rights reserved.
4 */
5#ifndef MPI30_IMAGE_H
6#define MPI30_IMAGE_H     1
7struct mpi3_comp_image_version {
8	__le16     build_num;
9	__le16     customer_id;
10	u8         phase_minor;
11	u8         phase_major;
12	u8         gen_minor;
13	u8         gen_major;
14};
15
16struct mpi3_hash_exclusion_format {
17	__le32                     offset;
18	__le32                     size;
19};
20
21#define MPI3_IMAGE_HASH_EXCUSION_NUM                           (4)
22struct mpi3_component_image_header {
23	__le32                            signature0;
24	__le32                            load_address;
25	__le32                            data_size;
26	__le32                            start_offset;
27	__le32                            signature1;
28	__le32                            flash_offset;
29	__le32                            image_size;
30	__le32                            version_string_offset;
31	__le32                            build_date_string_offset;
32	__le32                            build_time_string_offset;
33	__le32                            environment_variable_offset;
34	__le32                            application_specific;
35	__le32                            signature2;
36	__le32                            header_size;
37	__le32                            crc;
38	__le32                            flags;
39	__le32                            secondary_flash_offset;
40	__le32                            etp_offset;
41	__le32                            etp_size;
42	union mpi3_version_union             rmc_interface_version;
43	union mpi3_version_union             etp_interface_version;
44	struct mpi3_comp_image_version        component_image_version;
45	struct mpi3_hash_exclusion_format     hash_exclusion[MPI3_IMAGE_HASH_EXCUSION_NUM];
46	__le32                            next_image_header_offset;
47	union mpi3_version_union             security_version;
48	__le32                            reserved84[31];
49};
50
51#define MPI3_IMAGE_HEADER_SIGNATURE0_MPI3                     (0xeb00003e)
52#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_INVALID                (0x00000000)
53#define MPI3_IMAGE_HEADER_SIGNATURE1_APPLICATION              (0x20505041)
54#define MPI3_IMAGE_HEADER_SIGNATURE1_FIRST_MUTABLE            (0x20434d46)
55#define MPI3_IMAGE_HEADER_SIGNATURE1_BSP                      (0x20505342)
56#define MPI3_IMAGE_HEADER_SIGNATURE1_ROM_BIOS                 (0x534f4942)
57#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_X64                  (0x4d494948)
58#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_ARM                  (0x41494948)
59#define MPI3_IMAGE_HEADER_SIGNATURE1_CPLD                     (0x444c5043)
60#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD                      (0x20445053)
61#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE                (0x20534147)
62#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP                     (0x504c4250)
63#define MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST                 (0x464e414d)
64#define MPI3_IMAGE_HEADER_SIGNATURE1_OEM                      (0x204d454f)
65#define MPI3_IMAGE_HEADER_SIGNATURE1_RMC                      (0x20434d52)
66#define MPI3_IMAGE_HEADER_SIGNATURE1_SMM                      (0x204d4d53)
67#define MPI3_IMAGE_HEADER_SIGNATURE1_PSW                      (0x20575350)
68#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE                    (0x50584546)
69#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK         (0x00000030)
70#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI          (0x00000000)
71#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI           (0x00000010)
72#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA                 (0x00000008)
73#define MPI3_IMAGE_HEADER_FLAGS_REQUIRES_ACTIVATION           (0x00000004)
74#define MPI3_IMAGE_HEADER_FLAGS_COMPRESSED                    (0x00000002)
75#define MPI3_IMAGE_HEADER_FLAGS_FLASH                         (0x00000001)
76#define MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET                   (0x00)
77#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_OFFSET                 (0x04)
78#define MPI3_IMAGE_HEADER_DATA_SIZE_OFFSET                    (0x08)
79#define MPI3_IMAGE_HEADER_START_OFFSET_OFFSET                 (0x0c)
80#define MPI3_IMAGE_HEADER_SIGNATURE1_OFFSET                   (0x10)
81#define MPI3_IMAGE_HEADER_FLASH_OFFSET_OFFSET                 (0x14)
82#define MPI3_IMAGE_HEADER_FLASH_SIZE_OFFSET                   (0x18)
83#define MPI3_IMAGE_HEADER_VERSION_STRING_OFFSET_OFFSET        (0x1c)
84#define MPI3_IMAGE_HEADER_BUILD_DATE_STRING_OFFSET_OFFSET     (0x20)
85#define MPI3_IMAGE_HEADER_BUILD_TIME_OFFSET_OFFSET            (0x24)
86#define MPI3_IMAGE_HEADER_ENVIROMENT_VAR_OFFSET_OFFSET        (0x28)
87#define MPI3_IMAGE_HEADER_APPLICATION_SPECIFIC_OFFSET         (0x2c)
88#define MPI3_IMAGE_HEADER_SIGNATURE2_OFFSET                   (0x30)
89#define MPI3_IMAGE_HEADER_HEADER_SIZE_OFFSET                  (0x34)
90#define MPI3_IMAGE_HEADER_CRC_OFFSET                          (0x38)
91#define MPI3_IMAGE_HEADER_FLAGS_OFFSET                        (0x3c)
92#define MPI3_IMAGE_HEADER_SECONDARY_FLASH_OFFSET_OFFSET       (0x40)
93#define MPI3_IMAGE_HEADER_ETP_OFFSET_OFFSET                   (0x44)
94#define MPI3_IMAGE_HEADER_ETP_SIZE_OFFSET                     (0x48)
95#define MPI3_IMAGE_HEADER_RMC_INTERFACE_VER_OFFSET            (0x4c)
96#define MPI3_IMAGE_HEADER_ETP_INTERFACE_VER_OFFSET            (0x50)
97#define MPI3_IMAGE_HEADER_COMPONENT_IMAGE_VER_OFFSET          (0x54)
98#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET               (0x5c)
99#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET     (0x7c)
100#define MPI3_IMAGE_HEADER_SIZE                                (0x100)
101#ifndef MPI3_CI_MANIFEST_MPI_MAX
102#define MPI3_CI_MANIFEST_MPI_MAX                               (1)
103#endif
104struct mpi3_ci_manifest_mpi_comp_image_ref {
105	__le32                                signature1;
106	__le32                                reserved04[3];
107	struct mpi3_comp_image_version            component_image_version;
108	__le32                                component_image_version_string_offset;
109	__le32                                crc;
110};
111
112struct mpi3_ci_manifest_mpi {
113	u8                                       manifest_type;
114	u8                                       reserved01[3];
115	__le32                                   reserved04[3];
116	u8                                       num_image_references;
117	u8                                       release_level;
118	__le16                                   reserved12;
119	__le16                                   reserved14;
120	__le16                                   flags;
121	__le32                                   reserved18[2];
122	__le16                                   vendor_id;
123	__le16                                   device_id;
124	__le16                                   subsystem_vendor_id;
125	__le16                                   subsystem_id;
126	__le32                                   reserved28[2];
127	union mpi3_version_union                    package_security_version;
128	__le32                                   reserved34;
129	struct mpi3_comp_image_version               package_version;
130	__le32                                   package_version_string_offset;
131	__le32                                   package_build_date_string_offset;
132	__le32                                   package_build_time_string_offset;
133	__le32                                   reserved4c;
134	__le32                                   diag_authorization_identifier[16];
135	struct mpi3_ci_manifest_mpi_comp_image_ref   component_image_ref[MPI3_CI_MANIFEST_MPI_MAX];
136};
137
138#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DEV                        (0x00)
139#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PREALPHA                   (0x10)
140#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_ALPHA                      (0x20)
141#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_BETA                       (0x30)
142#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_RC                         (0x40)
143#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_GCA                        (0x50)
144#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_POINT                      (0x60)
145#define MPI3_CI_MANIFEST_MPI_FLAGS_DIAG_AUTHORIZATION                 (0x01)
146#define MPI3_CI_MANIFEST_MPI_SUBSYSTEMID_IGNORED                   (0xffff)
147#define MPI3_CI_MANIFEST_MPI_PKG_VER_STR_OFF_UNSPECIFIED           (0x00000000)
148#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_DATE_STR_OFF_UNSPECIFIED    (0x00000000)
149#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_TIME_STR_OFF_UNSPECIFIED    (0x00000000)
150union mpi3_ci_manifest {
151	struct mpi3_ci_manifest_mpi               mpi;
152	__le32                                dword[1];
153};
154
155#define MPI3_CI_MANIFEST_TYPE_MPI                                  (0x00)
156struct mpi3_extended_image_header {
157	u8                                image_type;
158	u8                                reserved01[3];
159	__le32                            checksum;
160	__le32                            image_size;
161	__le32                            next_image_header_offset;
162	__le32                            reserved10[4];
163	__le32                            identify_string[8];
164};
165
166#define MPI3_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
167#define MPI3_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
168#define MPI3_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0c)
169#define MPI3_EXT_IMAGE_HEADER_SIZE              (0x40)
170#define MPI3_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
171#define MPI3_EXT_IMAGE_TYPE_NVDATA                  (0x03)
172#define MPI3_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
173#define MPI3_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)
174#define MPI3_EXT_IMAGE_TYPE_RDE                     (0x0a)
175#define MPI3_EXT_IMAGE_TYPE_AUXILIARY_PROCESSOR     (0x0b)
176#define MPI3_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
177#define MPI3_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xff)
178struct mpi3_supported_device {
179	__le16                     device_id;
180	__le16                     vendor_id;
181	__le16                     device_id_mask;
182	__le16                     reserved06;
183	u8                         low_pci_rev;
184	u8                         high_pci_rev;
185	__le16                     reserved0a;
186	__le32                     reserved0c;
187};
188
189#ifndef MPI3_SUPPORTED_DEVICE_MAX
190#define MPI3_SUPPORTED_DEVICE_MAX                      (1)
191#endif
192struct mpi3_supported_devices_data {
193	u8                         image_version;
194	u8                         reserved01;
195	u8                         num_devices;
196	u8                         reserved03;
197	__le32                     reserved04;
198	struct mpi3_supported_device   supported_device[MPI3_SUPPORTED_DEVICE_MAX];
199};
200
201#ifndef MPI3_ENCRYPTED_HASH_MAX
202#define MPI3_ENCRYPTED_HASH_MAX                      (1)
203#endif
204struct mpi3_encrypted_hash_entry {
205	u8                         hash_image_type;
206	u8                         hash_algorithm;
207	u8                         encryption_algorithm;
208	u8                         reserved03;
209	__le32                     reserved04;
210	__le32                     encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];
211};
212
213#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE      (0x03)
214#define MPI3_HASH_ALGORITHM_VERSION_MASK             (0xe0)
215#define MPI3_HASH_ALGORITHM_VERSION_NONE             (0x00)
216#define MPI3_HASH_ALGORITHM_VERSION_SHA1             (0x20)
217#define MPI3_HASH_ALGORITHM_VERSION_SHA2             (0x40)
218#define MPI3_HASH_ALGORITHM_VERSION_SHA3             (0x60)
219#define MPI3_HASH_ALGORITHM_SIZE_MASK                (0x1f)
220#define MPI3_HASH_ALGORITHM_SIZE_UNUSED              (0x00)
221#define MPI3_HASH_ALGORITHM_SIZE_SHA256              (0x01)
222#define MPI3_HASH_ALGORITHM_SIZE_SHA512              (0x02)
223#define MPI3_HASH_ALGORITHM_SIZE_SHA384              (0x03)
224#define MPI3_ENCRYPTION_ALGORITHM_UNUSED             (0x00)
225#define MPI3_ENCRYPTION_ALGORITHM_RSA256             (0x01)
226#define MPI3_ENCRYPTION_ALGORITHM_RSA512             (0x02)
227#define MPI3_ENCRYPTION_ALGORITHM_RSA1024            (0x03)
228#define MPI3_ENCRYPTION_ALGORITHM_RSA2048            (0x04)
229#define MPI3_ENCRYPTION_ALGORITHM_RSA4096            (0x05)
230#define MPI3_ENCRYPTION_ALGORITHM_RSA3072            (0x06)
231#ifndef MPI3_PUBLIC_KEY_MAX
232#define MPI3_PUBLIC_KEY_MAX                          (1)
233#endif
234struct mpi3_encrypted_key_with_hash_entry {
235	u8                         hash_image_type;
236	u8                         hash_algorithm;
237	u8                         encryption_algorithm;
238	u8                         reserved03;
239	__le32                     reserved04;
240	__le32                     public_key[MPI3_PUBLIC_KEY_MAX];
241};
242
243#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
244#define MPI3_ENCRYPTED_HASH_ENTRY_MAX               (1)
245#endif
246struct mpi3_encrypted_hash_data {
247	u8                                  image_version;
248	u8                                  num_hash;
249	__le16                              reserved02;
250	__le32                              reserved04;
251	struct mpi3_encrypted_hash_entry        encrypted_hash_entry[MPI3_ENCRYPTED_HASH_ENTRY_MAX];
252};
253
254#ifndef MPI3_AUX_PROC_DATA_MAX
255#define MPI3_AUX_PROC_DATA_MAX               (1)
256#endif
257struct mpi3_aux_processor_data {
258	u8                         boot_method;
259	u8                         num_load_addr;
260	u8                         reserved02;
261	u8                         type;
262	__le32                     version;
263	__le32                     load_address[8];
264	__le32                     reserved28[22];
265	__le32                     aux_processor_data[MPI3_AUX_PROC_DATA_MAX];
266};
267
268#define MPI3_AUX_PROC_DATA_OFFSET                                     (0x80)
269#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_MSG                          (0x00)
270#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_DOORBELL                     (0x01)
271#define MPI3_AUXPROCESSOR_BOOT_METHOD_COMPONENT                       (0x02)
272#define MPI3_AUXPROCESSOR_TYPE_ARM_A15                                (0x00)
273#define MPI3_AUXPROCESSOR_TYPE_ARM_M0                                 (0x01)
274#define MPI3_AUXPROCESSOR_TYPE_ARM_R4                                 (0x02)
275#endif
276