1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time 4 * chips. 5 * 6 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>. 7 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>. 8 * 9 * References: 10 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. 11 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. 12 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. 13 * Application Note 90, Using the Multiplex Bus RTC Extended Features. 14 */ 15 16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18#include <linux/bcd.h> 19#include <linux/delay.h> 20#include <linux/io.h> 21#include <linux/module.h> 22#include <linux/platform_device.h> 23#include <linux/rtc.h> 24#include <linux/workqueue.h> 25 26#include <linux/rtc/ds1685.h> 27 28#ifdef CONFIG_PROC_FS 29#include <linux/proc_fs.h> 30#endif 31 32 33/* ----------------------------------------------------------------------- */ 34/* 35 * Standard read/write 36 * all registers are mapped in CPU address space 37 */ 38 39/** 40 * ds1685_read - read a value from an rtc register. 41 * @rtc: pointer to the ds1685 rtc structure. 42 * @reg: the register address to read. 43 */ 44static u8 45ds1685_read(struct ds1685_priv *rtc, int reg) 46{ 47 return readb((u8 __iomem *)rtc->regs + 48 (reg * rtc->regstep)); 49} 50 51/** 52 * ds1685_write - write a value to an rtc register. 53 * @rtc: pointer to the ds1685 rtc structure. 54 * @reg: the register address to write. 55 * @value: value to write to the register. 56 */ 57static void 58ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) 59{ 60 writeb(value, ((u8 __iomem *)rtc->regs + 61 (reg * rtc->regstep))); 62} 63/* ----------------------------------------------------------------------- */ 64 65/* 66 * Indirect read/write functions 67 * access happens via address and data register mapped in CPU address space 68 */ 69 70/** 71 * ds1685_indirect_read - read a value from an rtc register. 72 * @rtc: pointer to the ds1685 rtc structure. 73 * @reg: the register address to read. 74 */ 75static u8 76ds1685_indirect_read(struct ds1685_priv *rtc, int reg) 77{ 78 writeb(reg, rtc->regs); 79 return readb(rtc->data); 80} 81 82/** 83 * ds1685_indirect_write - write a value to an rtc register. 84 * @rtc: pointer to the ds1685 rtc structure. 85 * @reg: the register address to write. 86 * @value: value to write to the register. 87 */ 88static void 89ds1685_indirect_write(struct ds1685_priv *rtc, int reg, u8 value) 90{ 91 writeb(reg, rtc->regs); 92 writeb(value, rtc->data); 93} 94 95/* ----------------------------------------------------------------------- */ 96/* Inlined functions */ 97 98/** 99 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD. 100 * @rtc: pointer to the ds1685 rtc structure. 101 * @val: u8 time value to consider converting. 102 * @bcd_mask: u8 mask value if BCD mode is used. 103 * @bin_mask: u8 mask value if BIN mode is used. 104 * 105 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE. 106 */ 107static inline u8 108ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask) 109{ 110 if (rtc->bcd_mode) 111 return (bcd2bin(val) & bcd_mask); 112 113 return (val & bin_mask); 114} 115 116/** 117 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD. 118 * @rtc: pointer to the ds1685 rtc structure. 119 * @val: u8 time value to consider converting. 120 * @bin_mask: u8 mask value if BIN mode is used. 121 * @bcd_mask: u8 mask value if BCD mode is used. 122 * 123 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE. 124 */ 125static inline u8 126ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask) 127{ 128 if (rtc->bcd_mode) 129 return (bin2bcd(val) & bcd_mask); 130 131 return (val & bin_mask); 132} 133 134/** 135 * ds1685_rtc_check_mday - check validity of the day of month. 136 * @rtc: pointer to the ds1685 rtc structure. 137 * @mday: day of month. 138 * 139 * Returns -EDOM if the day of month is not within 1..31 range. 140 */ 141static inline int 142ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday) 143{ 144 if (rtc->bcd_mode) { 145 if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09) 146 return -EDOM; 147 } else { 148 if (mday < 1 || mday > 31) 149 return -EDOM; 150 } 151 return 0; 152} 153 154/** 155 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. 156 * @rtc: pointer to the ds1685 rtc structure. 157 */ 158static inline void 159ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) 160{ 161 rtc->write(rtc, RTC_CTRL_A, 162 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); 163} 164 165/** 166 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. 167 * @rtc: pointer to the ds1685 rtc structure. 168 */ 169static inline void 170ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) 171{ 172 rtc->write(rtc, RTC_CTRL_A, 173 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); 174} 175 176/** 177 * ds1685_rtc_begin_data_access - prepare the rtc for data access. 178 * @rtc: pointer to the ds1685 rtc structure. 179 * 180 * This takes several steps to prepare the rtc for access to get/set time 181 * and alarm values from the rtc registers: 182 * - Sets the SET bit in Control Register B. 183 * - Reads Ext Control Register 4A and checks the INCR bit. 184 * - If INCR is active, a short delay is added before Ext Control Register 4A 185 * is read again in a loop until INCR is inactive. 186 * - Switches the rtc to bank 1. This allows access to all relevant 187 * data for normal rtc operation, as bank 0 contains only the nvram. 188 */ 189static inline void 190ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) 191{ 192 /* Set the SET bit in Ctrl B */ 193 rtc->write(rtc, RTC_CTRL_B, 194 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); 195 196 /* Switch to Bank 1 */ 197 ds1685_rtc_switch_to_bank1(rtc); 198 199 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ 200 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) 201 cpu_relax(); 202} 203 204/** 205 * ds1685_rtc_end_data_access - end data access on the rtc. 206 * @rtc: pointer to the ds1685 rtc structure. 207 * 208 * This ends what was started by ds1685_rtc_begin_data_access: 209 * - Switches the rtc back to bank 0. 210 * - Clears the SET bit in Control Register B. 211 */ 212static inline void 213ds1685_rtc_end_data_access(struct ds1685_priv *rtc) 214{ 215 /* Switch back to Bank 0 */ 216 ds1685_rtc_switch_to_bank0(rtc); 217 218 /* Clear the SET bit in Ctrl B */ 219 rtc->write(rtc, RTC_CTRL_B, 220 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); 221} 222 223/** 224 * ds1685_rtc_get_ssn - retrieve the silicon serial number. 225 * @rtc: pointer to the ds1685 rtc structure. 226 * @ssn: u8 array to hold the bits of the silicon serial number. 227 * 228 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The 229 * first byte is the model number, the next six bytes are the serial number 230 * digits, and the final byte is a CRC check byte. Together, they form the 231 * silicon serial number. 232 * 233 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be 234 * called first before calling this function, else data will be read out of 235 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done. 236 */ 237static inline void 238ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) 239{ 240 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL); 241 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1); 242 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2); 243 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3); 244 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4); 245 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5); 246 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6); 247 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC); 248} 249/* ----------------------------------------------------------------------- */ 250 251 252/* ----------------------------------------------------------------------- */ 253/* Read/Set Time & Alarm functions */ 254 255/** 256 * ds1685_rtc_read_time - reads the time registers. 257 * @dev: pointer to device structure. 258 * @tm: pointer to rtc_time structure. 259 */ 260static int 261ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) 262{ 263 struct ds1685_priv *rtc = dev_get_drvdata(dev); 264 u8 century; 265 u8 seconds, minutes, hours, wday, mday, month, years; 266 267 /* Fetch the time info from the RTC registers. */ 268 ds1685_rtc_begin_data_access(rtc); 269 seconds = rtc->read(rtc, RTC_SECS); 270 minutes = rtc->read(rtc, RTC_MINS); 271 hours = rtc->read(rtc, RTC_HRS); 272 wday = rtc->read(rtc, RTC_WDAY); 273 mday = rtc->read(rtc, RTC_MDAY); 274 month = rtc->read(rtc, RTC_MONTH); 275 years = rtc->read(rtc, RTC_YEAR); 276 century = rtc->read(rtc, RTC_CENTURY); 277 ds1685_rtc_end_data_access(rtc); 278 279 /* bcd2bin if needed, perform fixups, and store to rtc_time. */ 280 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK, 281 RTC_YEAR_BIN_MASK); 282 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK, 283 RTC_CENTURY_MASK); 284 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK, 285 RTC_SECS_BIN_MASK); 286 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK, 287 RTC_MINS_BIN_MASK); 288 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK, 289 RTC_HRS_24_BIN_MASK); 290 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK, 291 RTC_WDAY_MASK) - 1); 292 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, 293 RTC_MDAY_BIN_MASK); 294 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK, 295 RTC_MONTH_BIN_MASK) - 1); 296 tm->tm_year = ((years + (century * 100)) - 1900); 297 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); 298 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ 299 300 return 0; 301} 302 303/** 304 * ds1685_rtc_set_time - sets the time registers. 305 * @dev: pointer to device structure. 306 * @tm: pointer to rtc_time structure. 307 */ 308static int 309ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) 310{ 311 struct ds1685_priv *rtc = dev_get_drvdata(dev); 312 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century; 313 314 /* Fetch the time info from rtc_time. */ 315 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK, 316 RTC_SECS_BCD_MASK); 317 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK, 318 RTC_MINS_BCD_MASK); 319 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK, 320 RTC_HRS_24_BCD_MASK); 321 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK, 322 RTC_WDAY_MASK); 323 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK, 324 RTC_MDAY_BCD_MASK); 325 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK, 326 RTC_MONTH_BCD_MASK); 327 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100), 328 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK); 329 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100), 330 RTC_CENTURY_MASK, RTC_CENTURY_MASK); 331 332 /* 333 * Perform Sanity Checks: 334 * - Months: !> 12, Month Day != 0. 335 * - Month Day !> Max days in current month. 336 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. 337 */ 338 if ((tm->tm_mon > 11) || (mday == 0)) 339 return -EDOM; 340 341 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) 342 return -EDOM; 343 344 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || 345 (tm->tm_sec >= 60) || (wday > 7)) 346 return -EDOM; 347 348 /* 349 * Set the data mode to use and store the time values in the 350 * RTC registers. 351 */ 352 ds1685_rtc_begin_data_access(rtc); 353 ctrlb = rtc->read(rtc, RTC_CTRL_B); 354 if (rtc->bcd_mode) 355 ctrlb &= ~(RTC_CTRL_B_DM); 356 else 357 ctrlb |= RTC_CTRL_B_DM; 358 rtc->write(rtc, RTC_CTRL_B, ctrlb); 359 rtc->write(rtc, RTC_SECS, seconds); 360 rtc->write(rtc, RTC_MINS, minutes); 361 rtc->write(rtc, RTC_HRS, hours); 362 rtc->write(rtc, RTC_WDAY, wday); 363 rtc->write(rtc, RTC_MDAY, mday); 364 rtc->write(rtc, RTC_MONTH, month); 365 rtc->write(rtc, RTC_YEAR, years); 366 rtc->write(rtc, RTC_CENTURY, century); 367 ds1685_rtc_end_data_access(rtc); 368 369 return 0; 370} 371 372/** 373 * ds1685_rtc_read_alarm - reads the alarm registers. 374 * @dev: pointer to device structure. 375 * @alrm: pointer to rtc_wkalrm structure. 376 * 377 * There are three primary alarm registers: seconds, minutes, and hours. 378 * A fourth alarm register for the month date is also available in bank1 for 379 * kickstart/wakeup features. The DS1685/DS1687 manual states that a 380 * "don't care" value ranging from 0xc0 to 0xff may be written into one or 381 * more of the three alarm bytes to act as a wildcard value. The fourth 382 * byte doesn't support a "don't care" value. 383 */ 384static int 385ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 386{ 387 struct ds1685_priv *rtc = dev_get_drvdata(dev); 388 u8 seconds, minutes, hours, mday, ctrlb, ctrlc; 389 int ret; 390 391 /* Fetch the alarm info from the RTC alarm registers. */ 392 ds1685_rtc_begin_data_access(rtc); 393 seconds = rtc->read(rtc, RTC_SECS_ALARM); 394 minutes = rtc->read(rtc, RTC_MINS_ALARM); 395 hours = rtc->read(rtc, RTC_HRS_ALARM); 396 mday = rtc->read(rtc, RTC_MDAY_ALARM); 397 ctrlb = rtc->read(rtc, RTC_CTRL_B); 398 ctrlc = rtc->read(rtc, RTC_CTRL_C); 399 ds1685_rtc_end_data_access(rtc); 400 401 /* Check the month date for validity. */ 402 ret = ds1685_rtc_check_mday(rtc, mday); 403 if (ret) 404 return ret; 405 406 /* 407 * Check the three alarm bytes. 408 * 409 * The Linux RTC system doesn't support the "don't care" capability 410 * of this RTC chip. We check for it anyways in case support is 411 * added in the future and only assign when we care. 412 */ 413 if (likely(seconds < 0xc0)) 414 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, 415 RTC_SECS_BCD_MASK, 416 RTC_SECS_BIN_MASK); 417 418 if (likely(minutes < 0xc0)) 419 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes, 420 RTC_MINS_BCD_MASK, 421 RTC_MINS_BIN_MASK); 422 423 if (likely(hours < 0xc0)) 424 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours, 425 RTC_HRS_24_BCD_MASK, 426 RTC_HRS_24_BIN_MASK); 427 428 /* Write the data to rtc_wkalrm. */ 429 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, 430 RTC_MDAY_BIN_MASK); 431 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); 432 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); 433 434 return 0; 435} 436 437/** 438 * ds1685_rtc_set_alarm - sets the alarm in registers. 439 * @dev: pointer to device structure. 440 * @alrm: pointer to rtc_wkalrm structure. 441 */ 442static int 443ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 444{ 445 struct ds1685_priv *rtc = dev_get_drvdata(dev); 446 u8 ctrlb, seconds, minutes, hours, mday; 447 int ret; 448 449 /* Fetch the alarm info and convert to BCD. */ 450 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec, 451 RTC_SECS_BIN_MASK, 452 RTC_SECS_BCD_MASK); 453 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min, 454 RTC_MINS_BIN_MASK, 455 RTC_MINS_BCD_MASK); 456 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour, 457 RTC_HRS_24_BIN_MASK, 458 RTC_HRS_24_BCD_MASK); 459 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday, 460 RTC_MDAY_BIN_MASK, 461 RTC_MDAY_BCD_MASK); 462 463 /* Check the month date for validity. */ 464 ret = ds1685_rtc_check_mday(rtc, mday); 465 if (ret) 466 return ret; 467 468 /* 469 * Check the three alarm bytes. 470 * 471 * The Linux RTC system doesn't support the "don't care" capability 472 * of this RTC chip because rtc_valid_tm tries to validate every 473 * field, and we only support four fields. We put the support 474 * here anyways for the future. 475 */ 476 if (unlikely(seconds >= 0xc0)) 477 seconds = 0xff; 478 479 if (unlikely(minutes >= 0xc0)) 480 minutes = 0xff; 481 482 if (unlikely(hours >= 0xc0)) 483 hours = 0xff; 484 485 alrm->time.tm_mon = -1; 486 alrm->time.tm_year = -1; 487 alrm->time.tm_wday = -1; 488 alrm->time.tm_yday = -1; 489 alrm->time.tm_isdst = -1; 490 491 /* Disable the alarm interrupt first. */ 492 ds1685_rtc_begin_data_access(rtc); 493 ctrlb = rtc->read(rtc, RTC_CTRL_B); 494 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); 495 496 /* Read ctrlc to clear RTC_CTRL_C_AF. */ 497 rtc->read(rtc, RTC_CTRL_C); 498 499 /* 500 * Set the data mode to use and store the time values in the 501 * RTC registers. 502 */ 503 ctrlb = rtc->read(rtc, RTC_CTRL_B); 504 if (rtc->bcd_mode) 505 ctrlb &= ~(RTC_CTRL_B_DM); 506 else 507 ctrlb |= RTC_CTRL_B_DM; 508 rtc->write(rtc, RTC_CTRL_B, ctrlb); 509 rtc->write(rtc, RTC_SECS_ALARM, seconds); 510 rtc->write(rtc, RTC_MINS_ALARM, minutes); 511 rtc->write(rtc, RTC_HRS_ALARM, hours); 512 rtc->write(rtc, RTC_MDAY_ALARM, mday); 513 514 /* Re-enable the alarm if needed. */ 515 if (alrm->enabled) { 516 ctrlb = rtc->read(rtc, RTC_CTRL_B); 517 ctrlb |= RTC_CTRL_B_AIE; 518 rtc->write(rtc, RTC_CTRL_B, ctrlb); 519 } 520 521 /* Done! */ 522 ds1685_rtc_end_data_access(rtc); 523 524 return 0; 525} 526/* ----------------------------------------------------------------------- */ 527 528 529/* ----------------------------------------------------------------------- */ 530/* /dev/rtcX Interface functions */ 531 532/** 533 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. 534 * @dev: pointer to device structure. 535 * @enabled: flag indicating whether to enable or disable. 536 */ 537static int 538ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 539{ 540 struct ds1685_priv *rtc = dev_get_drvdata(dev); 541 542 /* Flip the requisite interrupt-enable bit. */ 543 if (enabled) 544 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) | 545 RTC_CTRL_B_AIE)); 546 else 547 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) & 548 ~(RTC_CTRL_B_AIE))); 549 550 /* Read Control C to clear all the flag bits. */ 551 rtc->read(rtc, RTC_CTRL_C); 552 553 return 0; 554} 555/* ----------------------------------------------------------------------- */ 556 557 558/* ----------------------------------------------------------------------- */ 559/* IRQ handler */ 560 561/** 562 * ds1685_rtc_extended_irq - take care of extended interrupts 563 * @rtc: pointer to the ds1685 rtc structure. 564 * @pdev: platform device pointer. 565 */ 566static void 567ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev) 568{ 569 u8 ctrl4a, ctrl4b; 570 571 ds1685_rtc_switch_to_bank1(rtc); 572 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 573 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 574 575 /* 576 * Check for a kickstart interrupt. With Vcc applied, this 577 * typically means that the power button was pressed, so we 578 * begin the shutdown sequence. 579 */ 580 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) { 581 /* Briefly disable kickstarts to debounce button presses. */ 582 rtc->write(rtc, RTC_EXT_CTRL_4B, 583 (rtc->read(rtc, RTC_EXT_CTRL_4B) & 584 ~(RTC_CTRL_4B_KSE))); 585 586 /* Clear the kickstart flag. */ 587 rtc->write(rtc, RTC_EXT_CTRL_4A, 588 (ctrl4a & ~(RTC_CTRL_4A_KF))); 589 590 591 /* 592 * Sleep 500ms before re-enabling kickstarts. This allows 593 * adequate time to avoid reading signal jitter as additional 594 * button presses. 595 */ 596 msleep(500); 597 rtc->write(rtc, RTC_EXT_CTRL_4B, 598 (rtc->read(rtc, RTC_EXT_CTRL_4B) | 599 RTC_CTRL_4B_KSE)); 600 601 /* Call the platform pre-poweroff function. Else, shutdown. */ 602 if (rtc->prepare_poweroff != NULL) 603 rtc->prepare_poweroff(); 604 else 605 ds1685_rtc_poweroff(pdev); 606 } 607 608 /* 609 * Check for a wake-up interrupt. With Vcc applied, this is 610 * essentially a second alarm interrupt, except it takes into 611 * account the 'date' register in bank1 in addition to the 612 * standard three alarm registers. 613 */ 614 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) { 615 rtc->write(rtc, RTC_EXT_CTRL_4A, 616 (ctrl4a & ~(RTC_CTRL_4A_WF))); 617 618 /* Call the platform wake_alarm function if defined. */ 619 if (rtc->wake_alarm != NULL) 620 rtc->wake_alarm(); 621 else 622 dev_warn(&pdev->dev, 623 "Wake Alarm IRQ just occurred!\n"); 624 } 625 626 /* 627 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 628 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting 629 * each byte to a logic 1. This has no effect on any extended 630 * NV-SRAM that might be present, nor on the time/calendar/alarm 631 * registers. After a ram-clear is completed, there is a minimum 632 * recovery time of ~150ms in which all reads/writes are locked out. 633 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot 634 * catch this scenario. 635 */ 636 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) { 637 rtc->write(rtc, RTC_EXT_CTRL_4A, 638 (ctrl4a & ~(RTC_CTRL_4A_RF))); 639 msleep(150); 640 641 /* Call the platform post_ram_clear function if defined. */ 642 if (rtc->post_ram_clear != NULL) 643 rtc->post_ram_clear(); 644 else 645 dev_warn(&pdev->dev, 646 "RAM-Clear IRQ just occurred!\n"); 647 } 648 ds1685_rtc_switch_to_bank0(rtc); 649} 650 651/** 652 * ds1685_rtc_irq_handler - IRQ handler. 653 * @irq: IRQ number. 654 * @dev_id: platform device pointer. 655 */ 656static irqreturn_t 657ds1685_rtc_irq_handler(int irq, void *dev_id) 658{ 659 struct platform_device *pdev = dev_id; 660 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 661 u8 ctrlb, ctrlc; 662 unsigned long events = 0; 663 u8 num_irqs = 0; 664 665 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ 666 if (unlikely(!rtc)) 667 return IRQ_HANDLED; 668 669 rtc_lock(rtc->dev); 670 671 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ 672 ctrlb = rtc->read(rtc, RTC_CTRL_B); 673 ctrlc = rtc->read(rtc, RTC_CTRL_C); 674 675 /* Is the IRQF bit set? */ 676 if (likely(ctrlc & RTC_CTRL_C_IRQF)) { 677 /* 678 * We need to determine if it was one of the standard 679 * events: PF, AF, or UF. If so, we handle them and 680 * update the RTC core. 681 */ 682 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { 683 events = RTC_IRQF; 684 685 /* Check for a periodic interrupt. */ 686 if ((ctrlb & RTC_CTRL_B_PIE) && 687 (ctrlc & RTC_CTRL_C_PF)) { 688 events |= RTC_PF; 689 num_irqs++; 690 } 691 692 /* Check for an alarm interrupt. */ 693 if ((ctrlb & RTC_CTRL_B_AIE) && 694 (ctrlc & RTC_CTRL_C_AF)) { 695 events |= RTC_AF; 696 num_irqs++; 697 } 698 699 /* Check for an update interrupt. */ 700 if ((ctrlb & RTC_CTRL_B_UIE) && 701 (ctrlc & RTC_CTRL_C_UF)) { 702 events |= RTC_UF; 703 num_irqs++; 704 } 705 } else { 706 /* 707 * One of the "extended" interrupts was received that 708 * is not recognized by the RTC core. 709 */ 710 ds1685_rtc_extended_irq(rtc, pdev); 711 } 712 } 713 rtc_update_irq(rtc->dev, num_irqs, events); 714 rtc_unlock(rtc->dev); 715 716 return events ? IRQ_HANDLED : IRQ_NONE; 717} 718/* ----------------------------------------------------------------------- */ 719 720 721/* ----------------------------------------------------------------------- */ 722/* ProcFS interface */ 723 724#ifdef CONFIG_PROC_FS 725#define NUM_REGS 6 /* Num of control registers. */ 726#define NUM_BITS 8 /* Num bits per register. */ 727#define NUM_SPACES 4 /* Num spaces between each bit. */ 728 729/* 730 * Periodic Interrupt Rates. 731 */ 732static const char *ds1685_rtc_pirq_rate[16] = { 733 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", 734 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", 735 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" 736}; 737 738/* 739 * Square-Wave Output Frequencies. 740 */ 741static const char *ds1685_rtc_sqw_freq[16] = { 742 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz", 743 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz" 744}; 745 746/** 747 * ds1685_rtc_proc - procfs access function. 748 * @dev: pointer to device structure. 749 * @seq: pointer to seq_file structure. 750 */ 751static int 752ds1685_rtc_proc(struct device *dev, struct seq_file *seq) 753{ 754 struct ds1685_priv *rtc = dev_get_drvdata(dev); 755 u8 ctrla, ctrlb, ctrld, ctrl4a, ctrl4b, ssn[8]; 756 char *model; 757 758 /* Read all the relevant data from the control registers. */ 759 ds1685_rtc_switch_to_bank1(rtc); 760 ds1685_rtc_get_ssn(rtc, ssn); 761 ctrla = rtc->read(rtc, RTC_CTRL_A); 762 ctrlb = rtc->read(rtc, RTC_CTRL_B); 763 ctrld = rtc->read(rtc, RTC_CTRL_D); 764 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 765 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 766 ds1685_rtc_switch_to_bank0(rtc); 767 768 /* Determine the RTC model. */ 769 switch (ssn[0]) { 770 case RTC_MODEL_DS1685: 771 model = "DS1685/DS1687\0"; 772 break; 773 case RTC_MODEL_DS1689: 774 model = "DS1689/DS1693\0"; 775 break; 776 case RTC_MODEL_DS17285: 777 model = "DS17285/DS17287\0"; 778 break; 779 case RTC_MODEL_DS17485: 780 model = "DS17485/DS17487\0"; 781 break; 782 case RTC_MODEL_DS17885: 783 model = "DS17885/DS17887\0"; 784 break; 785 default: 786 model = "Unknown\0"; 787 break; 788 } 789 790 /* Print out the information. */ 791 seq_printf(seq, 792 "Model\t\t: %s\n" 793 "Oscillator\t: %s\n" 794 "12/24hr\t\t: %s\n" 795 "DST\t\t: %s\n" 796 "Data mode\t: %s\n" 797 "Battery\t\t: %s\n" 798 "Aux batt\t: %s\n" 799 "Update IRQ\t: %s\n" 800 "Periodic IRQ\t: %s\n" 801 "Periodic Rate\t: %s\n" 802 "SQW Freq\t: %s\n" 803 "Serial #\t: %8phC\n", 804 model, 805 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), 806 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), 807 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), 808 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), 809 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), 810 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), 811 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), 812 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), 813 (!(ctrl4b & RTC_CTRL_4B_E32K) ? 814 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), 815 (!((ctrl4b & RTC_CTRL_4B_E32K)) ? 816 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), 817 ssn); 818 return 0; 819} 820#else 821#define ds1685_rtc_proc NULL 822#endif /* CONFIG_PROC_FS */ 823/* ----------------------------------------------------------------------- */ 824 825 826/* ----------------------------------------------------------------------- */ 827/* RTC Class operations */ 828 829static const struct rtc_class_ops 830ds1685_rtc_ops = { 831 .proc = ds1685_rtc_proc, 832 .read_time = ds1685_rtc_read_time, 833 .set_time = ds1685_rtc_set_time, 834 .read_alarm = ds1685_rtc_read_alarm, 835 .set_alarm = ds1685_rtc_set_alarm, 836 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, 837}; 838/* ----------------------------------------------------------------------- */ 839 840static int ds1685_nvram_read(void *priv, unsigned int pos, void *val, 841 size_t size) 842{ 843 struct ds1685_priv *rtc = priv; 844 struct mutex *rtc_mutex = &rtc->dev->ops_lock; 845 ssize_t count; 846 u8 *buf = val; 847 int err; 848 849 err = mutex_lock_interruptible(rtc_mutex); 850 if (err) 851 return err; 852 853 ds1685_rtc_switch_to_bank0(rtc); 854 855 /* Read NVRAM in time and bank0 registers. */ 856 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; 857 count++, size--) { 858 if (count < NVRAM_SZ_TIME) 859 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++)); 860 else 861 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++)); 862 } 863 864#ifndef CONFIG_RTC_DRV_DS1689 865 if (size > 0) { 866 ds1685_rtc_switch_to_bank1(rtc); 867 868#ifndef CONFIG_RTC_DRV_DS1685 869 /* Enable burst-mode on DS17x85/DS17x87 */ 870 rtc->write(rtc, RTC_EXT_CTRL_4A, 871 (rtc->read(rtc, RTC_EXT_CTRL_4A) | 872 RTC_CTRL_4A_BME)); 873 874 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start 875 * reading with burst-mode */ 876 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, 877 (pos - NVRAM_TOTAL_SZ_BANK0)); 878#endif 879 880 /* Read NVRAM in bank1 registers. */ 881 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; 882 count++, size--) { 883#ifdef CONFIG_RTC_DRV_DS1685 884 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR 885 * before each read. */ 886 rtc->write(rtc, RTC_BANK1_RAM_ADDR, 887 (pos - NVRAM_TOTAL_SZ_BANK0)); 888#endif 889 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT); 890 pos++; 891 } 892 893#ifndef CONFIG_RTC_DRV_DS1685 894 /* Disable burst-mode on DS17x85/DS17x87 */ 895 rtc->write(rtc, RTC_EXT_CTRL_4A, 896 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 897 ~(RTC_CTRL_4A_BME))); 898#endif 899 ds1685_rtc_switch_to_bank0(rtc); 900 } 901#endif /* !CONFIG_RTC_DRV_DS1689 */ 902 mutex_unlock(rtc_mutex); 903 904 return 0; 905} 906 907static int ds1685_nvram_write(void *priv, unsigned int pos, void *val, 908 size_t size) 909{ 910 struct ds1685_priv *rtc = priv; 911 struct mutex *rtc_mutex = &rtc->dev->ops_lock; 912 ssize_t count; 913 u8 *buf = val; 914 int err; 915 916 err = mutex_lock_interruptible(rtc_mutex); 917 if (err) 918 return err; 919 920 ds1685_rtc_switch_to_bank0(rtc); 921 922 /* Write NVRAM in time and bank0 registers. */ 923 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; 924 count++, size--) 925 if (count < NVRAM_SZ_TIME) 926 rtc->write(rtc, (NVRAM_TIME_BASE + pos++), 927 *buf++); 928 else 929 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++); 930 931#ifndef CONFIG_RTC_DRV_DS1689 932 if (size > 0) { 933 ds1685_rtc_switch_to_bank1(rtc); 934 935#ifndef CONFIG_RTC_DRV_DS1685 936 /* Enable burst-mode on DS17x85/DS17x87 */ 937 rtc->write(rtc, RTC_EXT_CTRL_4A, 938 (rtc->read(rtc, RTC_EXT_CTRL_4A) | 939 RTC_CTRL_4A_BME)); 940 941 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start 942 * writing with burst-mode */ 943 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, 944 (pos - NVRAM_TOTAL_SZ_BANK0)); 945#endif 946 947 /* Write NVRAM in bank1 registers. */ 948 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; 949 count++, size--) { 950#ifdef CONFIG_RTC_DRV_DS1685 951 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR 952 * before each read. */ 953 rtc->write(rtc, RTC_BANK1_RAM_ADDR, 954 (pos - NVRAM_TOTAL_SZ_BANK0)); 955#endif 956 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); 957 pos++; 958 } 959 960#ifndef CONFIG_RTC_DRV_DS1685 961 /* Disable burst-mode on DS17x85/DS17x87 */ 962 rtc->write(rtc, RTC_EXT_CTRL_4A, 963 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 964 ~(RTC_CTRL_4A_BME))); 965#endif 966 ds1685_rtc_switch_to_bank0(rtc); 967 } 968#endif /* !CONFIG_RTC_DRV_DS1689 */ 969 mutex_unlock(rtc_mutex); 970 971 return 0; 972} 973 974/* ----------------------------------------------------------------------- */ 975/* SysFS interface */ 976 977/** 978 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. 979 * @dev: pointer to device structure. 980 * @attr: pointer to device_attribute structure. 981 * @buf: pointer to char array to hold the output. 982 */ 983static ssize_t 984ds1685_rtc_sysfs_battery_show(struct device *dev, 985 struct device_attribute *attr, char *buf) 986{ 987 struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); 988 u8 ctrld; 989 990 ctrld = rtc->read(rtc, RTC_CTRL_D); 991 992 return sprintf(buf, "%s\n", 993 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); 994} 995static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); 996 997/** 998 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. 999 * @dev: pointer to device structure. 1000 * @attr: pointer to device_attribute structure. 1001 * @buf: pointer to char array to hold the output. 1002 */ 1003static ssize_t 1004ds1685_rtc_sysfs_auxbatt_show(struct device *dev, 1005 struct device_attribute *attr, char *buf) 1006{ 1007 struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); 1008 u8 ctrl4a; 1009 1010 ds1685_rtc_switch_to_bank1(rtc); 1011 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 1012 ds1685_rtc_switch_to_bank0(rtc); 1013 1014 return sprintf(buf, "%s\n", 1015 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); 1016} 1017static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); 1018 1019/** 1020 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. 1021 * @dev: pointer to device structure. 1022 * @attr: pointer to device_attribute structure. 1023 * @buf: pointer to char array to hold the output. 1024 */ 1025static ssize_t 1026ds1685_rtc_sysfs_serial_show(struct device *dev, 1027 struct device_attribute *attr, char *buf) 1028{ 1029 struct ds1685_priv *rtc = dev_get_drvdata(dev->parent); 1030 u8 ssn[8]; 1031 1032 ds1685_rtc_switch_to_bank1(rtc); 1033 ds1685_rtc_get_ssn(rtc, ssn); 1034 ds1685_rtc_switch_to_bank0(rtc); 1035 1036 return sprintf(buf, "%8phC\n", ssn); 1037} 1038static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); 1039 1040/* 1041 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. 1042 */ 1043static struct attribute* 1044ds1685_rtc_sysfs_misc_attrs[] = { 1045 &dev_attr_battery.attr, 1046 &dev_attr_auxbatt.attr, 1047 &dev_attr_serial.attr, 1048 NULL, 1049}; 1050 1051/* 1052 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. 1053 */ 1054static const struct attribute_group 1055ds1685_rtc_sysfs_misc_grp = { 1056 .name = "misc", 1057 .attrs = ds1685_rtc_sysfs_misc_attrs, 1058}; 1059 1060/* ----------------------------------------------------------------------- */ 1061/* Driver Probe/Removal */ 1062 1063/** 1064 * ds1685_rtc_probe - initializes rtc driver. 1065 * @pdev: pointer to platform_device structure. 1066 */ 1067static int 1068ds1685_rtc_probe(struct platform_device *pdev) 1069{ 1070 struct rtc_device *rtc_dev; 1071 struct ds1685_priv *rtc; 1072 struct ds1685_rtc_platform_data *pdata; 1073 u8 ctrla, ctrlb, hours; 1074 unsigned char am_pm; 1075 int ret = 0; 1076 struct nvmem_config nvmem_cfg = { 1077 .name = "ds1685_nvram", 1078 .size = NVRAM_TOTAL_SZ, 1079 .reg_read = ds1685_nvram_read, 1080 .reg_write = ds1685_nvram_write, 1081 }; 1082 1083 /* Get the platform data. */ 1084 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; 1085 if (!pdata) 1086 return -ENODEV; 1087 1088 /* Allocate memory for the rtc device. */ 1089 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 1090 if (!rtc) 1091 return -ENOMEM; 1092 1093 /* Setup resources and access functions */ 1094 switch (pdata->access_type) { 1095 case ds1685_reg_direct: 1096 rtc->regs = devm_platform_ioremap_resource(pdev, 0); 1097 if (IS_ERR(rtc->regs)) 1098 return PTR_ERR(rtc->regs); 1099 rtc->read = ds1685_read; 1100 rtc->write = ds1685_write; 1101 break; 1102 case ds1685_reg_indirect: 1103 rtc->regs = devm_platform_ioremap_resource(pdev, 0); 1104 if (IS_ERR(rtc->regs)) 1105 return PTR_ERR(rtc->regs); 1106 rtc->data = devm_platform_ioremap_resource(pdev, 1); 1107 if (IS_ERR(rtc->data)) 1108 return PTR_ERR(rtc->data); 1109 rtc->read = ds1685_indirect_read; 1110 rtc->write = ds1685_indirect_write; 1111 break; 1112 } 1113 1114 if (!rtc->read || !rtc->write) 1115 return -ENXIO; 1116 1117 /* Get the register step size. */ 1118 if (pdata->regstep > 0) 1119 rtc->regstep = pdata->regstep; 1120 else 1121 rtc->regstep = 1; 1122 1123 /* Platform pre-shutdown function, if defined. */ 1124 if (pdata->plat_prepare_poweroff) 1125 rtc->prepare_poweroff = pdata->plat_prepare_poweroff; 1126 1127 /* Platform wake_alarm function, if defined. */ 1128 if (pdata->plat_wake_alarm) 1129 rtc->wake_alarm = pdata->plat_wake_alarm; 1130 1131 /* Platform post_ram_clear function, if defined. */ 1132 if (pdata->plat_post_ram_clear) 1133 rtc->post_ram_clear = pdata->plat_post_ram_clear; 1134 1135 /* set the driver data. */ 1136 platform_set_drvdata(pdev, rtc); 1137 1138 /* Turn the oscillator on if is not already on (DV1 = 1). */ 1139 ctrla = rtc->read(rtc, RTC_CTRL_A); 1140 if (!(ctrla & RTC_CTRL_A_DV1)) 1141 ctrla |= RTC_CTRL_A_DV1; 1142 1143 /* Enable the countdown chain (DV2 = 0) */ 1144 ctrla &= ~(RTC_CTRL_A_DV2); 1145 1146 /* Clear RS3-RS0 in Control A. */ 1147 ctrla &= ~(RTC_CTRL_A_RS_MASK); 1148 1149 /* 1150 * All done with Control A. Switch to Bank 1 for the remainder of 1151 * the RTC setup so we have access to the extended functions. 1152 */ 1153 ctrla |= RTC_CTRL_A_DV0; 1154 rtc->write(rtc, RTC_CTRL_A, ctrla); 1155 1156 /* Default to 32768kHz output. */ 1157 rtc->write(rtc, RTC_EXT_CTRL_4B, 1158 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); 1159 1160 /* Set the SET bit in Control B so we can do some housekeeping. */ 1161 rtc->write(rtc, RTC_CTRL_B, 1162 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); 1163 1164 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ 1165 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) 1166 cpu_relax(); 1167 1168 /* 1169 * If the platform supports BCD mode, then set DM=0 in Control B. 1170 * Otherwise, set DM=1 for BIN mode. 1171 */ 1172 ctrlb = rtc->read(rtc, RTC_CTRL_B); 1173 if (pdata->bcd_mode) 1174 ctrlb &= ~(RTC_CTRL_B_DM); 1175 else 1176 ctrlb |= RTC_CTRL_B_DM; 1177 rtc->bcd_mode = pdata->bcd_mode; 1178 1179 /* 1180 * Disable Daylight Savings Time (DSE = 0). 1181 * The RTC has hardcoded timezone information that is rendered 1182 * obselete. We'll let the OS deal with DST settings instead. 1183 */ 1184 if (ctrlb & RTC_CTRL_B_DSE) 1185 ctrlb &= ~(RTC_CTRL_B_DSE); 1186 1187 /* Force 24-hour mode (2412 = 1). */ 1188 if (!(ctrlb & RTC_CTRL_B_2412)) { 1189 /* Reinitialize the time hours. */ 1190 hours = rtc->read(rtc, RTC_HRS); 1191 am_pm = hours & RTC_HRS_AMPM_MASK; 1192 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, 1193 RTC_HRS_12_BIN_MASK); 1194 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); 1195 1196 /* Enable 24-hour mode. */ 1197 ctrlb |= RTC_CTRL_B_2412; 1198 1199 /* Write back to Control B, including DM & DSE bits. */ 1200 rtc->write(rtc, RTC_CTRL_B, ctrlb); 1201 1202 /* Write the time hours back. */ 1203 rtc->write(rtc, RTC_HRS, 1204 ds1685_rtc_bin2bcd(rtc, hours, 1205 RTC_HRS_24_BIN_MASK, 1206 RTC_HRS_24_BCD_MASK)); 1207 1208 /* Reinitialize the alarm hours. */ 1209 hours = rtc->read(rtc, RTC_HRS_ALARM); 1210 am_pm = hours & RTC_HRS_AMPM_MASK; 1211 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, 1212 RTC_HRS_12_BIN_MASK); 1213 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); 1214 1215 /* Write the alarm hours back. */ 1216 rtc->write(rtc, RTC_HRS_ALARM, 1217 ds1685_rtc_bin2bcd(rtc, hours, 1218 RTC_HRS_24_BIN_MASK, 1219 RTC_HRS_24_BCD_MASK)); 1220 } else { 1221 /* 24-hour mode is already set, so write Control B back. */ 1222 rtc->write(rtc, RTC_CTRL_B, ctrlb); 1223 } 1224 1225 /* Unset the SET bit in Control B so the RTC can update. */ 1226 rtc->write(rtc, RTC_CTRL_B, 1227 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); 1228 1229 /* Check the main battery. */ 1230 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) 1231 dev_warn(&pdev->dev, 1232 "Main battery is exhausted! RTC may be invalid!\n"); 1233 1234 /* Check the auxillary battery. It is optional. */ 1235 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) 1236 dev_warn(&pdev->dev, 1237 "Aux battery is exhausted or not available.\n"); 1238 1239 /* Read Ctrl B and clear PIE/AIE/UIE. */ 1240 rtc->write(rtc, RTC_CTRL_B, 1241 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK))); 1242 1243 /* Reading Ctrl C auto-clears PF/AF/UF. */ 1244 rtc->read(rtc, RTC_CTRL_C); 1245 1246 /* Read Ctrl 4B and clear RIE/WIE/KSE. */ 1247 rtc->write(rtc, RTC_EXT_CTRL_4B, 1248 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK))); 1249 1250 /* Clear RF/WF/KF in Ctrl 4A. */ 1251 rtc->write(rtc, RTC_EXT_CTRL_4A, 1252 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK))); 1253 1254 /* 1255 * Re-enable KSE to handle power button events. We do not enable 1256 * WIE or RIE by default. 1257 */ 1258 rtc->write(rtc, RTC_EXT_CTRL_4B, 1259 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE)); 1260 1261 rtc_dev = devm_rtc_allocate_device(&pdev->dev); 1262 if (IS_ERR(rtc_dev)) 1263 return PTR_ERR(rtc_dev); 1264 1265 rtc_dev->ops = &ds1685_rtc_ops; 1266 1267 /* Century bit is useless because leap year fails in 1900 and 2100 */ 1268 rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000; 1269 rtc_dev->range_max = RTC_TIMESTAMP_END_2099; 1270 1271 /* Maximum periodic rate is 8192Hz (0.122070ms). */ 1272 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; 1273 1274 /* See if the platform doesn't support UIE. */ 1275 if (pdata->uie_unsupported) 1276 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc_dev->features); 1277 1278 rtc->dev = rtc_dev; 1279 1280 /* 1281 * Fetch the IRQ and setup the interrupt handler. 1282 * 1283 * Not all platforms have the IRQF pin tied to something. If not, the 1284 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but 1285 * there won't be an automatic way of notifying the kernel about it, 1286 * unless ctrlc is explicitly polled. 1287 */ 1288 rtc->irq_num = platform_get_irq(pdev, 0); 1289 if (rtc->irq_num <= 0) { 1290 clear_bit(RTC_FEATURE_ALARM, rtc_dev->features); 1291 } else { 1292 /* Request an IRQ. */ 1293 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num, 1294 NULL, ds1685_rtc_irq_handler, 1295 IRQF_SHARED | IRQF_ONESHOT, 1296 pdev->name, pdev); 1297 1298 /* Check to see if something came back. */ 1299 if (unlikely(ret)) { 1300 dev_warn(&pdev->dev, 1301 "RTC interrupt not available\n"); 1302 rtc->irq_num = 0; 1303 } 1304 } 1305 1306 /* Setup complete. */ 1307 ds1685_rtc_switch_to_bank0(rtc); 1308 1309 ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp); 1310 if (ret) 1311 return ret; 1312 1313 nvmem_cfg.priv = rtc; 1314 ret = devm_rtc_nvmem_register(rtc_dev, &nvmem_cfg); 1315 if (ret) 1316 return ret; 1317 1318 return devm_rtc_register_device(rtc_dev); 1319} 1320 1321/** 1322 * ds1685_rtc_remove - removes rtc driver. 1323 * @pdev: pointer to platform_device structure. 1324 */ 1325static void 1326ds1685_rtc_remove(struct platform_device *pdev) 1327{ 1328 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 1329 1330 /* Read Ctrl B and clear PIE/AIE/UIE. */ 1331 rtc->write(rtc, RTC_CTRL_B, 1332 (rtc->read(rtc, RTC_CTRL_B) & 1333 ~(RTC_CTRL_B_PAU_MASK))); 1334 1335 /* Reading Ctrl C auto-clears PF/AF/UF. */ 1336 rtc->read(rtc, RTC_CTRL_C); 1337 1338 /* Read Ctrl 4B and clear RIE/WIE/KSE. */ 1339 rtc->write(rtc, RTC_EXT_CTRL_4B, 1340 (rtc->read(rtc, RTC_EXT_CTRL_4B) & 1341 ~(RTC_CTRL_4B_RWK_MASK))); 1342 1343 /* Manually clear RF/WF/KF in Ctrl 4A. */ 1344 rtc->write(rtc, RTC_EXT_CTRL_4A, 1345 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 1346 ~(RTC_CTRL_4A_RWK_MASK))); 1347} 1348 1349/* 1350 * ds1685_rtc_driver - rtc driver properties. 1351 */ 1352static struct platform_driver ds1685_rtc_driver = { 1353 .driver = { 1354 .name = "rtc-ds1685", 1355 }, 1356 .probe = ds1685_rtc_probe, 1357 .remove_new = ds1685_rtc_remove, 1358}; 1359module_platform_driver(ds1685_rtc_driver); 1360/* ----------------------------------------------------------------------- */ 1361 1362 1363/* ----------------------------------------------------------------------- */ 1364/* Poweroff function */ 1365 1366/** 1367 * ds1685_rtc_poweroff - uses the RTC chip to power the system off. 1368 * @pdev: pointer to platform_device structure. 1369 */ 1370void __noreturn 1371ds1685_rtc_poweroff(struct platform_device *pdev) 1372{ 1373 u8 ctrla, ctrl4a, ctrl4b; 1374 struct ds1685_priv *rtc; 1375 1376 /* Check for valid RTC data, else, spin forever. */ 1377 if (unlikely(!pdev)) { 1378 pr_emerg("platform device data not available, spinning forever ...\n"); 1379 while(1); 1380 unreachable(); 1381 } else { 1382 /* Get the rtc data. */ 1383 rtc = platform_get_drvdata(pdev); 1384 1385 /* 1386 * Disable our IRQ. We're powering down, so we're not 1387 * going to worry about cleaning up. Most of that should 1388 * have been taken care of by the shutdown scripts and this 1389 * is the final function call. 1390 */ 1391 if (rtc->irq_num) 1392 disable_irq_nosync(rtc->irq_num); 1393 1394 /* Oscillator must be on and the countdown chain enabled. */ 1395 ctrla = rtc->read(rtc, RTC_CTRL_A); 1396 ctrla |= RTC_CTRL_A_DV1; 1397 ctrla &= ~(RTC_CTRL_A_DV2); 1398 rtc->write(rtc, RTC_CTRL_A, ctrla); 1399 1400 /* 1401 * Read Control 4A and check the status of the auxillary 1402 * battery. This must be present and working (VRT2 = 1) 1403 * for wakeup and kickstart functionality to be useful. 1404 */ 1405 ds1685_rtc_switch_to_bank1(rtc); 1406 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 1407 if (ctrl4a & RTC_CTRL_4A_VRT2) { 1408 /* Clear all of the interrupt flags on Control 4A. */ 1409 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); 1410 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a); 1411 1412 /* 1413 * The auxillary battery is present and working. 1414 * Enable extended functions (ABE=1), enable 1415 * wake-up (WIE=1), and enable kickstart (KSE=1) 1416 * in Control 4B. 1417 */ 1418 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 1419 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | 1420 RTC_CTRL_4B_KSE); 1421 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b); 1422 } 1423 1424 /* Set PAB to 1 in Control 4A to power the system down. */ 1425 dev_warn(&pdev->dev, "Powerdown.\n"); 1426 msleep(20); 1427 rtc->write(rtc, RTC_EXT_CTRL_4A, 1428 (ctrl4a | RTC_CTRL_4A_PAB)); 1429 1430 /* Spin ... we do not switch back to bank0. */ 1431 while(1); 1432 unreachable(); 1433 } 1434} 1435EXPORT_SYMBOL_GPL(ds1685_rtc_poweroff); 1436/* ----------------------------------------------------------------------- */ 1437 1438 1439MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>"); 1440MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>"); 1441MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); 1442MODULE_LICENSE("GPL"); 1443MODULE_ALIAS("platform:rtc-ds1685"); 1444