1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * RTC driver for the Armada 38x Marvell SoCs 4 * 5 * Copyright (C) 2015 Marvell 6 * 7 * Gregory Clement <gregory.clement@free-electrons.com> 8 */ 9 10#include <linux/delay.h> 11#include <linux/io.h> 12#include <linux/module.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/rtc.h> 16 17#define RTC_STATUS 0x0 18#define RTC_STATUS_ALARM1 BIT(0) 19#define RTC_STATUS_ALARM2 BIT(1) 20#define RTC_IRQ1_CONF 0x4 21#define RTC_IRQ2_CONF 0x8 22#define RTC_IRQ_AL_EN BIT(0) 23#define RTC_IRQ_FREQ_EN BIT(1) 24#define RTC_IRQ_FREQ_1HZ BIT(2) 25#define RTC_CCR 0x18 26#define RTC_CCR_MODE BIT(15) 27#define RTC_CONF_TEST 0x1C 28#define RTC_NOMINAL_TIMING BIT(13) 29 30#define RTC_TIME 0xC 31#define RTC_ALARM1 0x10 32#define RTC_ALARM2 0x14 33 34/* Armada38x SoC registers */ 35#define RTC_38X_BRIDGE_TIMING_CTL 0x0 36#define RTC_38X_PERIOD_OFFS 0 37#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS) 38#define RTC_38X_READ_DELAY_OFFS 26 39#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS) 40 41/* Armada 7K/8K registers */ 42#define RTC_8K_BRIDGE_TIMING_CTL0 0x0 43#define RTC_8K_WRCLK_PERIOD_OFFS 0 44#define RTC_8K_WRCLK_PERIOD_MASK (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS) 45#define RTC_8K_WRCLK_SETUP_OFFS 16 46#define RTC_8K_WRCLK_SETUP_MASK (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS) 47#define RTC_8K_BRIDGE_TIMING_CTL1 0x4 48#define RTC_8K_READ_DELAY_OFFS 0 49#define RTC_8K_READ_DELAY_MASK (0xFFFF << RTC_8K_READ_DELAY_OFFS) 50 51#define RTC_8K_ISR 0x10 52#define RTC_8K_IMR 0x14 53#define RTC_8K_ALARM2 BIT(0) 54 55#define SOC_RTC_INTERRUPT 0x8 56#define SOC_RTC_ALARM1 BIT(0) 57#define SOC_RTC_ALARM2 BIT(1) 58#define SOC_RTC_ALARM1_MASK BIT(2) 59#define SOC_RTC_ALARM2_MASK BIT(3) 60 61#define SAMPLE_NR 100 62 63struct value_to_freq { 64 u32 value; 65 u8 freq; 66}; 67 68struct armada38x_rtc { 69 struct rtc_device *rtc_dev; 70 void __iomem *regs; 71 void __iomem *regs_soc; 72 spinlock_t lock; 73 int irq; 74 bool initialized; 75 struct value_to_freq *val_to_freq; 76 const struct armada38x_rtc_data *data; 77}; 78 79#define ALARM1 0 80#define ALARM2 1 81 82#define ALARM_REG(base, alarm) ((base) + (alarm) * sizeof(u32)) 83 84struct armada38x_rtc_data { 85 /* Initialize the RTC-MBUS bridge timing */ 86 void (*update_mbus_timing)(struct armada38x_rtc *rtc); 87 u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg); 88 void (*clear_isr)(struct armada38x_rtc *rtc); 89 void (*unmask_interrupt)(struct armada38x_rtc *rtc); 90 u32 alarm; 91}; 92 93/* 94 * According to the datasheet, the OS should wait 5us after every 95 * register write to the RTC hard macro so that the required update 96 * can occur without holding off the system bus 97 * According to errata RES-3124064, Write to any RTC register 98 * may fail. As a workaround, before writing to RTC 99 * register, issue a dummy write of 0x0 twice to RTC Status 100 * register. 101 */ 102 103static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) 104{ 105 writel(0, rtc->regs + RTC_STATUS); 106 writel(0, rtc->regs + RTC_STATUS); 107 writel(val, rtc->regs + offset); 108 udelay(5); 109} 110 111/* Update RTC-MBUS bridge timing parameters */ 112static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc) 113{ 114 u32 reg; 115 116 reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); 117 reg &= ~RTC_38X_PERIOD_MASK; 118 reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */ 119 reg &= ~RTC_38X_READ_DELAY_MASK; 120 reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */ 121 writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); 122} 123 124static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc) 125{ 126 u32 reg; 127 128 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); 129 reg &= ~RTC_8K_WRCLK_PERIOD_MASK; 130 reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS; 131 reg &= ~RTC_8K_WRCLK_SETUP_MASK; 132 reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS; 133 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); 134 135 reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); 136 reg &= ~RTC_8K_READ_DELAY_MASK; 137 reg |= 0x3F << RTC_8K_READ_DELAY_OFFS; 138 writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); 139} 140 141static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg) 142{ 143 return readl(rtc->regs + rtc_reg); 144} 145 146static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg) 147{ 148 int i, index_max = 0, max = 0; 149 150 for (i = 0; i < SAMPLE_NR; i++) { 151 rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg); 152 rtc->val_to_freq[i].freq = 0; 153 } 154 155 for (i = 0; i < SAMPLE_NR; i++) { 156 int j = 0; 157 u32 value = rtc->val_to_freq[i].value; 158 159 while (rtc->val_to_freq[j].freq) { 160 if (rtc->val_to_freq[j].value == value) { 161 rtc->val_to_freq[j].freq++; 162 break; 163 } 164 j++; 165 } 166 167 if (!rtc->val_to_freq[j].freq) { 168 rtc->val_to_freq[j].value = value; 169 rtc->val_to_freq[j].freq = 1; 170 } 171 172 if (rtc->val_to_freq[j].freq > max) { 173 index_max = j; 174 max = rtc->val_to_freq[j].freq; 175 } 176 177 /* 178 * If a value already has half of the sample this is the most 179 * frequent one and we can stop the research right now 180 */ 181 if (max > SAMPLE_NR / 2) 182 break; 183 } 184 185 return rtc->val_to_freq[index_max].value; 186} 187 188static void armada38x_clear_isr(struct armada38x_rtc *rtc) 189{ 190 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); 191 192 writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT); 193} 194 195static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc) 196{ 197 u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); 198 199 writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT); 200} 201 202static void armada8k_clear_isr(struct armada38x_rtc *rtc) 203{ 204 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR); 205} 206 207static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc) 208{ 209 writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR); 210} 211 212static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm) 213{ 214 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 215 unsigned long time, flags; 216 217 spin_lock_irqsave(&rtc->lock, flags); 218 time = rtc->data->read_rtc_reg(rtc, RTC_TIME); 219 spin_unlock_irqrestore(&rtc->lock, flags); 220 221 rtc_time64_to_tm(time, tm); 222 223 return 0; 224} 225 226static void armada38x_rtc_reset(struct armada38x_rtc *rtc) 227{ 228 u32 reg; 229 230 reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST); 231 /* If bits [7:0] are non-zero, assume RTC was uninitialized */ 232 if (reg & 0xff) { 233 rtc_delayed_write(0, rtc, RTC_CONF_TEST); 234 msleep(500); /* Oscillator startup time */ 235 rtc_delayed_write(0, rtc, RTC_TIME); 236 rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc, 237 RTC_STATUS); 238 rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR); 239 } 240 rtc->initialized = true; 241} 242 243static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm) 244{ 245 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 246 unsigned long time, flags; 247 248 time = rtc_tm_to_time64(tm); 249 250 if (!rtc->initialized) 251 armada38x_rtc_reset(rtc); 252 253 spin_lock_irqsave(&rtc->lock, flags); 254 rtc_delayed_write(time, rtc, RTC_TIME); 255 spin_unlock_irqrestore(&rtc->lock, flags); 256 257 return 0; 258} 259 260static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 261{ 262 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 263 unsigned long time, flags; 264 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); 265 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 266 u32 val; 267 268 spin_lock_irqsave(&rtc->lock, flags); 269 270 time = rtc->data->read_rtc_reg(rtc, reg); 271 val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN; 272 273 spin_unlock_irqrestore(&rtc->lock, flags); 274 275 alrm->enabled = val ? 1 : 0; 276 rtc_time64_to_tm(time, &alrm->time); 277 278 return 0; 279} 280 281static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 282{ 283 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 284 u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); 285 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 286 unsigned long time, flags; 287 288 time = rtc_tm_to_time64(&alrm->time); 289 290 spin_lock_irqsave(&rtc->lock, flags); 291 292 rtc_delayed_write(time, rtc, reg); 293 294 if (alrm->enabled) { 295 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq); 296 rtc->data->unmask_interrupt(rtc); 297 } 298 299 spin_unlock_irqrestore(&rtc->lock, flags); 300 301 return 0; 302} 303 304static int armada38x_rtc_alarm_irq_enable(struct device *dev, 305 unsigned int enabled) 306{ 307 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 308 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 309 unsigned long flags; 310 311 spin_lock_irqsave(&rtc->lock, flags); 312 313 if (enabled) 314 rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq); 315 else 316 rtc_delayed_write(0, rtc, reg_irq); 317 318 spin_unlock_irqrestore(&rtc->lock, flags); 319 320 return 0; 321} 322 323static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data) 324{ 325 struct armada38x_rtc *rtc = data; 326 u32 val; 327 int event = RTC_IRQF | RTC_AF; 328 u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm); 329 330 dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq); 331 332 spin_lock(&rtc->lock); 333 334 rtc->data->clear_isr(rtc); 335 val = rtc->data->read_rtc_reg(rtc, reg_irq); 336 /* disable all the interrupts for alarm*/ 337 rtc_delayed_write(0, rtc, reg_irq); 338 /* Ack the event */ 339 rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS); 340 341 spin_unlock(&rtc->lock); 342 343 if (val & RTC_IRQ_FREQ_EN) { 344 if (val & RTC_IRQ_FREQ_1HZ) 345 event |= RTC_UF; 346 else 347 event |= RTC_PF; 348 } 349 350 rtc_update_irq(rtc->rtc_dev, 1, event); 351 352 return IRQ_HANDLED; 353} 354 355/* 356 * The information given in the Armada 388 functional spec is complex. 357 * They give two different formulas for calculating the offset value, 358 * but when considering "Offset" as an 8-bit signed integer, they both 359 * reduce down to (we shall rename "Offset" as "val" here): 360 * 361 * val = (f_ideal / f_measured - 1) / resolution where f_ideal = 32768 362 * 363 * Converting to time, f = 1/t: 364 * val = (t_measured / t_ideal - 1) / resolution where t_ideal = 1/32768 365 * 366 * => t_measured / t_ideal = val * resolution + 1 367 * 368 * "offset" in the RTC interface is defined as: 369 * t = t0 * (1 + offset * 1e-9) 370 * where t is the desired period, t0 is the measured period with a zero 371 * offset, which is t_measured above. With t0 = t_measured and t = t_ideal, 372 * offset = (t_ideal / t_measured - 1) / 1e-9 373 * 374 * => t_ideal / t_measured = offset * 1e-9 + 1 375 * 376 * so: 377 * 378 * offset * 1e-9 + 1 = 1 / (val * resolution + 1) 379 * 380 * We want "resolution" to be an integer, so resolution = R * 1e-9, giving 381 * offset = 1e18 / (val * R + 1e9) - 1e9 382 * val = (1e18 / (offset + 1e9) - 1e9) / R 383 * with a common transformation: 384 * f(x) = 1e18 / (x + 1e9) - 1e9 385 * offset = f(val * R) 386 * val = f(offset) / R 387 * 388 * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb). 389 */ 390static long armada38x_ppb_convert(long ppb) 391{ 392 long div = ppb + 1000000000L; 393 394 return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L; 395} 396 397static int armada38x_rtc_read_offset(struct device *dev, long *offset) 398{ 399 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 400 unsigned long ccr, flags; 401 long ppb_cor; 402 403 spin_lock_irqsave(&rtc->lock, flags); 404 ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR); 405 spin_unlock_irqrestore(&rtc->lock, flags); 406 407 ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr; 408 /* ppb_cor + 1000000000L can never be zero */ 409 *offset = armada38x_ppb_convert(ppb_cor); 410 411 return 0; 412} 413 414static int armada38x_rtc_set_offset(struct device *dev, long offset) 415{ 416 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 417 unsigned long ccr = 0; 418 long ppb_cor, off; 419 420 /* 421 * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we 422 * need to clamp the input. This equates to -484270 .. 488558. 423 * Not only is this to stop out of range "off" but also to 424 * avoid the division by zero in armada38x_ppb_convert(). 425 */ 426 offset = clamp(offset, -484270L, 488558L); 427 428 ppb_cor = armada38x_ppb_convert(offset); 429 430 /* 431 * Use low update mode where possible, which gives a better 432 * resolution of correction. 433 */ 434 off = DIV_ROUND_CLOSEST(ppb_cor, 954); 435 if (off > 127 || off < -128) { 436 ccr = RTC_CCR_MODE; 437 off = DIV_ROUND_CLOSEST(ppb_cor, 3815); 438 } 439 440 /* 441 * Armada 388 requires a bit pattern in bits 14..8 depending on 442 * the sign bit: { 0, ~S, S, S, S, S, S } 443 */ 444 ccr |= (off & 0x3fff) ^ 0x2000; 445 rtc_delayed_write(ccr, rtc, RTC_CCR); 446 447 return 0; 448} 449 450static const struct rtc_class_ops armada38x_rtc_ops = { 451 .read_time = armada38x_rtc_read_time, 452 .set_time = armada38x_rtc_set_time, 453 .read_alarm = armada38x_rtc_read_alarm, 454 .set_alarm = armada38x_rtc_set_alarm, 455 .alarm_irq_enable = armada38x_rtc_alarm_irq_enable, 456 .read_offset = armada38x_rtc_read_offset, 457 .set_offset = armada38x_rtc_set_offset, 458}; 459 460static const struct armada38x_rtc_data armada38x_data = { 461 .update_mbus_timing = rtc_update_38x_mbus_timing_params, 462 .read_rtc_reg = read_rtc_register_38x_wa, 463 .clear_isr = armada38x_clear_isr, 464 .unmask_interrupt = armada38x_unmask_interrupt, 465 .alarm = ALARM1, 466}; 467 468static const struct armada38x_rtc_data armada8k_data = { 469 .update_mbus_timing = rtc_update_8k_mbus_timing_params, 470 .read_rtc_reg = read_rtc_register, 471 .clear_isr = armada8k_clear_isr, 472 .unmask_interrupt = armada8k_unmask_interrupt, 473 .alarm = ALARM2, 474}; 475 476static const struct of_device_id armada38x_rtc_of_match_table[] = { 477 { 478 .compatible = "marvell,armada-380-rtc", 479 .data = &armada38x_data, 480 }, 481 { 482 .compatible = "marvell,armada-8k-rtc", 483 .data = &armada8k_data, 484 }, 485 {} 486}; 487MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table); 488 489static __init int armada38x_rtc_probe(struct platform_device *pdev) 490{ 491 struct armada38x_rtc *rtc; 492 493 rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc), 494 GFP_KERNEL); 495 if (!rtc) 496 return -ENOMEM; 497 498 rtc->data = of_device_get_match_data(&pdev->dev); 499 500 rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR, 501 sizeof(struct value_to_freq), GFP_KERNEL); 502 if (!rtc->val_to_freq) 503 return -ENOMEM; 504 505 spin_lock_init(&rtc->lock); 506 507 rtc->regs = devm_platform_ioremap_resource_byname(pdev, "rtc"); 508 if (IS_ERR(rtc->regs)) 509 return PTR_ERR(rtc->regs); 510 rtc->regs_soc = devm_platform_ioremap_resource_byname(pdev, "rtc-soc"); 511 if (IS_ERR(rtc->regs_soc)) 512 return PTR_ERR(rtc->regs_soc); 513 514 rtc->irq = platform_get_irq(pdev, 0); 515 if (rtc->irq < 0) 516 return rtc->irq; 517 518 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); 519 if (IS_ERR(rtc->rtc_dev)) 520 return PTR_ERR(rtc->rtc_dev); 521 522 if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq, 523 0, pdev->name, rtc) < 0) { 524 dev_warn(&pdev->dev, "Interrupt not available.\n"); 525 rtc->irq = -1; 526 } 527 platform_set_drvdata(pdev, rtc); 528 529 if (rtc->irq != -1) 530 device_init_wakeup(&pdev->dev, 1); 531 else 532 clear_bit(RTC_FEATURE_ALARM, rtc->rtc_dev->features); 533 534 /* Update RTC-MBUS bridge timing parameters */ 535 rtc->data->update_mbus_timing(rtc); 536 537 rtc->rtc_dev->ops = &armada38x_rtc_ops; 538 rtc->rtc_dev->range_max = U32_MAX; 539 540 return devm_rtc_register_device(rtc->rtc_dev); 541} 542 543#ifdef CONFIG_PM_SLEEP 544static int armada38x_rtc_suspend(struct device *dev) 545{ 546 if (device_may_wakeup(dev)) { 547 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 548 549 return enable_irq_wake(rtc->irq); 550 } 551 552 return 0; 553} 554 555static int armada38x_rtc_resume(struct device *dev) 556{ 557 if (device_may_wakeup(dev)) { 558 struct armada38x_rtc *rtc = dev_get_drvdata(dev); 559 560 /* Update RTC-MBUS bridge timing parameters */ 561 rtc->data->update_mbus_timing(rtc); 562 563 return disable_irq_wake(rtc->irq); 564 } 565 566 return 0; 567} 568#endif 569 570static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops, 571 armada38x_rtc_suspend, armada38x_rtc_resume); 572 573static struct platform_driver armada38x_rtc_driver = { 574 .driver = { 575 .name = "armada38x-rtc", 576 .pm = &armada38x_rtc_pm_ops, 577 .of_match_table = armada38x_rtc_of_match_table, 578 }, 579}; 580 581module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe); 582 583MODULE_DESCRIPTION("Marvell Armada 38x RTC driver"); 584MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>"); 585MODULE_LICENSE("GPL"); 586