1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. 4 5#include <linux/kernel.h> 6#include <linux/module.h> 7#include <linux/init.h> 8#include <linux/err.h> 9#include <linux/of.h> 10#include <linux/of_device.h> 11#include <linux/regulator/of_regulator.h> 12#include <linux/platform_device.h> 13#include <linux/reboot.h> 14#include <linux/regulator/driver.h> 15#include <linux/regulator/machine.h> 16#include <linux/regulator/pfuze100.h> 17#include <linux/i2c.h> 18#include <linux/slab.h> 19#include <linux/regmap.h> 20 21#define PFUZE_FLAG_DISABLE_SW BIT(1) 22 23#define PFUZE_NUMREGS 128 24#define PFUZE100_VOL_OFFSET 0 25#define PFUZE100_STANDBY_OFFSET 1 26#define PFUZE100_MODE_OFFSET 3 27#define PFUZE100_CONF_OFFSET 4 28 29#define PFUZE100_DEVICEID 0x0 30#define PFUZE100_REVID 0x3 31#define PFUZE100_FABID 0x4 32 33#define PFUZE100_COINVOL 0x1a 34#define PFUZE100_SW1ABVOL 0x20 35#define PFUZE100_SW1ABMODE 0x23 36#define PFUZE100_SW1CVOL 0x2e 37#define PFUZE100_SW1CMODE 0x31 38#define PFUZE100_SW2VOL 0x35 39#define PFUZE100_SW2MODE 0x38 40#define PFUZE100_SW3AVOL 0x3c 41#define PFUZE100_SW3AMODE 0x3f 42#define PFUZE100_SW3BVOL 0x43 43#define PFUZE100_SW3BMODE 0x46 44#define PFUZE100_SW4VOL 0x4a 45#define PFUZE100_SW4MODE 0x4d 46#define PFUZE100_SWBSTCON1 0x66 47#define PFUZE100_VREFDDRCON 0x6a 48#define PFUZE100_VSNVSVOL 0x6b 49#define PFUZE100_VGEN1VOL 0x6c 50#define PFUZE100_VGEN2VOL 0x6d 51#define PFUZE100_VGEN3VOL 0x6e 52#define PFUZE100_VGEN4VOL 0x6f 53#define PFUZE100_VGEN5VOL 0x70 54#define PFUZE100_VGEN6VOL 0x71 55 56#define PFUZE100_SWxMODE_MASK 0xf 57#define PFUZE100_SWxMODE_APS_APS 0x8 58#define PFUZE100_SWxMODE_APS_OFF 0x4 59 60#define PFUZE100_VGENxLPWR BIT(6) 61#define PFUZE100_VGENxSTBY BIT(5) 62 63enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, }; 64 65struct pfuze_regulator { 66 struct regulator_desc desc; 67 unsigned char stby_reg; 68 unsigned char stby_mask; 69 bool sw_reg; 70}; 71 72struct pfuze_chip { 73 int chip_id; 74 int flags; 75 struct regmap *regmap; 76 struct device *dev; 77 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR]; 78 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR]; 79 struct pfuze_regulator *pfuze_regulators; 80}; 81 82static const int pfuze100_swbst[] = { 83 5000000, 5050000, 5100000, 5150000, 84}; 85 86static const int pfuze100_vsnvs[] = { 87 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, 88}; 89 90static const int pfuze100_coin[] = { 91 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000, 92}; 93 94static const int pfuze3000_sw1a[] = { 95 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000, 96 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000, 97 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 98 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000, 99}; 100 101static const int pfuze3000_sw2lo[] = { 102 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 103}; 104 105static const int pfuze3000_sw2hi[] = { 106 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000, 107}; 108 109static const struct of_device_id pfuze_dt_ids[] = { 110 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100}, 111 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200}, 112 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000}, 113 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001}, 114 { } 115}; 116MODULE_DEVICE_TABLE(of, pfuze_dt_ids); 117 118static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) 119{ 120 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev); 121 int id = rdev_get_id(rdev); 122 bool reg_has_ramp_delay; 123 unsigned int ramp_bits = 0; 124 int ret; 125 126 switch (pfuze100->chip_id) { 127 case PFUZE3001: 128 /* no dynamic voltage scaling for PF3001 */ 129 reg_has_ramp_delay = false; 130 break; 131 case PFUZE3000: 132 reg_has_ramp_delay = (id < PFUZE3000_SWBST); 133 break; 134 case PFUZE200: 135 reg_has_ramp_delay = (id < PFUZE200_SWBST); 136 break; 137 case PFUZE100: 138 default: 139 reg_has_ramp_delay = (id < PFUZE100_SWBST); 140 break; 141 } 142 143 if (reg_has_ramp_delay) { 144 if (ramp_delay > 0) { 145 ramp_delay = 12500 / ramp_delay; 146 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3); 147 } 148 149 ret = regmap_update_bits(pfuze100->regmap, 150 rdev->desc->vsel_reg + 4, 151 0xc0, ramp_bits << 6); 152 if (ret < 0) 153 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret); 154 } else { 155 ret = -EACCES; 156 } 157 158 return ret; 159} 160 161static const struct regulator_ops pfuze100_ldo_regulator_ops = { 162 .enable = regulator_enable_regmap, 163 .disable = regulator_disable_regmap, 164 .is_enabled = regulator_is_enabled_regmap, 165 .list_voltage = regulator_list_voltage_linear, 166 .set_voltage_sel = regulator_set_voltage_sel_regmap, 167 .get_voltage_sel = regulator_get_voltage_sel_regmap, 168}; 169 170static const struct regulator_ops pfuze100_fixed_regulator_ops = { 171 .enable = regulator_enable_regmap, 172 .disable = regulator_disable_regmap, 173 .is_enabled = regulator_is_enabled_regmap, 174 .list_voltage = regulator_list_voltage_linear, 175}; 176 177static const struct regulator_ops pfuze100_sw_regulator_ops = { 178 .list_voltage = regulator_list_voltage_linear, 179 .set_voltage_sel = regulator_set_voltage_sel_regmap, 180 .get_voltage_sel = regulator_get_voltage_sel_regmap, 181 .set_voltage_time_sel = regulator_set_voltage_time_sel, 182 .set_ramp_delay = pfuze100_set_ramp_delay, 183}; 184 185static const struct regulator_ops pfuze100_sw_disable_regulator_ops = { 186 .enable = regulator_enable_regmap, 187 .disable = regulator_disable_regmap, 188 .is_enabled = regulator_is_enabled_regmap, 189 .list_voltage = regulator_list_voltage_linear, 190 .set_voltage_sel = regulator_set_voltage_sel_regmap, 191 .get_voltage_sel = regulator_get_voltage_sel_regmap, 192 .set_voltage_time_sel = regulator_set_voltage_time_sel, 193 .set_ramp_delay = pfuze100_set_ramp_delay, 194}; 195 196static const struct regulator_ops pfuze100_swb_regulator_ops = { 197 .enable = regulator_enable_regmap, 198 .disable = regulator_disable_regmap, 199 .is_enabled = regulator_is_enabled_regmap, 200 .list_voltage = regulator_list_voltage_table, 201 .map_voltage = regulator_map_voltage_ascend, 202 .set_voltage_sel = regulator_set_voltage_sel_regmap, 203 .get_voltage_sel = regulator_get_voltage_sel_regmap, 204 205}; 206 207static const struct regulator_ops pfuze3000_sw_regulator_ops = { 208 .enable = regulator_enable_regmap, 209 .disable = regulator_disable_regmap, 210 .is_enabled = regulator_is_enabled_regmap, 211 .list_voltage = regulator_list_voltage_table, 212 .map_voltage = regulator_map_voltage_ascend, 213 .set_voltage_sel = regulator_set_voltage_sel_regmap, 214 .get_voltage_sel = regulator_get_voltage_sel_regmap, 215 .set_voltage_time_sel = regulator_set_voltage_time_sel, 216 .set_ramp_delay = pfuze100_set_ramp_delay, 217 218}; 219 220#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ 221 [_chip ## _ ## _name] = { \ 222 .desc = { \ 223 .name = #_name, \ 224 .n_voltages = 1, \ 225 .ops = &pfuze100_fixed_regulator_ops, \ 226 .type = REGULATOR_VOLTAGE, \ 227 .id = _chip ## _ ## _name, \ 228 .owner = THIS_MODULE, \ 229 .min_uV = (voltage), \ 230 .enable_reg = (base), \ 231 .enable_mask = 0x10, \ 232 }, \ 233 } 234 235#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ 236 [_chip ## _ ## _name] = { \ 237 .desc = { \ 238 .name = #_name,\ 239 .n_voltages = ((max) - (min)) / (step) + 1, \ 240 .ops = &pfuze100_sw_regulator_ops, \ 241 .type = REGULATOR_VOLTAGE, \ 242 .id = _chip ## _ ## _name, \ 243 .owner = THIS_MODULE, \ 244 .min_uV = (min), \ 245 .uV_step = (step), \ 246 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 247 .vsel_mask = 0x3f, \ 248 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \ 249 .enable_mask = 0xf, \ 250 }, \ 251 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 252 .stby_mask = 0x3f, \ 253 .sw_reg = true, \ 254 } 255 256#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ 257 [_chip ## _ ## _name] = { \ 258 .desc = { \ 259 .name = #_name, \ 260 .n_voltages = ARRAY_SIZE(voltages), \ 261 .ops = &pfuze100_swb_regulator_ops, \ 262 .type = REGULATOR_VOLTAGE, \ 263 .id = _chip ## _ ## _name, \ 264 .owner = THIS_MODULE, \ 265 .volt_table = voltages, \ 266 .vsel_reg = (base), \ 267 .vsel_mask = (mask), \ 268 .enable_reg = (base), \ 269 .enable_mask = 0x48, \ 270 }, \ 271 } 272 273#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \ 274 [_chip ## _ ## _name] = { \ 275 .desc = { \ 276 .name = #_name, \ 277 .n_voltages = ((max) - (min)) / (step) + 1, \ 278 .ops = &pfuze100_ldo_regulator_ops, \ 279 .type = REGULATOR_VOLTAGE, \ 280 .id = _chip ## _ ## _name, \ 281 .owner = THIS_MODULE, \ 282 .min_uV = (min), \ 283 .uV_step = (step), \ 284 .vsel_reg = (base), \ 285 .vsel_mask = 0xf, \ 286 .enable_reg = (base), \ 287 .enable_mask = 0x10, \ 288 }, \ 289 .stby_reg = (base), \ 290 .stby_mask = 0x20, \ 291 } 292 293#define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \ 294 [_chip ## _ ## _name] = { \ 295 .desc = { \ 296 .name = #_name, \ 297 .n_voltages = ARRAY_SIZE(voltages), \ 298 .ops = &pfuze100_swb_regulator_ops, \ 299 .type = REGULATOR_VOLTAGE, \ 300 .id = _chip ## _ ## _name, \ 301 .owner = THIS_MODULE, \ 302 .volt_table = voltages, \ 303 .vsel_reg = (base), \ 304 .vsel_mask = (mask), \ 305 .enable_reg = (base), \ 306 .enable_mask = 0x8, \ 307 }, \ 308 } 309 310#define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \ 311 .desc = { \ 312 .name = #_name, \ 313 .n_voltages = ((max) - (min)) / (step) + 1, \ 314 .ops = &pfuze100_ldo_regulator_ops, \ 315 .type = REGULATOR_VOLTAGE, \ 316 .id = _chip ## _ ## _name, \ 317 .owner = THIS_MODULE, \ 318 .min_uV = (min), \ 319 .uV_step = (step), \ 320 .vsel_reg = (base), \ 321 .vsel_mask = 0x3, \ 322 .enable_reg = (base), \ 323 .enable_mask = 0x10, \ 324 }, \ 325 .stby_reg = (base), \ 326 .stby_mask = 0x20, \ 327} 328 329/* No linar case for the some switches of PFUZE3000 */ 330#define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \ 331 [_chip ## _ ## _name] = { \ 332 .desc = { \ 333 .name = #_name, \ 334 .n_voltages = ARRAY_SIZE(voltages), \ 335 .ops = &pfuze3000_sw_regulator_ops, \ 336 .type = REGULATOR_VOLTAGE, \ 337 .id = _chip ## _ ## _name, \ 338 .owner = THIS_MODULE, \ 339 .volt_table = voltages, \ 340 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 341 .vsel_mask = (mask), \ 342 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \ 343 .enable_mask = 0xf, \ 344 .enable_val = 0x8, \ 345 .enable_time = 500, \ 346 }, \ 347 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 348 .stby_mask = (mask), \ 349 .sw_reg = true, \ 350 } 351 352#define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \ 353 .desc = { \ 354 .name = #_name,\ 355 .n_voltages = ((max) - (min)) / (step) + 1, \ 356 .ops = &pfuze100_sw_regulator_ops, \ 357 .type = REGULATOR_VOLTAGE, \ 358 .id = _chip ## _ ## _name, \ 359 .owner = THIS_MODULE, \ 360 .min_uV = (min), \ 361 .uV_step = (step), \ 362 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 363 .vsel_mask = 0xf, \ 364 }, \ 365 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 366 .stby_mask = 0xf, \ 367} 368 369/* PFUZE100 */ 370static struct pfuze_regulator pfuze100_regulators[] = { 371 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000), 372 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000), 373 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000), 374 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000), 375 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000), 376 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000), 377 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst), 378 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 379 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000), 380 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000), 381 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 382 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000), 383 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000), 384 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 385 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 386 PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin), 387}; 388 389static struct pfuze_regulator pfuze200_regulators[] = { 390 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000), 391 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000), 392 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000), 393 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000), 394 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst), 395 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 396 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000), 397 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000), 398 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 399 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000), 400 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000), 401 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 402 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 403 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin), 404}; 405 406static struct pfuze_regulator pfuze3000_regulators[] = { 407 PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a), 408 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000), 409 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo), 410 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000), 411 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst), 412 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 413 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000), 414 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000), 415 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 416 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000), 417 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000), 418 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 419 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 420}; 421 422static struct pfuze_regulator pfuze3001_regulators[] = { 423 PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a), 424 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo), 425 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000), 426 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 427 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000), 428 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 429 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000), 430 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000), 431 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 432 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 433}; 434 435/* PFUZE100 */ 436static struct of_regulator_match pfuze100_matches[] = { 437 { .name = "sw1ab", }, 438 { .name = "sw1c", }, 439 { .name = "sw2", }, 440 { .name = "sw3a", }, 441 { .name = "sw3b", }, 442 { .name = "sw4", }, 443 { .name = "swbst", }, 444 { .name = "vsnvs", }, 445 { .name = "vrefddr", }, 446 { .name = "vgen1", }, 447 { .name = "vgen2", }, 448 { .name = "vgen3", }, 449 { .name = "vgen4", }, 450 { .name = "vgen5", }, 451 { .name = "vgen6", }, 452 { .name = "coin", }, 453}; 454 455/* PFUZE200 */ 456static struct of_regulator_match pfuze200_matches[] = { 457 458 { .name = "sw1ab", }, 459 { .name = "sw2", }, 460 { .name = "sw3a", }, 461 { .name = "sw3b", }, 462 { .name = "swbst", }, 463 { .name = "vsnvs", }, 464 { .name = "vrefddr", }, 465 { .name = "vgen1", }, 466 { .name = "vgen2", }, 467 { .name = "vgen3", }, 468 { .name = "vgen4", }, 469 { .name = "vgen5", }, 470 { .name = "vgen6", }, 471 { .name = "coin", }, 472}; 473 474/* PFUZE3000 */ 475static struct of_regulator_match pfuze3000_matches[] = { 476 477 { .name = "sw1a", }, 478 { .name = "sw1b", }, 479 { .name = "sw2", }, 480 { .name = "sw3", }, 481 { .name = "swbst", }, 482 { .name = "vsnvs", }, 483 { .name = "vrefddr", }, 484 { .name = "vldo1", }, 485 { .name = "vldo2", }, 486 { .name = "vccsd", }, 487 { .name = "v33", }, 488 { .name = "vldo3", }, 489 { .name = "vldo4", }, 490}; 491 492/* PFUZE3001 */ 493static struct of_regulator_match pfuze3001_matches[] = { 494 495 { .name = "sw1", }, 496 { .name = "sw2", }, 497 { .name = "sw3", }, 498 { .name = "vsnvs", }, 499 { .name = "vldo1", }, 500 { .name = "vldo2", }, 501 { .name = "vccsd", }, 502 { .name = "v33", }, 503 { .name = "vldo3", }, 504 { .name = "vldo4", }, 505}; 506 507static struct of_regulator_match *pfuze_matches; 508 509static int pfuze_parse_regulators_dt(struct pfuze_chip *chip) 510{ 511 struct device *dev = chip->dev; 512 struct device_node *np, *parent; 513 int ret; 514 515 np = of_node_get(dev->of_node); 516 if (!np) 517 return -EINVAL; 518 519 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw")) 520 chip->flags |= PFUZE_FLAG_DISABLE_SW; 521 522 parent = of_get_child_by_name(np, "regulators"); 523 if (!parent) { 524 dev_err(dev, "regulators node not found\n"); 525 of_node_put(np); 526 return -EINVAL; 527 } 528 529 switch (chip->chip_id) { 530 case PFUZE3001: 531 pfuze_matches = pfuze3001_matches; 532 ret = of_regulator_match(dev, parent, pfuze3001_matches, 533 ARRAY_SIZE(pfuze3001_matches)); 534 break; 535 case PFUZE3000: 536 pfuze_matches = pfuze3000_matches; 537 ret = of_regulator_match(dev, parent, pfuze3000_matches, 538 ARRAY_SIZE(pfuze3000_matches)); 539 break; 540 case PFUZE200: 541 pfuze_matches = pfuze200_matches; 542 ret = of_regulator_match(dev, parent, pfuze200_matches, 543 ARRAY_SIZE(pfuze200_matches)); 544 break; 545 546 case PFUZE100: 547 default: 548 pfuze_matches = pfuze100_matches; 549 ret = of_regulator_match(dev, parent, pfuze100_matches, 550 ARRAY_SIZE(pfuze100_matches)); 551 break; 552 } 553 554 of_node_put(parent); 555 of_node_put(np); 556 if (ret < 0) { 557 dev_err(dev, "Error parsing regulator init data: %d\n", 558 ret); 559 return ret; 560 } 561 562 return 0; 563} 564 565static inline struct regulator_init_data *match_init_data(int index) 566{ 567 return pfuze_matches[index].init_data; 568} 569 570static inline struct device_node *match_of_node(int index) 571{ 572 return pfuze_matches[index].of_node; 573} 574 575static int pfuze_power_off_prepare(struct sys_off_data *data) 576{ 577 struct pfuze_chip *syspm_pfuze_chip = data->cb_data; 578 579 dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off"); 580 581 /* Switch from default mode: APS/APS to APS/Off */ 582 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE, 583 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 584 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE, 585 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 586 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE, 587 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 588 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE, 589 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 590 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE, 591 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 592 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE, 593 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 594 595 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL, 596 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 597 PFUZE100_VGENxSTBY); 598 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL, 599 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 600 PFUZE100_VGENxSTBY); 601 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL, 602 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 603 PFUZE100_VGENxSTBY); 604 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL, 605 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 606 PFUZE100_VGENxSTBY); 607 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL, 608 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 609 PFUZE100_VGENxSTBY); 610 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL, 611 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 612 PFUZE100_VGENxSTBY); 613 614 return NOTIFY_DONE; 615} 616 617static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip) 618{ 619 int err; 620 621 if (pfuze_chip->chip_id != PFUZE100) { 622 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n"); 623 return -ENODEV; 624 } 625 626 err = devm_register_sys_off_handler(pfuze_chip->dev, 627 SYS_OFF_MODE_POWER_OFF_PREPARE, 628 SYS_OFF_PRIO_DEFAULT, 629 pfuze_power_off_prepare, 630 pfuze_chip); 631 if (err) { 632 dev_err(pfuze_chip->dev, "failed to register sys-off handler: %d\n", 633 err); 634 return err; 635 } 636 637 return 0; 638} 639 640static int pfuze_identify(struct pfuze_chip *pfuze_chip) 641{ 642 unsigned int value; 643 int ret; 644 645 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value); 646 if (ret) 647 return ret; 648 649 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) { 650 /* 651 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013 652 * as ID=8 in PFUZE100 653 */ 654 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8"); 655 } else if ((value & 0x0f) != pfuze_chip->chip_id && 656 (value & 0xf0) >> 4 != pfuze_chip->chip_id && 657 (value != pfuze_chip->chip_id)) { 658 /* device id NOT match with your setting */ 659 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value); 660 return -ENODEV; 661 } 662 663 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value); 664 if (ret) 665 return ret; 666 dev_info(pfuze_chip->dev, 667 "Full layer: %x, Metal layer: %x\n", 668 (value & 0xf0) >> 4, value & 0x0f); 669 670 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value); 671 if (ret) 672 return ret; 673 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n", 674 (value & 0xc) >> 2, value & 0x3); 675 676 return 0; 677} 678 679static const struct regmap_config pfuze_regmap_config = { 680 .reg_bits = 8, 681 .val_bits = 8, 682 .max_register = PFUZE_NUMREGS - 1, 683 .cache_type = REGCACHE_RBTREE, 684}; 685 686static int pfuze100_regulator_probe(struct i2c_client *client) 687{ 688 const struct i2c_device_id *id = i2c_client_get_device_id(client); 689 struct pfuze_chip *pfuze_chip; 690 struct regulator_config config = { }; 691 int i, ret; 692 const struct of_device_id *match; 693 u32 regulator_num; 694 u32 sw_check_start, sw_check_end, sw_hi = 0x40; 695 696 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip), 697 GFP_KERNEL); 698 if (!pfuze_chip) 699 return -ENOMEM; 700 701 if (client->dev.of_node) { 702 match = of_match_device(pfuze_dt_ids, &client->dev); 703 if (!match) { 704 dev_err(&client->dev, "Error: No device match found\n"); 705 return -ENODEV; 706 } 707 pfuze_chip->chip_id = (int)(long)match->data; 708 } else if (id) { 709 pfuze_chip->chip_id = id->driver_data; 710 } else { 711 dev_err(&client->dev, "No dts match or id table match found\n"); 712 return -ENODEV; 713 } 714 715 i2c_set_clientdata(client, pfuze_chip); 716 pfuze_chip->dev = &client->dev; 717 718 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config); 719 if (IS_ERR(pfuze_chip->regmap)) { 720 ret = PTR_ERR(pfuze_chip->regmap); 721 dev_err(&client->dev, 722 "regmap allocation failed with err %d\n", ret); 723 return ret; 724 } 725 726 ret = pfuze_identify(pfuze_chip); 727 if (ret) { 728 dev_err(&client->dev, "unrecognized pfuze chip ID!\n"); 729 return ret; 730 } 731 732 /* use the right regulators after identify the right device */ 733 switch (pfuze_chip->chip_id) { 734 case PFUZE3001: 735 pfuze_chip->pfuze_regulators = pfuze3001_regulators; 736 regulator_num = ARRAY_SIZE(pfuze3001_regulators); 737 sw_check_start = PFUZE3001_SW2; 738 sw_check_end = PFUZE3001_SW2; 739 sw_hi = 1 << 3; 740 break; 741 case PFUZE3000: 742 pfuze_chip->pfuze_regulators = pfuze3000_regulators; 743 regulator_num = ARRAY_SIZE(pfuze3000_regulators); 744 sw_check_start = PFUZE3000_SW2; 745 sw_check_end = PFUZE3000_SW2; 746 sw_hi = 1 << 3; 747 break; 748 case PFUZE200: 749 pfuze_chip->pfuze_regulators = pfuze200_regulators; 750 regulator_num = ARRAY_SIZE(pfuze200_regulators); 751 sw_check_start = PFUZE200_SW2; 752 sw_check_end = PFUZE200_SW3B; 753 break; 754 case PFUZE100: 755 default: 756 pfuze_chip->pfuze_regulators = pfuze100_regulators; 757 regulator_num = ARRAY_SIZE(pfuze100_regulators); 758 sw_check_start = PFUZE100_SW2; 759 sw_check_end = PFUZE100_SW4; 760 break; 761 } 762 dev_info(&client->dev, "pfuze%s found.\n", 763 (pfuze_chip->chip_id == PFUZE100) ? "100" : 764 (((pfuze_chip->chip_id == PFUZE200) ? "200" : 765 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001")))); 766 767 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators, 768 regulator_num * sizeof(struct pfuze_regulator)); 769 770 ret = pfuze_parse_regulators_dt(pfuze_chip); 771 if (ret) 772 return ret; 773 774 for (i = 0; i < regulator_num; i++) { 775 struct regulator_init_data *init_data; 776 struct regulator_desc *desc; 777 int val; 778 779 desc = &pfuze_chip->regulator_descs[i].desc; 780 781 init_data = match_init_data(i); 782 783 /* SW2~SW4 high bit check and modify the voltage value table */ 784 if (i >= sw_check_start && i <= sw_check_end) { 785 ret = regmap_read(pfuze_chip->regmap, 786 desc->vsel_reg, &val); 787 if (ret) { 788 dev_err(&client->dev, "Fails to read from the register.\n"); 789 return ret; 790 } 791 792 if (val & sw_hi) { 793 if (pfuze_chip->chip_id == PFUZE3000 || 794 pfuze_chip->chip_id == PFUZE3001) { 795 desc->volt_table = pfuze3000_sw2hi; 796 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi); 797 } else { 798 desc->min_uV = 800000; 799 desc->uV_step = 50000; 800 desc->n_voltages = 51; 801 } 802 } 803 } 804 805 /* 806 * Allow SW regulators to turn off. Checking it trough a flag is 807 * a workaround to keep the backward compatibility with existing 808 * old dtb's which may relay on the fact that we didn't disable 809 * the switched regulator till yet. 810 */ 811 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) { 812 if (pfuze_chip->chip_id == PFUZE100 || 813 pfuze_chip->chip_id == PFUZE200) { 814 if (pfuze_chip->regulator_descs[i].sw_reg) { 815 desc->ops = &pfuze100_sw_disable_regulator_ops; 816 desc->enable_val = 0x8; 817 desc->disable_val = 0x0; 818 desc->enable_time = 500; 819 } 820 } 821 } 822 823 config.dev = &client->dev; 824 config.init_data = init_data; 825 config.driver_data = pfuze_chip; 826 config.of_node = match_of_node(i); 827 828 pfuze_chip->regulators[i] = 829 devm_regulator_register(&client->dev, desc, &config); 830 if (IS_ERR(pfuze_chip->regulators[i])) { 831 dev_err(&client->dev, "register regulator%s failed\n", 832 pfuze_chip->pfuze_regulators[i].desc.name); 833 return PTR_ERR(pfuze_chip->regulators[i]); 834 } 835 } 836 837 if (of_property_read_bool(client->dev.of_node, 838 "fsl,pmic-stby-poweroff")) 839 return pfuze_power_off_prepare_init(pfuze_chip); 840 841 return 0; 842} 843 844static struct i2c_driver pfuze_driver = { 845 .driver = { 846 .name = "pfuze100-regulator", 847 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 848 .of_match_table = pfuze_dt_ids, 849 }, 850 .probe = pfuze100_regulator_probe, 851}; 852module_i2c_driver(pfuze_driver); 853 854MODULE_AUTHOR("Robin Gong <b38343@freescale.com>"); 855MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC"); 856MODULE_LICENSE("GPL v2"); 857