1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge 4 * 5 * Copyright 2011 Integrated Device Technology, Inc. 6 * Alexandre Bounine <alexandre.bounine@idt.com> 7 * Chul Kim <chul.kim@idt.com> 8 */ 9 10#include <linux/io.h> 11#include <linux/errno.h> 12#include <linux/init.h> 13#include <linux/ioport.h> 14#include <linux/kernel.h> 15#include <linux/module.h> 16#include <linux/pci.h> 17#include <linux/rio.h> 18#include <linux/rio_drv.h> 19#include <linux/dma-mapping.h> 20#include <linux/interrupt.h> 21#include <linux/kfifo.h> 22#include <linux/delay.h> 23 24#include "tsi721.h" 25 26#ifdef DEBUG 27u32 tsi_dbg_level; 28module_param_named(dbg_level, tsi_dbg_level, uint, S_IWUSR | S_IRUGO); 29MODULE_PARM_DESC(dbg_level, "Debugging output level (default 0 = none)"); 30#endif 31 32static int pcie_mrrs = -1; 33module_param(pcie_mrrs, int, S_IRUGO); 34MODULE_PARM_DESC(pcie_mrrs, "PCIe MRRS override value (0...5)"); 35 36static u8 mbox_sel = 0x0f; 37module_param(mbox_sel, byte, S_IRUGO); 38MODULE_PARM_DESC(mbox_sel, 39 "RIO Messaging MBOX Selection Mask (default: 0x0f = all)"); 40 41static DEFINE_SPINLOCK(tsi721_maint_lock); 42 43static void tsi721_omsg_handler(struct tsi721_device *priv, int ch); 44static void tsi721_imsg_handler(struct tsi721_device *priv, int ch); 45 46/** 47 * tsi721_lcread - read from local SREP config space 48 * @mport: RapidIO master port info 49 * @index: ID of RapdiIO interface 50 * @offset: Offset into configuration space 51 * @len: Length (in bytes) of the maintenance transaction 52 * @data: Value to be read into 53 * 54 * Generates a local SREP space read. 55 * 56 * Returns: %0 on success or %-EINVAL on failure. 57 */ 58static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset, 59 int len, u32 *data) 60{ 61 struct tsi721_device *priv = mport->priv; 62 63 if (len != sizeof(u32)) 64 return -EINVAL; /* only 32-bit access is supported */ 65 66 *data = ioread32(priv->regs + offset); 67 68 return 0; 69} 70 71/** 72 * tsi721_lcwrite - write into local SREP config space 73 * @mport: RapidIO master port info 74 * @index: ID of RapdiIO interface 75 * @offset: Offset into configuration space 76 * @len: Length (in bytes) of the maintenance transaction 77 * @data: Value to be written 78 * 79 * Generates a local write into SREP configuration space. 80 * 81 * Returns: %0 on success or %-EINVAL on failure. 82 */ 83static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset, 84 int len, u32 data) 85{ 86 struct tsi721_device *priv = mport->priv; 87 88 if (len != sizeof(u32)) 89 return -EINVAL; /* only 32-bit access is supported */ 90 91 iowrite32(data, priv->regs + offset); 92 93 return 0; 94} 95 96/** 97 * tsi721_maint_dma - Helper function to generate RapidIO maintenance 98 * transactions using designated Tsi721 DMA channel. 99 * @priv: pointer to tsi721 private data 100 * @sys_size: RapdiIO transport system size 101 * @destid: Destination ID of transaction 102 * @hopcount: Number of hops to target device 103 * @offset: Offset into configuration space 104 * @len: Length (in bytes) of the maintenance transaction 105 * @data: Location to be read from or write into 106 * @do_wr: Operation flag (1 == MAINT_WR) 107 * 108 * Generates a RapidIO maintenance transaction (Read or Write). 109 * Returns: %0 on success and %-EINVAL or %-EFAULT on failure. 110 */ 111static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size, 112 u16 destid, u8 hopcount, u32 offset, int len, 113 u32 *data, int do_wr) 114{ 115 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); 116 struct tsi721_dma_desc *bd_ptr; 117 u32 rd_count, swr_ptr, ch_stat; 118 unsigned long flags; 119 int i, err = 0; 120 u32 op = do_wr ? MAINT_WR : MAINT_RD; 121 122 if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32))) 123 return -EINVAL; 124 125 spin_lock_irqsave(&tsi721_maint_lock, flags); 126 127 bd_ptr = priv->mdma.bd_base; 128 129 rd_count = ioread32(regs + TSI721_DMAC_DRDCNT); 130 131 /* Initialize DMA descriptor */ 132 bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid); 133 bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04); 134 bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset); 135 bd_ptr[0].raddr_hi = 0; 136 if (do_wr) 137 bd_ptr[0].data[0] = cpu_to_be32p(data); 138 else 139 bd_ptr[0].data[0] = 0xffffffff; 140 141 mb(); 142 143 /* Start DMA operation */ 144 iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT); 145 ioread32(regs + TSI721_DMAC_DWRCNT); 146 i = 0; 147 148 /* Wait until DMA transfer is finished */ 149 while ((ch_stat = ioread32(regs + TSI721_DMAC_STS)) 150 & TSI721_DMAC_STS_RUN) { 151 udelay(1); 152 if (++i >= 5000000) { 153 tsi_debug(MAINT, &priv->pdev->dev, 154 "DMA[%d] read timeout ch_status=%x", 155 priv->mdma.ch_id, ch_stat); 156 if (!do_wr) 157 *data = 0xffffffff; 158 err = -EIO; 159 goto err_out; 160 } 161 } 162 163 if (ch_stat & TSI721_DMAC_STS_ABORT) { 164 /* If DMA operation aborted due to error, 165 * reinitialize DMA channel 166 */ 167 tsi_debug(MAINT, &priv->pdev->dev, "DMA ABORT ch_stat=%x", 168 ch_stat); 169 tsi_debug(MAINT, &priv->pdev->dev, 170 "OP=%d : destid=%x hc=%x off=%x", 171 do_wr ? MAINT_WR : MAINT_RD, 172 destid, hopcount, offset); 173 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT); 174 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); 175 udelay(10); 176 iowrite32(0, regs + TSI721_DMAC_DWRCNT); 177 udelay(1); 178 if (!do_wr) 179 *data = 0xffffffff; 180 err = -EIO; 181 goto err_out; 182 } 183 184 if (!do_wr) 185 *data = be32_to_cpu(bd_ptr[0].data[0]); 186 187 /* 188 * Update descriptor status FIFO RD pointer. 189 * NOTE: Skipping check and clear FIFO entries because we are waiting 190 * for transfer to be completed. 191 */ 192 swr_ptr = ioread32(regs + TSI721_DMAC_DSWP); 193 iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP); 194 195err_out: 196 spin_unlock_irqrestore(&tsi721_maint_lock, flags); 197 198 return err; 199} 200 201/** 202 * tsi721_cread_dma - Generate a RapidIO maintenance read transaction 203 * using Tsi721 BDMA engine. 204 * @mport: RapidIO master port control structure 205 * @index: ID of RapdiIO interface 206 * @destid: Destination ID of transaction 207 * @hopcount: Number of hops to target device 208 * @offset: Offset into configuration space 209 * @len: Length (in bytes) of the maintenance transaction 210 * @data: Location to be read into 211 * 212 * Generates a RapidIO maintenance read transaction. 213 * Returns: %0 on success and %-EINVAL or %-EFAULT on failure. 214 */ 215static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid, 216 u8 hopcount, u32 offset, int len, u32 *data) 217{ 218 struct tsi721_device *priv = mport->priv; 219 220 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount, 221 offset, len, data, 0); 222} 223 224/** 225 * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction 226 * using Tsi721 BDMA engine 227 * @mport: RapidIO master port control structure 228 * @index: ID of RapdiIO interface 229 * @destid: Destination ID of transaction 230 * @hopcount: Number of hops to target device 231 * @offset: Offset into configuration space 232 * @len: Length (in bytes) of the maintenance transaction 233 * @data: Value to be written 234 * 235 * Generates a RapidIO maintenance write transaction. 236 * Returns: %0 on success and %-EINVAL or %-EFAULT on failure. 237 */ 238static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid, 239 u8 hopcount, u32 offset, int len, u32 data) 240{ 241 struct tsi721_device *priv = mport->priv; 242 u32 temp = data; 243 244 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount, 245 offset, len, &temp, 1); 246} 247 248/** 249 * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler 250 * @priv: tsi721 device private structure 251 * 252 * Handles inbound port-write interrupts. Copies PW message from an internal 253 * buffer into PW message FIFO and schedules deferred routine to process 254 * queued messages. 255 * 256 * Returns: %0 257 */ 258static int 259tsi721_pw_handler(struct tsi721_device *priv) 260{ 261 u32 pw_stat; 262 u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)]; 263 264 265 pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT); 266 267 if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) { 268 pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0)); 269 pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1)); 270 pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2)); 271 pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3)); 272 273 /* Queue PW message (if there is room in FIFO), 274 * otherwise discard it. 275 */ 276 spin_lock(&priv->pw_fifo_lock); 277 if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE) 278 kfifo_in(&priv->pw_fifo, pw_buf, 279 TSI721_RIO_PW_MSG_SIZE); 280 else 281 priv->pw_discard_count++; 282 spin_unlock(&priv->pw_fifo_lock); 283 } 284 285 /* Clear pending PW interrupts */ 286 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL, 287 priv->regs + TSI721_RIO_PW_RX_STAT); 288 289 schedule_work(&priv->pw_work); 290 291 return 0; 292} 293 294static void tsi721_pw_dpc(struct work_struct *work) 295{ 296 struct tsi721_device *priv = container_of(work, struct tsi721_device, 297 pw_work); 298 union rio_pw_msg pwmsg; 299 300 /* 301 * Process port-write messages 302 */ 303 while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)&pwmsg, 304 TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) { 305 /* Pass the port-write message to RIO core for processing */ 306 rio_inb_pwrite_handler(&priv->mport, &pwmsg); 307 } 308} 309 310/** 311 * tsi721_pw_enable - enable/disable port-write interface init 312 * @mport: Master port implementing the port write unit 313 * @enable: 1=enable; 0=disable port-write message handling 314 * 315 * Returns: %0 316 */ 317static int tsi721_pw_enable(struct rio_mport *mport, int enable) 318{ 319 struct tsi721_device *priv = mport->priv; 320 u32 rval; 321 322 rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE); 323 324 if (enable) 325 rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX; 326 else 327 rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX; 328 329 /* Clear pending PW interrupts */ 330 iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL, 331 priv->regs + TSI721_RIO_PW_RX_STAT); 332 /* Update enable bits */ 333 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE); 334 335 return 0; 336} 337 338/** 339 * tsi721_dsend - Send a RapidIO doorbell 340 * @mport: RapidIO master port info 341 * @index: ID of RapidIO interface 342 * @destid: Destination ID of target device 343 * @data: 16-bit info field of RapidIO doorbell 344 * 345 * Sends a RapidIO doorbell message. 346 * 347 * Returns: %0 348 */ 349static int tsi721_dsend(struct rio_mport *mport, int index, 350 u16 destid, u16 data) 351{ 352 struct tsi721_device *priv = mport->priv; 353 u32 offset; 354 355 offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) | 356 (destid << 2); 357 358 tsi_debug(DBELL, &priv->pdev->dev, 359 "Send Doorbell 0x%04x to destID 0x%x", data, destid); 360 iowrite16be(data, priv->odb_base + offset); 361 362 return 0; 363} 364 365/** 366 * tsi721_dbell_handler - Tsi721 doorbell interrupt handler 367 * @priv: tsi721 device-specific data structure 368 * 369 * Handles inbound doorbell interrupts. Copies doorbell entry from an internal 370 * buffer into DB message FIFO and schedules deferred routine to process 371 * queued DBs. 372 * 373 * Returns: %0 374 */ 375static int 376tsi721_dbell_handler(struct tsi721_device *priv) 377{ 378 u32 regval; 379 380 /* Disable IDB interrupts */ 381 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); 382 regval &= ~TSI721_SR_CHINT_IDBQRCV; 383 iowrite32(regval, 384 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); 385 386 schedule_work(&priv->idb_work); 387 388 return 0; 389} 390 391static void tsi721_db_dpc(struct work_struct *work) 392{ 393 struct tsi721_device *priv = container_of(work, struct tsi721_device, 394 idb_work); 395 struct rio_mport *mport; 396 struct rio_dbell *dbell; 397 int found = 0; 398 u32 wr_ptr, rd_ptr; 399 u64 *idb_entry; 400 u32 regval; 401 union { 402 u64 msg; 403 u8 bytes[8]; 404 } idb; 405 406 /* 407 * Process queued inbound doorbells 408 */ 409 mport = &priv->mport; 410 411 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; 412 rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE; 413 414 while (wr_ptr != rd_ptr) { 415 idb_entry = (u64 *)(priv->idb_base + 416 (TSI721_IDB_ENTRY_SIZE * rd_ptr)); 417 rd_ptr++; 418 rd_ptr %= IDB_QSIZE; 419 idb.msg = *idb_entry; 420 *idb_entry = 0; 421 422 /* Process one doorbell */ 423 list_for_each_entry(dbell, &mport->dbells, node) { 424 if ((dbell->res->start <= DBELL_INF(idb.bytes)) && 425 (dbell->res->end >= DBELL_INF(idb.bytes))) { 426 found = 1; 427 break; 428 } 429 } 430 431 if (found) { 432 dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes), 433 DBELL_TID(idb.bytes), DBELL_INF(idb.bytes)); 434 } else { 435 tsi_debug(DBELL, &priv->pdev->dev, 436 "spurious IDB sid %2.2x tid %2.2x info %4.4x", 437 DBELL_SID(idb.bytes), DBELL_TID(idb.bytes), 438 DBELL_INF(idb.bytes)); 439 } 440 441 wr_ptr = ioread32(priv->regs + 442 TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; 443 } 444 445 iowrite32(rd_ptr & (IDB_QSIZE - 1), 446 priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); 447 448 /* Re-enable IDB interrupts */ 449 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); 450 regval |= TSI721_SR_CHINT_IDBQRCV; 451 iowrite32(regval, 452 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); 453 454 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; 455 if (wr_ptr != rd_ptr) 456 schedule_work(&priv->idb_work); 457} 458 459/** 460 * tsi721_irqhandler - Tsi721 interrupt handler 461 * @irq: Linux interrupt number 462 * @ptr: Pointer to interrupt-specific data (tsi721_device structure) 463 * 464 * Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported 465 * interrupt events and calls an event-specific handler(s). 466 * 467 * Returns: %IRQ_HANDLED or %IRQ_NONE 468 */ 469static irqreturn_t tsi721_irqhandler(int irq, void *ptr) 470{ 471 struct tsi721_device *priv = (struct tsi721_device *)ptr; 472 u32 dev_int; 473 u32 dev_ch_int; 474 u32 intval; 475 u32 ch_inte; 476 477 /* For MSI mode disable all device-level interrupts */ 478 if (priv->flags & TSI721_USING_MSI) 479 iowrite32(0, priv->regs + TSI721_DEV_INTE); 480 481 dev_int = ioread32(priv->regs + TSI721_DEV_INT); 482 if (!dev_int) 483 return IRQ_NONE; 484 485 dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT); 486 487 if (dev_int & TSI721_DEV_INT_SR2PC_CH) { 488 /* Service SR2PC Channel interrupts */ 489 if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) { 490 /* Service Inbound Doorbell interrupt */ 491 intval = ioread32(priv->regs + 492 TSI721_SR_CHINT(IDB_QUEUE)); 493 if (intval & TSI721_SR_CHINT_IDBQRCV) 494 tsi721_dbell_handler(priv); 495 else 496 tsi_info(&priv->pdev->dev, 497 "Unsupported SR_CH_INT %x", intval); 498 499 /* Clear interrupts */ 500 iowrite32(intval, 501 priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); 502 ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); 503 } 504 } 505 506 if (dev_int & TSI721_DEV_INT_SMSG_CH) { 507 int ch; 508 509 /* 510 * Service channel interrupts from Messaging Engine 511 */ 512 513 if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */ 514 /* Disable signaled OB MSG Channel interrupts */ 515 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 516 ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M); 517 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); 518 519 /* 520 * Process Inbound Message interrupt for each MBOX 521 */ 522 for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) { 523 if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch))) 524 continue; 525 tsi721_imsg_handler(priv, ch); 526 } 527 } 528 529 if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */ 530 /* Disable signaled OB MSG Channel interrupts */ 531 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 532 ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M); 533 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); 534 535 /* 536 * Process Outbound Message interrupts for each MBOX 537 */ 538 539 for (ch = 0; ch < RIO_MAX_MBOX; ch++) { 540 if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch))) 541 continue; 542 tsi721_omsg_handler(priv, ch); 543 } 544 } 545 } 546 547 if (dev_int & TSI721_DEV_INT_SRIO) { 548 /* Service SRIO MAC interrupts */ 549 intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT); 550 if (intval & TSI721_RIO_EM_INT_STAT_PW_RX) 551 tsi721_pw_handler(priv); 552 } 553 554#ifdef CONFIG_RAPIDIO_DMA_ENGINE 555 if (dev_int & TSI721_DEV_INT_BDMA_CH) { 556 int ch; 557 558 if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) { 559 tsi_debug(DMA, &priv->pdev->dev, 560 "IRQ from DMA channel 0x%08x", dev_ch_int); 561 562 for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) { 563 if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch))) 564 continue; 565 tsi721_bdma_handler(&priv->bdma[ch]); 566 } 567 } 568 } 569#endif 570 571 /* For MSI mode re-enable device-level interrupts */ 572 if (priv->flags & TSI721_USING_MSI) { 573 dev_int = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO | 574 TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH; 575 iowrite32(dev_int, priv->regs + TSI721_DEV_INTE); 576 } 577 578 return IRQ_HANDLED; 579} 580 581static void tsi721_interrupts_init(struct tsi721_device *priv) 582{ 583 u32 intr; 584 585 /* Enable IDB interrupts */ 586 iowrite32(TSI721_SR_CHINT_ALL, 587 priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); 588 iowrite32(TSI721_SR_CHINT_IDBQRCV, 589 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); 590 591 /* Enable SRIO MAC interrupts */ 592 iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT, 593 priv->regs + TSI721_RIO_EM_DEV_INT_EN); 594 595 /* Enable interrupts from channels in use */ 596#ifdef CONFIG_RAPIDIO_DMA_ENGINE 597 intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) | 598 (TSI721_INT_BDMA_CHAN_M & 599 ~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT)); 600#else 601 intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE); 602#endif 603 iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE); 604 605 if (priv->flags & TSI721_USING_MSIX) 606 intr = TSI721_DEV_INT_SRIO; 607 else 608 intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO | 609 TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH; 610 611 iowrite32(intr, priv->regs + TSI721_DEV_INTE); 612 ioread32(priv->regs + TSI721_DEV_INTE); 613} 614 615#ifdef CONFIG_PCI_MSI 616/** 617 * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging 618 * @irq: Linux interrupt number 619 * @ptr: Pointer to interrupt-specific data (tsi721_device structure) 620 * 621 * Handles outbound messaging interrupts signaled using MSI-X. 622 * 623 * Returns: %IRQ_HANDLED 624 */ 625static irqreturn_t tsi721_omsg_msix(int irq, void *ptr) 626{ 627 struct tsi721_device *priv = (struct tsi721_device *)ptr; 628 int mbox; 629 630 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX; 631 tsi721_omsg_handler(priv, mbox); 632 return IRQ_HANDLED; 633} 634 635/** 636 * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging 637 * @irq: Linux interrupt number 638 * @ptr: Pointer to interrupt-specific data (tsi721_device structure) 639 * 640 * Handles inbound messaging interrupts signaled using MSI-X. 641 * 642 * Returns: %IRQ_HANDLED 643 */ 644static irqreturn_t tsi721_imsg_msix(int irq, void *ptr) 645{ 646 struct tsi721_device *priv = (struct tsi721_device *)ptr; 647 int mbox; 648 649 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX; 650 tsi721_imsg_handler(priv, mbox + 4); 651 return IRQ_HANDLED; 652} 653 654/** 655 * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler 656 * @irq: Linux interrupt number 657 * @ptr: Pointer to interrupt-specific data (tsi721_device structure) 658 * 659 * Handles Tsi721 interrupts from SRIO MAC. 660 * 661 * Returns: %IRQ_HANDLED 662 */ 663static irqreturn_t tsi721_srio_msix(int irq, void *ptr) 664{ 665 struct tsi721_device *priv = (struct tsi721_device *)ptr; 666 u32 srio_int; 667 668 /* Service SRIO MAC interrupts */ 669 srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT); 670 if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX) 671 tsi721_pw_handler(priv); 672 673 return IRQ_HANDLED; 674} 675 676/** 677 * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler 678 * @irq: Linux interrupt number 679 * @ptr: Pointer to interrupt-specific data (tsi721_device structure) 680 * 681 * Handles Tsi721 interrupts from SR2PC Channel. 682 * NOTE: At this moment services only one SR2PC channel associated with inbound 683 * doorbells. 684 * 685 * Returns: %IRQ_HANDLED 686 */ 687static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr) 688{ 689 struct tsi721_device *priv = (struct tsi721_device *)ptr; 690 u32 sr_ch_int; 691 692 /* Service Inbound DB interrupt from SR2PC channel */ 693 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); 694 if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV) 695 tsi721_dbell_handler(priv); 696 697 /* Clear interrupts */ 698 iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); 699 /* Read back to ensure that interrupt was cleared */ 700 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); 701 702 return IRQ_HANDLED; 703} 704 705/** 706 * tsi721_request_msix - register interrupt service for MSI-X mode. 707 * @priv: tsi721 device-specific data structure 708 * 709 * Registers MSI-X interrupt service routines for interrupts that are active 710 * immediately after mport initialization. Messaging interrupt service routines 711 * should be registered during corresponding open requests. 712 * 713 * Returns: %0 on success or -errno value on failure. 714 */ 715static int tsi721_request_msix(struct tsi721_device *priv) 716{ 717 int err = 0; 718 719 err = request_irq(priv->msix[TSI721_VECT_IDB].vector, 720 tsi721_sr2pc_ch_msix, 0, 721 priv->msix[TSI721_VECT_IDB].irq_name, (void *)priv); 722 if (err) 723 return err; 724 725 err = request_irq(priv->msix[TSI721_VECT_PWRX].vector, 726 tsi721_srio_msix, 0, 727 priv->msix[TSI721_VECT_PWRX].irq_name, (void *)priv); 728 if (err) { 729 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv); 730 return err; 731 } 732 733 return 0; 734} 735 736/** 737 * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721. 738 * @priv: pointer to tsi721 private data 739 * 740 * Configures MSI-X support for Tsi721. Supports only an exact number 741 * of requested vectors. 742 * 743 * Returns: %0 on success or -errno value on failure. 744 */ 745static int tsi721_enable_msix(struct tsi721_device *priv) 746{ 747 struct msix_entry entries[TSI721_VECT_MAX]; 748 int err; 749 int i; 750 751 entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE); 752 entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT; 753 754 /* 755 * Initialize MSI-X entries for Messaging Engine: 756 * this driver supports four RIO mailboxes (inbound and outbound) 757 * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore 758 * offset +4 is added to IB MBOX number. 759 */ 760 for (i = 0; i < RIO_MAX_MBOX; i++) { 761 entries[TSI721_VECT_IMB0_RCV + i].entry = 762 TSI721_MSIX_IMSG_DQ_RCV(i + 4); 763 entries[TSI721_VECT_IMB0_INT + i].entry = 764 TSI721_MSIX_IMSG_INT(i + 4); 765 entries[TSI721_VECT_OMB0_DONE + i].entry = 766 TSI721_MSIX_OMSG_DONE(i); 767 entries[TSI721_VECT_OMB0_INT + i].entry = 768 TSI721_MSIX_OMSG_INT(i); 769 } 770 771#ifdef CONFIG_RAPIDIO_DMA_ENGINE 772 /* 773 * Initialize MSI-X entries for Block DMA Engine: 774 * this driver supports XXX DMA channels 775 * (one is reserved for SRIO maintenance transactions) 776 */ 777 for (i = 0; i < TSI721_DMA_CHNUM; i++) { 778 entries[TSI721_VECT_DMA0_DONE + i].entry = 779 TSI721_MSIX_DMACH_DONE(i); 780 entries[TSI721_VECT_DMA0_INT + i].entry = 781 TSI721_MSIX_DMACH_INT(i); 782 } 783#endif /* CONFIG_RAPIDIO_DMA_ENGINE */ 784 785 err = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries)); 786 if (err) { 787 tsi_err(&priv->pdev->dev, 788 "Failed to enable MSI-X (err=%d)", err); 789 return err; 790 } 791 792 /* 793 * Copy MSI-X vector information into tsi721 private structure 794 */ 795 priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector; 796 snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX, 797 DRV_NAME "-idb@pci:%s", pci_name(priv->pdev)); 798 priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector; 799 snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX, 800 DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev)); 801 802 for (i = 0; i < RIO_MAX_MBOX; i++) { 803 priv->msix[TSI721_VECT_IMB0_RCV + i].vector = 804 entries[TSI721_VECT_IMB0_RCV + i].vector; 805 snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name, 806 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s", 807 i, pci_name(priv->pdev)); 808 809 priv->msix[TSI721_VECT_IMB0_INT + i].vector = 810 entries[TSI721_VECT_IMB0_INT + i].vector; 811 snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name, 812 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s", 813 i, pci_name(priv->pdev)); 814 815 priv->msix[TSI721_VECT_OMB0_DONE + i].vector = 816 entries[TSI721_VECT_OMB0_DONE + i].vector; 817 snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name, 818 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s", 819 i, pci_name(priv->pdev)); 820 821 priv->msix[TSI721_VECT_OMB0_INT + i].vector = 822 entries[TSI721_VECT_OMB0_INT + i].vector; 823 snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name, 824 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s", 825 i, pci_name(priv->pdev)); 826 } 827 828#ifdef CONFIG_RAPIDIO_DMA_ENGINE 829 for (i = 0; i < TSI721_DMA_CHNUM; i++) { 830 priv->msix[TSI721_VECT_DMA0_DONE + i].vector = 831 entries[TSI721_VECT_DMA0_DONE + i].vector; 832 snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name, 833 IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s", 834 i, pci_name(priv->pdev)); 835 836 priv->msix[TSI721_VECT_DMA0_INT + i].vector = 837 entries[TSI721_VECT_DMA0_INT + i].vector; 838 snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name, 839 IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s", 840 i, pci_name(priv->pdev)); 841 } 842#endif /* CONFIG_RAPIDIO_DMA_ENGINE */ 843 844 return 0; 845} 846#endif /* CONFIG_PCI_MSI */ 847 848static int tsi721_request_irq(struct tsi721_device *priv) 849{ 850 int err; 851 852#ifdef CONFIG_PCI_MSI 853 if (priv->flags & TSI721_USING_MSIX) 854 err = tsi721_request_msix(priv); 855 else 856#endif 857 err = request_irq(priv->pdev->irq, tsi721_irqhandler, 858 (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED, 859 DRV_NAME, (void *)priv); 860 861 if (err) 862 tsi_err(&priv->pdev->dev, 863 "Unable to allocate interrupt, err=%d", err); 864 865 return err; 866} 867 868static void tsi721_free_irq(struct tsi721_device *priv) 869{ 870#ifdef CONFIG_PCI_MSI 871 if (priv->flags & TSI721_USING_MSIX) { 872 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv); 873 free_irq(priv->msix[TSI721_VECT_PWRX].vector, (void *)priv); 874 } else 875#endif 876 free_irq(priv->pdev->irq, (void *)priv); 877} 878 879static int 880tsi721_obw_alloc(struct tsi721_device *priv, struct tsi721_obw_bar *pbar, 881 u32 size, int *win_id) 882{ 883 u64 win_base; 884 u64 bar_base; 885 u64 bar_end; 886 u32 align; 887 struct tsi721_ob_win *win; 888 struct tsi721_ob_win *new_win = NULL; 889 int new_win_idx = -1; 890 int i = 0; 891 892 bar_base = pbar->base; 893 bar_end = bar_base + pbar->size; 894 win_base = bar_base; 895 align = size/TSI721_PC2SR_ZONES; 896 897 while (i < TSI721_IBWIN_NUM) { 898 for (i = 0; i < TSI721_IBWIN_NUM; i++) { 899 if (!priv->ob_win[i].active) { 900 if (new_win == NULL) { 901 new_win = &priv->ob_win[i]; 902 new_win_idx = i; 903 } 904 continue; 905 } 906 907 /* 908 * If this window belongs to the current BAR check it 909 * for overlap 910 */ 911 win = &priv->ob_win[i]; 912 913 if (win->base >= bar_base && win->base < bar_end) { 914 if (win_base < (win->base + win->size) && 915 (win_base + size) > win->base) { 916 /* Overlap detected */ 917 win_base = win->base + win->size; 918 win_base = ALIGN(win_base, align); 919 break; 920 } 921 } 922 } 923 } 924 925 if (win_base + size > bar_end) 926 return -ENOMEM; 927 928 if (!new_win) { 929 tsi_err(&priv->pdev->dev, "OBW count tracking failed"); 930 return -EIO; 931 } 932 933 new_win->active = true; 934 new_win->base = win_base; 935 new_win->size = size; 936 new_win->pbar = pbar; 937 priv->obwin_cnt--; 938 pbar->free -= size; 939 *win_id = new_win_idx; 940 return 0; 941} 942 943static int tsi721_map_outb_win(struct rio_mport *mport, u16 destid, u64 rstart, 944 u32 size, u32 flags, dma_addr_t *laddr) 945{ 946 struct tsi721_device *priv = mport->priv; 947 int i; 948 struct tsi721_obw_bar *pbar; 949 struct tsi721_ob_win *ob_win; 950 int obw = -1; 951 u32 rval; 952 u64 rio_addr; 953 u32 zsize; 954 int ret = -ENOMEM; 955 956 tsi_debug(OBW, &priv->pdev->dev, 957 "did=%d ra=0x%llx sz=0x%x", destid, rstart, size); 958 959 if (!is_power_of_2(size) || (size < 0x8000) || (rstart & (size - 1))) 960 return -EINVAL; 961 962 if (priv->obwin_cnt == 0) 963 return -EBUSY; 964 965 for (i = 0; i < 2; i++) { 966 if (priv->p2r_bar[i].free >= size) { 967 pbar = &priv->p2r_bar[i]; 968 ret = tsi721_obw_alloc(priv, pbar, size, &obw); 969 if (!ret) 970 break; 971 } 972 } 973 974 if (ret) 975 return ret; 976 977 WARN_ON(obw == -1); 978 ob_win = &priv->ob_win[obw]; 979 ob_win->destid = destid; 980 ob_win->rstart = rstart; 981 tsi_debug(OBW, &priv->pdev->dev, 982 "allocated OBW%d @%llx", obw, ob_win->base); 983 984 /* 985 * Configure Outbound Window 986 */ 987 988 zsize = size/TSI721_PC2SR_ZONES; 989 rio_addr = rstart; 990 991 /* 992 * Program Address Translation Zones: 993 * This implementation uses all 8 zones associated wit window. 994 */ 995 for (i = 0; i < TSI721_PC2SR_ZONES; i++) { 996 997 while (ioread32(priv->regs + TSI721_ZONE_SEL) & 998 TSI721_ZONE_SEL_GO) { 999 udelay(1); 1000 } 1001 1002 rval = (u32)(rio_addr & TSI721_LUT_DATA0_ADD) | 1003 TSI721_LUT_DATA0_NREAD | TSI721_LUT_DATA0_NWR; 1004 iowrite32(rval, priv->regs + TSI721_LUT_DATA0); 1005 rval = (u32)(rio_addr >> 32); 1006 iowrite32(rval, priv->regs + TSI721_LUT_DATA1); 1007 rval = destid; 1008 iowrite32(rval, priv->regs + TSI721_LUT_DATA2); 1009 1010 rval = TSI721_ZONE_SEL_GO | (obw << 3) | i; 1011 iowrite32(rval, priv->regs + TSI721_ZONE_SEL); 1012 1013 rio_addr += zsize; 1014 } 1015 1016 iowrite32(TSI721_OBWIN_SIZE(size) << 8, 1017 priv->regs + TSI721_OBWINSZ(obw)); 1018 iowrite32((u32)(ob_win->base >> 32), priv->regs + TSI721_OBWINUB(obw)); 1019 iowrite32((u32)(ob_win->base & TSI721_OBWINLB_BA) | TSI721_OBWINLB_WEN, 1020 priv->regs + TSI721_OBWINLB(obw)); 1021 1022 *laddr = ob_win->base; 1023 return 0; 1024} 1025 1026static void tsi721_unmap_outb_win(struct rio_mport *mport, 1027 u16 destid, u64 rstart) 1028{ 1029 struct tsi721_device *priv = mport->priv; 1030 struct tsi721_ob_win *ob_win; 1031 int i; 1032 1033 tsi_debug(OBW, &priv->pdev->dev, "did=%d ra=0x%llx", destid, rstart); 1034 1035 for (i = 0; i < TSI721_OBWIN_NUM; i++) { 1036 ob_win = &priv->ob_win[i]; 1037 1038 if (ob_win->active && 1039 ob_win->destid == destid && ob_win->rstart == rstart) { 1040 tsi_debug(OBW, &priv->pdev->dev, 1041 "free OBW%d @%llx", i, ob_win->base); 1042 ob_win->active = false; 1043 iowrite32(0, priv->regs + TSI721_OBWINLB(i)); 1044 ob_win->pbar->free += ob_win->size; 1045 priv->obwin_cnt++; 1046 break; 1047 } 1048 } 1049} 1050 1051/** 1052 * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO) 1053 * translation regions. 1054 * @priv: pointer to tsi721 private data 1055 * 1056 * Disables SREP translation regions. 1057 */ 1058static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv) 1059{ 1060 int i, z; 1061 u32 rval; 1062 1063 /* Disable all PC2SR translation windows */ 1064 for (i = 0; i < TSI721_OBWIN_NUM; i++) 1065 iowrite32(0, priv->regs + TSI721_OBWINLB(i)); 1066 1067 /* Initialize zone lookup tables to avoid ECC errors on reads */ 1068 iowrite32(0, priv->regs + TSI721_LUT_DATA0); 1069 iowrite32(0, priv->regs + TSI721_LUT_DATA1); 1070 iowrite32(0, priv->regs + TSI721_LUT_DATA2); 1071 1072 for (i = 0; i < TSI721_OBWIN_NUM; i++) { 1073 for (z = 0; z < TSI721_PC2SR_ZONES; z++) { 1074 while (ioread32(priv->regs + TSI721_ZONE_SEL) & 1075 TSI721_ZONE_SEL_GO) { 1076 udelay(1); 1077 } 1078 rval = TSI721_ZONE_SEL_GO | (i << 3) | z; 1079 iowrite32(rval, priv->regs + TSI721_ZONE_SEL); 1080 } 1081 } 1082 1083 if (priv->p2r_bar[0].size == 0 && priv->p2r_bar[1].size == 0) { 1084 priv->obwin_cnt = 0; 1085 return; 1086 } 1087 1088 priv->p2r_bar[0].free = priv->p2r_bar[0].size; 1089 priv->p2r_bar[1].free = priv->p2r_bar[1].size; 1090 1091 for (i = 0; i < TSI721_OBWIN_NUM; i++) 1092 priv->ob_win[i].active = false; 1093 1094 priv->obwin_cnt = TSI721_OBWIN_NUM; 1095} 1096 1097/** 1098 * tsi721_rio_map_inb_mem -- Mapping inbound memory region. 1099 * @mport: RapidIO master port 1100 * @lstart: Local memory space start address. 1101 * @rstart: RapidIO space start address. 1102 * @size: The mapping region size. 1103 * @flags: Flags for mapping. 0 for using default flags. 1104 * 1105 * Return: 0 -- Success. 1106 * 1107 * This function will create the inbound mapping 1108 * from rstart to lstart. 1109 */ 1110static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart, 1111 u64 rstart, u64 size, u32 flags) 1112{ 1113 struct tsi721_device *priv = mport->priv; 1114 int i, avail = -1; 1115 u32 regval; 1116 struct tsi721_ib_win *ib_win; 1117 bool direct = (lstart == rstart); 1118 u64 ibw_size; 1119 dma_addr_t loc_start; 1120 u64 ibw_start; 1121 struct tsi721_ib_win_mapping *map = NULL; 1122 int ret = -EBUSY; 1123 1124 /* Max IBW size supported by HW is 16GB */ 1125 if (size > 0x400000000UL) 1126 return -EINVAL; 1127 1128 if (direct) { 1129 /* Calculate minimal acceptable window size and base address */ 1130 1131 ibw_size = roundup_pow_of_two(size); 1132 ibw_start = lstart & ~(ibw_size - 1); 1133 1134 tsi_debug(IBW, &priv->pdev->dev, 1135 "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%llx, ibw_start = 0x%llx", 1136 rstart, &lstart, size, ibw_start); 1137 1138 while ((lstart + size) > (ibw_start + ibw_size)) { 1139 ibw_size *= 2; 1140 ibw_start = lstart & ~(ibw_size - 1); 1141 /* Check for crossing IBW max size 16GB */ 1142 if (ibw_size > 0x400000000UL) 1143 return -EBUSY; 1144 } 1145 1146 loc_start = ibw_start; 1147 1148 map = kzalloc(sizeof(struct tsi721_ib_win_mapping), GFP_ATOMIC); 1149 if (map == NULL) 1150 return -ENOMEM; 1151 1152 } else { 1153 tsi_debug(IBW, &priv->pdev->dev, 1154 "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%llx", 1155 rstart, &lstart, size); 1156 1157 if (!is_power_of_2(size) || size < 0x1000 || 1158 ((u64)lstart & (size - 1)) || (rstart & (size - 1))) 1159 return -EINVAL; 1160 if (priv->ibwin_cnt == 0) 1161 return -EBUSY; 1162 ibw_start = rstart; 1163 ibw_size = size; 1164 loc_start = lstart; 1165 } 1166 1167 /* 1168 * Scan for overlapping with active regions and mark the first available 1169 * IB window at the same time. 1170 */ 1171 for (i = 0; i < TSI721_IBWIN_NUM; i++) { 1172 ib_win = &priv->ib_win[i]; 1173 1174 if (!ib_win->active) { 1175 if (avail == -1) { 1176 avail = i; 1177 ret = 0; 1178 } 1179 } else if (ibw_start < (ib_win->rstart + ib_win->size) && 1180 (ibw_start + ibw_size) > ib_win->rstart) { 1181 /* Return error if address translation involved */ 1182 if (!direct || ib_win->xlat) { 1183 ret = -EFAULT; 1184 break; 1185 } 1186 1187 /* 1188 * Direct mappings usually are larger than originally 1189 * requested fragments - check if this new request fits 1190 * into it. 1191 */ 1192 if (rstart >= ib_win->rstart && 1193 (rstart + size) <= (ib_win->rstart + 1194 ib_win->size)) { 1195 /* We are in - no further mapping required */ 1196 map->lstart = lstart; 1197 list_add_tail(&map->node, &ib_win->mappings); 1198 return 0; 1199 } 1200 1201 ret = -EFAULT; 1202 break; 1203 } 1204 } 1205 1206 if (ret) 1207 goto out; 1208 i = avail; 1209 1210 /* Sanity check: available IB window must be disabled at this point */ 1211 regval = ioread32(priv->regs + TSI721_IBWIN_LB(i)); 1212 if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) { 1213 ret = -EIO; 1214 goto out; 1215 } 1216 1217 ib_win = &priv->ib_win[i]; 1218 ib_win->active = true; 1219 ib_win->rstart = ibw_start; 1220 ib_win->lstart = loc_start; 1221 ib_win->size = ibw_size; 1222 ib_win->xlat = (lstart != rstart); 1223 INIT_LIST_HEAD(&ib_win->mappings); 1224 1225 /* 1226 * When using direct IBW mapping and have larger than requested IBW size 1227 * we can have multiple local memory blocks mapped through the same IBW 1228 * To handle this situation we maintain list of "clients" for such IBWs. 1229 */ 1230 if (direct) { 1231 map->lstart = lstart; 1232 list_add_tail(&map->node, &ib_win->mappings); 1233 } 1234 1235 iowrite32(TSI721_IBWIN_SIZE(ibw_size) << 8, 1236 priv->regs + TSI721_IBWIN_SZ(i)); 1237 1238 iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i)); 1239 iowrite32(((u64)loc_start & TSI721_IBWIN_TLA_ADD), 1240 priv->regs + TSI721_IBWIN_TLA(i)); 1241 1242 iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i)); 1243 iowrite32((ibw_start & TSI721_IBWIN_LB_BA) | TSI721_IBWIN_LB_WEN, 1244 priv->regs + TSI721_IBWIN_LB(i)); 1245 1246 priv->ibwin_cnt--; 1247 1248 tsi_debug(IBW, &priv->pdev->dev, 1249 "Configured IBWIN%d (RIO_0x%llx -> PCIe_%pad), size=0x%llx", 1250 i, ibw_start, &loc_start, ibw_size); 1251 1252 return 0; 1253out: 1254 kfree(map); 1255 return ret; 1256} 1257 1258/** 1259 * tsi721_rio_unmap_inb_mem -- Unmapping inbound memory region. 1260 * @mport: RapidIO master port 1261 * @lstart: Local memory space start address. 1262 */ 1263static void tsi721_rio_unmap_inb_mem(struct rio_mport *mport, 1264 dma_addr_t lstart) 1265{ 1266 struct tsi721_device *priv = mport->priv; 1267 struct tsi721_ib_win *ib_win; 1268 int i; 1269 1270 tsi_debug(IBW, &priv->pdev->dev, 1271 "Unmap IBW mapped to PCIe_%pad", &lstart); 1272 1273 /* Search for matching active inbound translation window */ 1274 for (i = 0; i < TSI721_IBWIN_NUM; i++) { 1275 ib_win = &priv->ib_win[i]; 1276 1277 /* Address translating IBWs must to be an exact march */ 1278 if (!ib_win->active || 1279 (ib_win->xlat && lstart != ib_win->lstart)) 1280 continue; 1281 1282 if (lstart >= ib_win->lstart && 1283 lstart < (ib_win->lstart + ib_win->size)) { 1284 1285 if (!ib_win->xlat) { 1286 struct tsi721_ib_win_mapping *map; 1287 int found = 0; 1288 1289 list_for_each_entry(map, 1290 &ib_win->mappings, node) { 1291 if (map->lstart == lstart) { 1292 list_del(&map->node); 1293 kfree(map); 1294 found = 1; 1295 break; 1296 } 1297 } 1298 1299 if (!found) 1300 continue; 1301 1302 if (!list_empty(&ib_win->mappings)) 1303 break; 1304 } 1305 1306 tsi_debug(IBW, &priv->pdev->dev, "Disable IBWIN_%d", i); 1307 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); 1308 ib_win->active = false; 1309 priv->ibwin_cnt++; 1310 break; 1311 } 1312 } 1313 1314 if (i == TSI721_IBWIN_NUM) 1315 tsi_debug(IBW, &priv->pdev->dev, 1316 "IB window mapped to %pad not found", &lstart); 1317} 1318 1319/** 1320 * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe) 1321 * translation regions. 1322 * @priv: pointer to tsi721 private data 1323 * 1324 * Disables inbound windows. 1325 */ 1326static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv) 1327{ 1328 int i; 1329 1330 /* Disable all SR2PC inbound windows */ 1331 for (i = 0; i < TSI721_IBWIN_NUM; i++) 1332 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); 1333 priv->ibwin_cnt = TSI721_IBWIN_NUM; 1334} 1335 1336/* 1337 * tsi721_close_sr2pc_mapping - closes all active inbound (SRIO->PCIe) 1338 * translation regions. 1339 * @priv: pointer to tsi721 device private data 1340 */ 1341static void tsi721_close_sr2pc_mapping(struct tsi721_device *priv) 1342{ 1343 struct tsi721_ib_win *ib_win; 1344 int i; 1345 1346 /* Disable all active SR2PC inbound windows */ 1347 for (i = 0; i < TSI721_IBWIN_NUM; i++) { 1348 ib_win = &priv->ib_win[i]; 1349 if (ib_win->active) { 1350 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); 1351 ib_win->active = false; 1352 } 1353 } 1354} 1355 1356/** 1357 * tsi721_port_write_init - Inbound port write interface init 1358 * @priv: pointer to tsi721 private data 1359 * 1360 * Initializes inbound port write handler. 1361 * Returns: %0 on success or %-ENOMEM on failure. 1362 */ 1363static int tsi721_port_write_init(struct tsi721_device *priv) 1364{ 1365 priv->pw_discard_count = 0; 1366 INIT_WORK(&priv->pw_work, tsi721_pw_dpc); 1367 spin_lock_init(&priv->pw_fifo_lock); 1368 if (kfifo_alloc(&priv->pw_fifo, 1369 TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { 1370 tsi_err(&priv->pdev->dev, "PW FIFO allocation failed"); 1371 return -ENOMEM; 1372 } 1373 1374 /* Use reliable port-write capture mode */ 1375 iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL); 1376 return 0; 1377} 1378 1379static void tsi721_port_write_free(struct tsi721_device *priv) 1380{ 1381 kfifo_free(&priv->pw_fifo); 1382} 1383 1384static int tsi721_doorbell_init(struct tsi721_device *priv) 1385{ 1386 /* Outbound Doorbells do not require any setup. 1387 * Tsi721 uses dedicated PCI BAR1 to generate doorbells. 1388 * That BAR1 was mapped during the probe routine. 1389 */ 1390 1391 /* Initialize Inbound Doorbell processing DPC and queue */ 1392 priv->db_discard_count = 0; 1393 INIT_WORK(&priv->idb_work, tsi721_db_dpc); 1394 1395 /* Allocate buffer for inbound doorbells queue */ 1396 priv->idb_base = dma_alloc_coherent(&priv->pdev->dev, 1397 IDB_QSIZE * TSI721_IDB_ENTRY_SIZE, 1398 &priv->idb_dma, GFP_KERNEL); 1399 if (!priv->idb_base) 1400 return -ENOMEM; 1401 1402 tsi_debug(DBELL, &priv->pdev->dev, 1403 "Allocated IDB buffer @ %p (phys = %pad)", 1404 priv->idb_base, &priv->idb_dma); 1405 1406 iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE), 1407 priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE)); 1408 iowrite32(((u64)priv->idb_dma >> 32), 1409 priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE)); 1410 iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR), 1411 priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE)); 1412 /* Enable accepting all inbound doorbells */ 1413 iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE)); 1414 1415 iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE)); 1416 1417 iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); 1418 1419 return 0; 1420} 1421 1422static void tsi721_doorbell_free(struct tsi721_device *priv) 1423{ 1424 if (priv->idb_base == NULL) 1425 return; 1426 1427 /* Free buffer allocated for inbound doorbell queue */ 1428 dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE, 1429 priv->idb_base, priv->idb_dma); 1430 priv->idb_base = NULL; 1431} 1432 1433/** 1434 * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel. 1435 * @priv: pointer to tsi721 private data 1436 * 1437 * Initialize BDMA channel allocated for RapidIO maintenance read/write 1438 * request generation 1439 * 1440 * Returns: %0 on success or %-ENOMEM on failure. 1441 */ 1442static int tsi721_bdma_maint_init(struct tsi721_device *priv) 1443{ 1444 struct tsi721_dma_desc *bd_ptr; 1445 u64 *sts_ptr; 1446 dma_addr_t bd_phys, sts_phys; 1447 int sts_size; 1448 int bd_num = 2; 1449 void __iomem *regs; 1450 1451 tsi_debug(MAINT, &priv->pdev->dev, 1452 "Init BDMA_%d Maintenance requests", TSI721_DMACH_MAINT); 1453 1454 /* 1455 * Initialize DMA channel for maintenance requests 1456 */ 1457 1458 priv->mdma.ch_id = TSI721_DMACH_MAINT; 1459 regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT); 1460 1461 /* Allocate space for DMA descriptors */ 1462 bd_ptr = dma_alloc_coherent(&priv->pdev->dev, 1463 bd_num * sizeof(struct tsi721_dma_desc), 1464 &bd_phys, GFP_KERNEL); 1465 if (!bd_ptr) 1466 return -ENOMEM; 1467 1468 priv->mdma.bd_num = bd_num; 1469 priv->mdma.bd_phys = bd_phys; 1470 priv->mdma.bd_base = bd_ptr; 1471 1472 tsi_debug(MAINT, &priv->pdev->dev, "DMA descriptors @ %p (phys = %pad)", 1473 bd_ptr, &bd_phys); 1474 1475 /* Allocate space for descriptor status FIFO */ 1476 sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ? 1477 bd_num : TSI721_DMA_MINSTSSZ; 1478 sts_size = roundup_pow_of_two(sts_size); 1479 sts_ptr = dma_alloc_coherent(&priv->pdev->dev, 1480 sts_size * sizeof(struct tsi721_dma_sts), 1481 &sts_phys, GFP_KERNEL); 1482 if (!sts_ptr) { 1483 /* Free space allocated for DMA descriptors */ 1484 dma_free_coherent(&priv->pdev->dev, 1485 bd_num * sizeof(struct tsi721_dma_desc), 1486 bd_ptr, bd_phys); 1487 priv->mdma.bd_base = NULL; 1488 return -ENOMEM; 1489 } 1490 1491 priv->mdma.sts_phys = sts_phys; 1492 priv->mdma.sts_base = sts_ptr; 1493 priv->mdma.sts_size = sts_size; 1494 1495 tsi_debug(MAINT, &priv->pdev->dev, 1496 "desc status FIFO @ %p (phys = %pad) size=0x%x", 1497 sts_ptr, &sts_phys, sts_size); 1498 1499 /* Initialize DMA descriptors ring */ 1500 bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29); 1501 bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys & 1502 TSI721_DMAC_DPTRL_MASK); 1503 bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32); 1504 1505 /* Setup DMA descriptor pointers */ 1506 iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH); 1507 iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK), 1508 regs + TSI721_DMAC_DPTRL); 1509 1510 /* Setup descriptor status FIFO */ 1511 iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH); 1512 iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK), 1513 regs + TSI721_DMAC_DSBL); 1514 iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size), 1515 regs + TSI721_DMAC_DSSZ); 1516 1517 /* Clear interrupt bits */ 1518 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT); 1519 1520 ioread32(regs + TSI721_DMAC_INT); 1521 1522 /* Toggle DMA channel initialization */ 1523 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); 1524 ioread32(regs + TSI721_DMAC_CTL); 1525 udelay(10); 1526 1527 return 0; 1528} 1529 1530static int tsi721_bdma_maint_free(struct tsi721_device *priv) 1531{ 1532 u32 ch_stat; 1533 struct tsi721_bdma_maint *mdma = &priv->mdma; 1534 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id); 1535 1536 if (mdma->bd_base == NULL) 1537 return 0; 1538 1539 /* Check if DMA channel still running */ 1540 ch_stat = ioread32(regs + TSI721_DMAC_STS); 1541 if (ch_stat & TSI721_DMAC_STS_RUN) 1542 return -EFAULT; 1543 1544 /* Put DMA channel into init state */ 1545 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL); 1546 1547 /* Free space allocated for DMA descriptors */ 1548 dma_free_coherent(&priv->pdev->dev, 1549 mdma->bd_num * sizeof(struct tsi721_dma_desc), 1550 mdma->bd_base, mdma->bd_phys); 1551 mdma->bd_base = NULL; 1552 1553 /* Free space allocated for status FIFO */ 1554 dma_free_coherent(&priv->pdev->dev, 1555 mdma->sts_size * sizeof(struct tsi721_dma_sts), 1556 mdma->sts_base, mdma->sts_phys); 1557 mdma->sts_base = NULL; 1558 return 0; 1559} 1560 1561/* Enable Inbound Messaging Interrupts */ 1562static void 1563tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch, 1564 u32 inte_mask) 1565{ 1566 u32 rval; 1567 1568 if (!inte_mask) 1569 return; 1570 1571 /* Clear pending Inbound Messaging interrupts */ 1572 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch)); 1573 1574 /* Enable Inbound Messaging interrupts */ 1575 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch)); 1576 iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch)); 1577 1578 if (priv->flags & TSI721_USING_MSIX) 1579 return; /* Finished if we are in MSI-X mode */ 1580 1581 /* 1582 * For MSI and INTA interrupt signalling we need to enable next levels 1583 */ 1584 1585 /* Enable Device Channel Interrupt */ 1586 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 1587 iowrite32(rval | TSI721_INT_IMSG_CHAN(ch), 1588 priv->regs + TSI721_DEV_CHAN_INTE); 1589} 1590 1591/* Disable Inbound Messaging Interrupts */ 1592static void 1593tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch, 1594 u32 inte_mask) 1595{ 1596 u32 rval; 1597 1598 if (!inte_mask) 1599 return; 1600 1601 /* Clear pending Inbound Messaging interrupts */ 1602 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch)); 1603 1604 /* Disable Inbound Messaging interrupts */ 1605 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch)); 1606 rval &= ~inte_mask; 1607 iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch)); 1608 1609 if (priv->flags & TSI721_USING_MSIX) 1610 return; /* Finished if we are in MSI-X mode */ 1611 1612 /* 1613 * For MSI and INTA interrupt signalling we need to disable next levels 1614 */ 1615 1616 /* Disable Device Channel Interrupt */ 1617 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 1618 rval &= ~TSI721_INT_IMSG_CHAN(ch); 1619 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE); 1620} 1621 1622/* Enable Outbound Messaging interrupts */ 1623static void 1624tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch, 1625 u32 inte_mask) 1626{ 1627 u32 rval; 1628 1629 if (!inte_mask) 1630 return; 1631 1632 /* Clear pending Outbound Messaging interrupts */ 1633 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch)); 1634 1635 /* Enable Outbound Messaging channel interrupts */ 1636 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch)); 1637 iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch)); 1638 1639 if (priv->flags & TSI721_USING_MSIX) 1640 return; /* Finished if we are in MSI-X mode */ 1641 1642 /* 1643 * For MSI and INTA interrupt signalling we need to enable next levels 1644 */ 1645 1646 /* Enable Device Channel Interrupt */ 1647 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 1648 iowrite32(rval | TSI721_INT_OMSG_CHAN(ch), 1649 priv->regs + TSI721_DEV_CHAN_INTE); 1650} 1651 1652/* Disable Outbound Messaging interrupts */ 1653static void 1654tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch, 1655 u32 inte_mask) 1656{ 1657 u32 rval; 1658 1659 if (!inte_mask) 1660 return; 1661 1662 /* Clear pending Outbound Messaging interrupts */ 1663 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch)); 1664 1665 /* Disable Outbound Messaging interrupts */ 1666 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch)); 1667 rval &= ~inte_mask; 1668 iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch)); 1669 1670 if (priv->flags & TSI721_USING_MSIX) 1671 return; /* Finished if we are in MSI-X mode */ 1672 1673 /* 1674 * For MSI and INTA interrupt signalling we need to disable next levels 1675 */ 1676 1677 /* Disable Device Channel Interrupt */ 1678 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 1679 rval &= ~TSI721_INT_OMSG_CHAN(ch); 1680 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE); 1681} 1682 1683/** 1684 * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue 1685 * @mport: Master port with outbound message queue 1686 * @rdev: Target of outbound message 1687 * @mbox: Outbound mailbox 1688 * @buffer: Message to add to outbound queue 1689 * @len: Length of message 1690 * 1691 * Returns: %0 on success or -errno value on failure. 1692 */ 1693static int 1694tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, 1695 void *buffer, size_t len) 1696{ 1697 struct tsi721_device *priv = mport->priv; 1698 struct tsi721_omsg_desc *desc; 1699 u32 tx_slot; 1700 unsigned long flags; 1701 1702 if (!priv->omsg_init[mbox] || 1703 len > TSI721_MSG_MAX_SIZE || len < 8) 1704 return -EINVAL; 1705 1706 spin_lock_irqsave(&priv->omsg_ring[mbox].lock, flags); 1707 1708 tx_slot = priv->omsg_ring[mbox].tx_slot; 1709 1710 /* Copy copy message into transfer buffer */ 1711 memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len); 1712 1713 if (len & 0x7) 1714 len += 8; 1715 1716 /* Build descriptor associated with buffer */ 1717 desc = priv->omsg_ring[mbox].omd_base; 1718 desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid); 1719#ifdef TSI721_OMSG_DESC_INT 1720 /* Request IOF_DONE interrupt generation for each N-th frame in queue */ 1721 if (tx_slot % 4 == 0) 1722 desc[tx_slot].type_id |= cpu_to_le32(TSI721_OMD_IOF); 1723#endif 1724 desc[tx_slot].msg_info = 1725 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) | 1726 (0xe << 12) | (len & 0xff8)); 1727 desc[tx_slot].bufptr_lo = 1728 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] & 1729 0xffffffff); 1730 desc[tx_slot].bufptr_hi = 1731 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32); 1732 1733 priv->omsg_ring[mbox].wr_count++; 1734 1735 /* Go to next descriptor */ 1736 if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) { 1737 priv->omsg_ring[mbox].tx_slot = 0; 1738 /* Move through the ring link descriptor at the end */ 1739 priv->omsg_ring[mbox].wr_count++; 1740 } 1741 1742 mb(); 1743 1744 /* Set new write count value */ 1745 iowrite32(priv->omsg_ring[mbox].wr_count, 1746 priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); 1747 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); 1748 1749 spin_unlock_irqrestore(&priv->omsg_ring[mbox].lock, flags); 1750 1751 return 0; 1752} 1753 1754/** 1755 * tsi721_omsg_handler - Outbound Message Interrupt Handler 1756 * @priv: pointer to tsi721 private data 1757 * @ch: number of OB MSG channel to service 1758 * 1759 * Services channel interrupts from outbound messaging engine. 1760 */ 1761static void tsi721_omsg_handler(struct tsi721_device *priv, int ch) 1762{ 1763 u32 omsg_int; 1764 struct rio_mport *mport = &priv->mport; 1765 void *dev_id = NULL; 1766 u32 tx_slot = 0xffffffff; 1767 int do_callback = 0; 1768 1769 spin_lock(&priv->omsg_ring[ch].lock); 1770 1771 omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch)); 1772 1773 if (omsg_int & TSI721_OBDMAC_INT_ST_FULL) 1774 tsi_info(&priv->pdev->dev, 1775 "OB MBOX%d: Status FIFO is full", ch); 1776 1777 if (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) { 1778 u32 srd_ptr; 1779 u64 *sts_ptr, last_ptr = 0, prev_ptr = 0; 1780 int i, j; 1781 1782 /* 1783 * Find last successfully processed descriptor 1784 */ 1785 1786 /* Check and clear descriptor status FIFO entries */ 1787 srd_ptr = priv->omsg_ring[ch].sts_rdptr; 1788 sts_ptr = priv->omsg_ring[ch].sts_base; 1789 j = srd_ptr * 8; 1790 while (sts_ptr[j]) { 1791 for (i = 0; i < 8 && sts_ptr[j]; i++, j++) { 1792 prev_ptr = last_ptr; 1793 last_ptr = le64_to_cpu(sts_ptr[j]); 1794 sts_ptr[j] = 0; 1795 } 1796 1797 ++srd_ptr; 1798 srd_ptr %= priv->omsg_ring[ch].sts_size; 1799 j = srd_ptr * 8; 1800 } 1801 1802 if (last_ptr == 0) 1803 goto no_sts_update; 1804 1805 priv->omsg_ring[ch].sts_rdptr = srd_ptr; 1806 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch)); 1807 1808 if (!mport->outb_msg[ch].mcback) 1809 goto no_sts_update; 1810 1811 /* Inform upper layer about transfer completion */ 1812 1813 tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/ 1814 sizeof(struct tsi721_omsg_desc); 1815 1816 /* 1817 * Check if this is a Link Descriptor (LD). 1818 * If yes, ignore LD and use descriptor processed 1819 * before LD. 1820 */ 1821 if (tx_slot == priv->omsg_ring[ch].size) { 1822 if (prev_ptr) 1823 tx_slot = (prev_ptr - 1824 (u64)priv->omsg_ring[ch].omd_phys)/ 1825 sizeof(struct tsi721_omsg_desc); 1826 else 1827 goto no_sts_update; 1828 } 1829 1830 if (tx_slot >= priv->omsg_ring[ch].size) 1831 tsi_debug(OMSG, &priv->pdev->dev, 1832 "OB_MSG tx_slot=%x > size=%x", 1833 tx_slot, priv->omsg_ring[ch].size); 1834 WARN_ON(tx_slot >= priv->omsg_ring[ch].size); 1835 1836 /* Move slot index to the next message to be sent */ 1837 ++tx_slot; 1838 if (tx_slot == priv->omsg_ring[ch].size) 1839 tx_slot = 0; 1840 1841 dev_id = priv->omsg_ring[ch].dev_id; 1842 do_callback = 1; 1843 } 1844 1845no_sts_update: 1846 1847 if (omsg_int & TSI721_OBDMAC_INT_ERROR) { 1848 /* 1849 * Outbound message operation aborted due to error, 1850 * reinitialize OB MSG channel 1851 */ 1852 1853 tsi_debug(OMSG, &priv->pdev->dev, "OB MSG ABORT ch_stat=%x", 1854 ioread32(priv->regs + TSI721_OBDMAC_STS(ch))); 1855 1856 iowrite32(TSI721_OBDMAC_INT_ERROR, 1857 priv->regs + TSI721_OBDMAC_INT(ch)); 1858 iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT, 1859 priv->regs + TSI721_OBDMAC_CTL(ch)); 1860 ioread32(priv->regs + TSI721_OBDMAC_CTL(ch)); 1861 1862 /* Inform upper level to clear all pending tx slots */ 1863 dev_id = priv->omsg_ring[ch].dev_id; 1864 tx_slot = priv->omsg_ring[ch].tx_slot; 1865 do_callback = 1; 1866 1867 /* Synch tx_slot tracking */ 1868 iowrite32(priv->omsg_ring[ch].tx_slot, 1869 priv->regs + TSI721_OBDMAC_DRDCNT(ch)); 1870 ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch)); 1871 priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot; 1872 priv->omsg_ring[ch].sts_rdptr = 0; 1873 } 1874 1875 /* Clear channel interrupts */ 1876 iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch)); 1877 1878 if (!(priv->flags & TSI721_USING_MSIX)) { 1879 u32 ch_inte; 1880 1881 /* Re-enable channel interrupts */ 1882 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 1883 ch_inte |= TSI721_INT_OMSG_CHAN(ch); 1884 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); 1885 } 1886 1887 spin_unlock(&priv->omsg_ring[ch].lock); 1888 1889 if (mport->outb_msg[ch].mcback && do_callback) 1890 mport->outb_msg[ch].mcback(mport, dev_id, ch, tx_slot); 1891} 1892 1893/** 1894 * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox 1895 * @mport: Master port implementing Outbound Messaging Engine 1896 * @dev_id: Device specific pointer to pass on event 1897 * @mbox: Mailbox to open 1898 * @entries: Number of entries in the outbound mailbox ring 1899 * 1900 * Returns: %0 on success or -errno value on failure. 1901 */ 1902static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id, 1903 int mbox, int entries) 1904{ 1905 struct tsi721_device *priv = mport->priv; 1906 struct tsi721_omsg_desc *bd_ptr; 1907 int i, rc = 0; 1908 1909 if ((entries < TSI721_OMSGD_MIN_RING_SIZE) || 1910 (entries > (TSI721_OMSGD_RING_SIZE)) || 1911 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) { 1912 rc = -EINVAL; 1913 goto out; 1914 } 1915 1916 if ((mbox_sel & (1 << mbox)) == 0) { 1917 rc = -ENODEV; 1918 goto out; 1919 } 1920 1921 priv->omsg_ring[mbox].dev_id = dev_id; 1922 priv->omsg_ring[mbox].size = entries; 1923 priv->omsg_ring[mbox].sts_rdptr = 0; 1924 spin_lock_init(&priv->omsg_ring[mbox].lock); 1925 1926 /* Outbound Msg Buffer allocation based on 1927 the number of maximum descriptor entries */ 1928 for (i = 0; i < entries; i++) { 1929 priv->omsg_ring[mbox].omq_base[i] = 1930 dma_alloc_coherent( 1931 &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE, 1932 &priv->omsg_ring[mbox].omq_phys[i], 1933 GFP_KERNEL); 1934 if (priv->omsg_ring[mbox].omq_base[i] == NULL) { 1935 tsi_debug(OMSG, &priv->pdev->dev, 1936 "ENOMEM for OB_MSG_%d data buffer", mbox); 1937 rc = -ENOMEM; 1938 goto out_buf; 1939 } 1940 } 1941 1942 /* Outbound message descriptor allocation */ 1943 priv->omsg_ring[mbox].omd_base = dma_alloc_coherent( 1944 &priv->pdev->dev, 1945 (entries + 1) * sizeof(struct tsi721_omsg_desc), 1946 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL); 1947 if (priv->omsg_ring[mbox].omd_base == NULL) { 1948 tsi_debug(OMSG, &priv->pdev->dev, 1949 "ENOMEM for OB_MSG_%d descriptor memory", mbox); 1950 rc = -ENOMEM; 1951 goto out_buf; 1952 } 1953 1954 priv->omsg_ring[mbox].tx_slot = 0; 1955 1956 /* Outbound message descriptor status FIFO allocation */ 1957 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1); 1958 priv->omsg_ring[mbox].sts_base = dma_alloc_coherent(&priv->pdev->dev, 1959 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), 1960 &priv->omsg_ring[mbox].sts_phys, 1961 GFP_KERNEL); 1962 if (priv->omsg_ring[mbox].sts_base == NULL) { 1963 tsi_debug(OMSG, &priv->pdev->dev, 1964 "ENOMEM for OB_MSG_%d status FIFO", mbox); 1965 rc = -ENOMEM; 1966 goto out_desc; 1967 } 1968 1969 /* 1970 * Configure Outbound Messaging Engine 1971 */ 1972 1973 /* Setup Outbound Message descriptor pointer */ 1974 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32), 1975 priv->regs + TSI721_OBDMAC_DPTRH(mbox)); 1976 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys & 1977 TSI721_OBDMAC_DPTRL_MASK), 1978 priv->regs + TSI721_OBDMAC_DPTRL(mbox)); 1979 1980 /* Setup Outbound Message descriptor status FIFO */ 1981 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32), 1982 priv->regs + TSI721_OBDMAC_DSBH(mbox)); 1983 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys & 1984 TSI721_OBDMAC_DSBL_MASK), 1985 priv->regs + TSI721_OBDMAC_DSBL(mbox)); 1986 iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size), 1987 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox)); 1988 1989 /* Enable interrupts */ 1990 1991#ifdef CONFIG_PCI_MSI 1992 if (priv->flags & TSI721_USING_MSIX) { 1993 int idx = TSI721_VECT_OMB0_DONE + mbox; 1994 1995 /* Request interrupt service if we are in MSI-X mode */ 1996 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0, 1997 priv->msix[idx].irq_name, (void *)priv); 1998 1999 if (rc) { 2000 tsi_debug(OMSG, &priv->pdev->dev, 2001 "Unable to get MSI-X IRQ for OBOX%d-DONE", 2002 mbox); 2003 goto out_stat; 2004 } 2005 2006 idx = TSI721_VECT_OMB0_INT + mbox; 2007 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0, 2008 priv->msix[idx].irq_name, (void *)priv); 2009 2010 if (rc) { 2011 tsi_debug(OMSG, &priv->pdev->dev, 2012 "Unable to get MSI-X IRQ for MBOX%d-INT", mbox); 2013 idx = TSI721_VECT_OMB0_DONE + mbox; 2014 free_irq(priv->msix[idx].vector, (void *)priv); 2015 goto out_stat; 2016 } 2017 } 2018#endif /* CONFIG_PCI_MSI */ 2019 2020 tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL); 2021 2022 /* Initialize Outbound Message descriptors ring */ 2023 bd_ptr = priv->omsg_ring[mbox].omd_base; 2024 bd_ptr[entries].type_id = cpu_to_le32(DTYPE5 << 29); 2025 bd_ptr[entries].msg_info = 0; 2026 bd_ptr[entries].next_lo = 2027 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys & 2028 TSI721_OBDMAC_DPTRL_MASK); 2029 bd_ptr[entries].next_hi = 2030 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32); 2031 priv->omsg_ring[mbox].wr_count = 0; 2032 mb(); 2033 2034 /* Initialize Outbound Message engine */ 2035 iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT, 2036 priv->regs + TSI721_OBDMAC_CTL(mbox)); 2037 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); 2038 udelay(10); 2039 2040 priv->omsg_init[mbox] = 1; 2041 2042 return 0; 2043 2044#ifdef CONFIG_PCI_MSI 2045out_stat: 2046 dma_free_coherent(&priv->pdev->dev, 2047 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), 2048 priv->omsg_ring[mbox].sts_base, 2049 priv->omsg_ring[mbox].sts_phys); 2050 2051 priv->omsg_ring[mbox].sts_base = NULL; 2052#endif /* CONFIG_PCI_MSI */ 2053 2054out_desc: 2055 dma_free_coherent(&priv->pdev->dev, 2056 (entries + 1) * sizeof(struct tsi721_omsg_desc), 2057 priv->omsg_ring[mbox].omd_base, 2058 priv->omsg_ring[mbox].omd_phys); 2059 2060 priv->omsg_ring[mbox].omd_base = NULL; 2061 2062out_buf: 2063 for (i = 0; i < priv->omsg_ring[mbox].size; i++) { 2064 if (priv->omsg_ring[mbox].omq_base[i]) { 2065 dma_free_coherent(&priv->pdev->dev, 2066 TSI721_MSG_BUFFER_SIZE, 2067 priv->omsg_ring[mbox].omq_base[i], 2068 priv->omsg_ring[mbox].omq_phys[i]); 2069 2070 priv->omsg_ring[mbox].omq_base[i] = NULL; 2071 } 2072 } 2073 2074out: 2075 return rc; 2076} 2077 2078/** 2079 * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox 2080 * @mport: Master port implementing the outbound message unit 2081 * @mbox: Mailbox to close 2082 */ 2083static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox) 2084{ 2085 struct tsi721_device *priv = mport->priv; 2086 u32 i; 2087 2088 if (!priv->omsg_init[mbox]) 2089 return; 2090 priv->omsg_init[mbox] = 0; 2091 2092 /* Disable Interrupts */ 2093 2094 tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL); 2095 2096#ifdef CONFIG_PCI_MSI 2097 if (priv->flags & TSI721_USING_MSIX) { 2098 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector, 2099 (void *)priv); 2100 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector, 2101 (void *)priv); 2102 } 2103#endif /* CONFIG_PCI_MSI */ 2104 2105 /* Free OMSG Descriptor Status FIFO */ 2106 dma_free_coherent(&priv->pdev->dev, 2107 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), 2108 priv->omsg_ring[mbox].sts_base, 2109 priv->omsg_ring[mbox].sts_phys); 2110 2111 priv->omsg_ring[mbox].sts_base = NULL; 2112 2113 /* Free OMSG descriptors */ 2114 dma_free_coherent(&priv->pdev->dev, 2115 (priv->omsg_ring[mbox].size + 1) * 2116 sizeof(struct tsi721_omsg_desc), 2117 priv->omsg_ring[mbox].omd_base, 2118 priv->omsg_ring[mbox].omd_phys); 2119 2120 priv->omsg_ring[mbox].omd_base = NULL; 2121 2122 /* Free message buffers */ 2123 for (i = 0; i < priv->omsg_ring[mbox].size; i++) { 2124 if (priv->omsg_ring[mbox].omq_base[i]) { 2125 dma_free_coherent(&priv->pdev->dev, 2126 TSI721_MSG_BUFFER_SIZE, 2127 priv->omsg_ring[mbox].omq_base[i], 2128 priv->omsg_ring[mbox].omq_phys[i]); 2129 2130 priv->omsg_ring[mbox].omq_base[i] = NULL; 2131 } 2132 } 2133} 2134 2135/** 2136 * tsi721_imsg_handler - Inbound Message Interrupt Handler 2137 * @priv: pointer to tsi721 private data 2138 * @ch: inbound message channel number to service 2139 * 2140 * Services channel interrupts from inbound messaging engine. 2141 */ 2142static void tsi721_imsg_handler(struct tsi721_device *priv, int ch) 2143{ 2144 u32 mbox = ch - 4; 2145 u32 imsg_int; 2146 struct rio_mport *mport = &priv->mport; 2147 2148 spin_lock(&priv->imsg_ring[mbox].lock); 2149 2150 imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch)); 2151 2152 if (imsg_int & TSI721_IBDMAC_INT_SRTO) 2153 tsi_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout", mbox); 2154 2155 if (imsg_int & TSI721_IBDMAC_INT_PC_ERROR) 2156 tsi_info(&priv->pdev->dev, "IB MBOX%d PCIe error", mbox); 2157 2158 if (imsg_int & TSI721_IBDMAC_INT_FQ_LOW) 2159 tsi_info(&priv->pdev->dev, "IB MBOX%d IB free queue low", mbox); 2160 2161 /* Clear IB channel interrupts */ 2162 iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch)); 2163 2164 /* If an IB Msg is received notify the upper layer */ 2165 if (imsg_int & TSI721_IBDMAC_INT_DQ_RCV && 2166 mport->inb_msg[mbox].mcback) 2167 mport->inb_msg[mbox].mcback(mport, 2168 priv->imsg_ring[mbox].dev_id, mbox, -1); 2169 2170 if (!(priv->flags & TSI721_USING_MSIX)) { 2171 u32 ch_inte; 2172 2173 /* Re-enable channel interrupts */ 2174 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); 2175 ch_inte |= TSI721_INT_IMSG_CHAN(ch); 2176 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); 2177 } 2178 2179 spin_unlock(&priv->imsg_ring[mbox].lock); 2180} 2181 2182/** 2183 * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox 2184 * @mport: Master port implementing the Inbound Messaging Engine 2185 * @dev_id: Device specific pointer to pass on event 2186 * @mbox: Mailbox to open 2187 * @entries: Number of entries in the inbound mailbox ring 2188 * 2189 * Returns: %0 on success or -errno value on failure. 2190 */ 2191static int tsi721_open_inb_mbox(struct rio_mport *mport, void *dev_id, 2192 int mbox, int entries) 2193{ 2194 struct tsi721_device *priv = mport->priv; 2195 int ch = mbox + 4; 2196 int i; 2197 u64 *free_ptr; 2198 int rc = 0; 2199 2200 if ((entries < TSI721_IMSGD_MIN_RING_SIZE) || 2201 (entries > TSI721_IMSGD_RING_SIZE) || 2202 (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) { 2203 rc = -EINVAL; 2204 goto out; 2205 } 2206 2207 if ((mbox_sel & (1 << mbox)) == 0) { 2208 rc = -ENODEV; 2209 goto out; 2210 } 2211 2212 /* Initialize IB Messaging Ring */ 2213 priv->imsg_ring[mbox].dev_id = dev_id; 2214 priv->imsg_ring[mbox].size = entries; 2215 priv->imsg_ring[mbox].rx_slot = 0; 2216 priv->imsg_ring[mbox].desc_rdptr = 0; 2217 priv->imsg_ring[mbox].fq_wrptr = 0; 2218 for (i = 0; i < priv->imsg_ring[mbox].size; i++) 2219 priv->imsg_ring[mbox].imq_base[i] = NULL; 2220 spin_lock_init(&priv->imsg_ring[mbox].lock); 2221 2222 /* Allocate buffers for incoming messages */ 2223 priv->imsg_ring[mbox].buf_base = 2224 dma_alloc_coherent(&priv->pdev->dev, 2225 entries * TSI721_MSG_BUFFER_SIZE, 2226 &priv->imsg_ring[mbox].buf_phys, 2227 GFP_KERNEL); 2228 2229 if (priv->imsg_ring[mbox].buf_base == NULL) { 2230 tsi_err(&priv->pdev->dev, 2231 "Failed to allocate buffers for IB MBOX%d", mbox); 2232 rc = -ENOMEM; 2233 goto out; 2234 } 2235 2236 /* Allocate memory for circular free list */ 2237 priv->imsg_ring[mbox].imfq_base = 2238 dma_alloc_coherent(&priv->pdev->dev, 2239 entries * 8, 2240 &priv->imsg_ring[mbox].imfq_phys, 2241 GFP_KERNEL); 2242 2243 if (priv->imsg_ring[mbox].imfq_base == NULL) { 2244 tsi_err(&priv->pdev->dev, 2245 "Failed to allocate free queue for IB MBOX%d", mbox); 2246 rc = -ENOMEM; 2247 goto out_buf; 2248 } 2249 2250 /* Allocate memory for Inbound message descriptors */ 2251 priv->imsg_ring[mbox].imd_base = 2252 dma_alloc_coherent(&priv->pdev->dev, 2253 entries * sizeof(struct tsi721_imsg_desc), 2254 &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL); 2255 2256 if (priv->imsg_ring[mbox].imd_base == NULL) { 2257 tsi_err(&priv->pdev->dev, 2258 "Failed to allocate descriptor memory for IB MBOX%d", 2259 mbox); 2260 rc = -ENOMEM; 2261 goto out_dma; 2262 } 2263 2264 /* Fill free buffer pointer list */ 2265 free_ptr = priv->imsg_ring[mbox].imfq_base; 2266 for (i = 0; i < entries; i++) 2267 free_ptr[i] = cpu_to_le64( 2268 (u64)(priv->imsg_ring[mbox].buf_phys) + 2269 i * 0x1000); 2270 2271 mb(); 2272 2273 /* 2274 * For mapping of inbound SRIO Messages into appropriate queues we need 2275 * to set Inbound Device ID register in the messaging engine. We do it 2276 * once when first inbound mailbox is requested. 2277 */ 2278 if (!(priv->flags & TSI721_IMSGID_SET)) { 2279 iowrite32((u32)priv->mport.host_deviceid, 2280 priv->regs + TSI721_IB_DEVID); 2281 priv->flags |= TSI721_IMSGID_SET; 2282 } 2283 2284 /* 2285 * Configure Inbound Messaging channel (ch = mbox + 4) 2286 */ 2287 2288 /* Setup Inbound Message free queue */ 2289 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32), 2290 priv->regs + TSI721_IBDMAC_FQBH(ch)); 2291 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys & 2292 TSI721_IBDMAC_FQBL_MASK), 2293 priv->regs+TSI721_IBDMAC_FQBL(ch)); 2294 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries), 2295 priv->regs + TSI721_IBDMAC_FQSZ(ch)); 2296 2297 /* Setup Inbound Message descriptor queue */ 2298 iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32), 2299 priv->regs + TSI721_IBDMAC_DQBH(ch)); 2300 iowrite32(((u32)priv->imsg_ring[mbox].imd_phys & 2301 (u32)TSI721_IBDMAC_DQBL_MASK), 2302 priv->regs+TSI721_IBDMAC_DQBL(ch)); 2303 iowrite32(TSI721_DMAC_DSSZ_SIZE(entries), 2304 priv->regs + TSI721_IBDMAC_DQSZ(ch)); 2305 2306 /* Enable interrupts */ 2307 2308#ifdef CONFIG_PCI_MSI 2309 if (priv->flags & TSI721_USING_MSIX) { 2310 int idx = TSI721_VECT_IMB0_RCV + mbox; 2311 2312 /* Request interrupt service if we are in MSI-X mode */ 2313 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0, 2314 priv->msix[idx].irq_name, (void *)priv); 2315 2316 if (rc) { 2317 tsi_debug(IMSG, &priv->pdev->dev, 2318 "Unable to get MSI-X IRQ for IBOX%d-DONE", 2319 mbox); 2320 goto out_desc; 2321 } 2322 2323 idx = TSI721_VECT_IMB0_INT + mbox; 2324 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0, 2325 priv->msix[idx].irq_name, (void *)priv); 2326 2327 if (rc) { 2328 tsi_debug(IMSG, &priv->pdev->dev, 2329 "Unable to get MSI-X IRQ for IBOX%d-INT", mbox); 2330 free_irq( 2331 priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector, 2332 (void *)priv); 2333 goto out_desc; 2334 } 2335 } 2336#endif /* CONFIG_PCI_MSI */ 2337 2338 tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL); 2339 2340 /* Initialize Inbound Message Engine */ 2341 iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch)); 2342 ioread32(priv->regs + TSI721_IBDMAC_CTL(ch)); 2343 udelay(10); 2344 priv->imsg_ring[mbox].fq_wrptr = entries - 1; 2345 iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch)); 2346 2347 priv->imsg_init[mbox] = 1; 2348 return 0; 2349 2350#ifdef CONFIG_PCI_MSI 2351out_desc: 2352 dma_free_coherent(&priv->pdev->dev, 2353 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc), 2354 priv->imsg_ring[mbox].imd_base, 2355 priv->imsg_ring[mbox].imd_phys); 2356 2357 priv->imsg_ring[mbox].imd_base = NULL; 2358#endif /* CONFIG_PCI_MSI */ 2359 2360out_dma: 2361 dma_free_coherent(&priv->pdev->dev, 2362 priv->imsg_ring[mbox].size * 8, 2363 priv->imsg_ring[mbox].imfq_base, 2364 priv->imsg_ring[mbox].imfq_phys); 2365 2366 priv->imsg_ring[mbox].imfq_base = NULL; 2367 2368out_buf: 2369 dma_free_coherent(&priv->pdev->dev, 2370 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE, 2371 priv->imsg_ring[mbox].buf_base, 2372 priv->imsg_ring[mbox].buf_phys); 2373 2374 priv->imsg_ring[mbox].buf_base = NULL; 2375 2376out: 2377 return rc; 2378} 2379 2380/** 2381 * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox 2382 * @mport: Master port implementing the Inbound Messaging Engine 2383 * @mbox: Mailbox to close 2384 */ 2385static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox) 2386{ 2387 struct tsi721_device *priv = mport->priv; 2388 u32 rx_slot; 2389 int ch = mbox + 4; 2390 2391 if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */ 2392 return; 2393 priv->imsg_init[mbox] = 0; 2394 2395 /* Disable Inbound Messaging Engine */ 2396 2397 /* Disable Interrupts */ 2398 tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK); 2399 2400#ifdef CONFIG_PCI_MSI 2401 if (priv->flags & TSI721_USING_MSIX) { 2402 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector, 2403 (void *)priv); 2404 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector, 2405 (void *)priv); 2406 } 2407#endif /* CONFIG_PCI_MSI */ 2408 2409 /* Clear Inbound Buffer Queue */ 2410 for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++) 2411 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL; 2412 2413 /* Free memory allocated for message buffers */ 2414 dma_free_coherent(&priv->pdev->dev, 2415 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE, 2416 priv->imsg_ring[mbox].buf_base, 2417 priv->imsg_ring[mbox].buf_phys); 2418 2419 priv->imsg_ring[mbox].buf_base = NULL; 2420 2421 /* Free memory allocated for free pointr list */ 2422 dma_free_coherent(&priv->pdev->dev, 2423 priv->imsg_ring[mbox].size * 8, 2424 priv->imsg_ring[mbox].imfq_base, 2425 priv->imsg_ring[mbox].imfq_phys); 2426 2427 priv->imsg_ring[mbox].imfq_base = NULL; 2428 2429 /* Free memory allocated for RX descriptors */ 2430 dma_free_coherent(&priv->pdev->dev, 2431 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc), 2432 priv->imsg_ring[mbox].imd_base, 2433 priv->imsg_ring[mbox].imd_phys); 2434 2435 priv->imsg_ring[mbox].imd_base = NULL; 2436} 2437 2438/** 2439 * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue 2440 * @mport: Master port implementing the Inbound Messaging Engine 2441 * @mbox: Inbound mailbox number 2442 * @buf: Buffer to add to inbound queue 2443 * 2444 * Returns: %0 on success or -errno value on failure. 2445 */ 2446static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) 2447{ 2448 struct tsi721_device *priv = mport->priv; 2449 u32 rx_slot; 2450 int rc = 0; 2451 2452 rx_slot = priv->imsg_ring[mbox].rx_slot; 2453 if (priv->imsg_ring[mbox].imq_base[rx_slot]) { 2454 tsi_err(&priv->pdev->dev, 2455 "Error adding inbound buffer %d, buffer exists", 2456 rx_slot); 2457 rc = -EINVAL; 2458 goto out; 2459 } 2460 2461 priv->imsg_ring[mbox].imq_base[rx_slot] = buf; 2462 2463 if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size) 2464 priv->imsg_ring[mbox].rx_slot = 0; 2465 2466out: 2467 return rc; 2468} 2469 2470/** 2471 * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue 2472 * @mport: Master port implementing the Inbound Messaging Engine 2473 * @mbox: Inbound mailbox number 2474 * 2475 * Returns: pointer to the message on success or %NULL on failure. 2476 */ 2477static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox) 2478{ 2479 struct tsi721_device *priv = mport->priv; 2480 struct tsi721_imsg_desc *desc; 2481 u32 rx_slot; 2482 void *rx_virt = NULL; 2483 u64 rx_phys; 2484 void *buf = NULL; 2485 u64 *free_ptr; 2486 int ch = mbox + 4; 2487 int msg_size; 2488 2489 if (!priv->imsg_init[mbox]) 2490 return NULL; 2491 2492 desc = priv->imsg_ring[mbox].imd_base; 2493 desc += priv->imsg_ring[mbox].desc_rdptr; 2494 2495 if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO)) 2496 goto out; 2497 2498 rx_slot = priv->imsg_ring[mbox].rx_slot; 2499 while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) { 2500 if (++rx_slot == priv->imsg_ring[mbox].size) 2501 rx_slot = 0; 2502 } 2503 2504 rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) | 2505 le32_to_cpu(desc->bufptr_lo); 2506 2507 rx_virt = priv->imsg_ring[mbox].buf_base + 2508 (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys); 2509 2510 buf = priv->imsg_ring[mbox].imq_base[rx_slot]; 2511 msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT; 2512 if (msg_size == 0) 2513 msg_size = RIO_MAX_MSG_SIZE; 2514 2515 memcpy(buf, rx_virt, msg_size); 2516 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL; 2517 2518 desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO); 2519 if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size) 2520 priv->imsg_ring[mbox].desc_rdptr = 0; 2521 2522 iowrite32(priv->imsg_ring[mbox].desc_rdptr, 2523 priv->regs + TSI721_IBDMAC_DQRP(ch)); 2524 2525 /* Return free buffer into the pointer list */ 2526 free_ptr = priv->imsg_ring[mbox].imfq_base; 2527 free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys); 2528 2529 if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size) 2530 priv->imsg_ring[mbox].fq_wrptr = 0; 2531 2532 iowrite32(priv->imsg_ring[mbox].fq_wrptr, 2533 priv->regs + TSI721_IBDMAC_FQWP(ch)); 2534out: 2535 return buf; 2536} 2537 2538/** 2539 * tsi721_messages_init - Initialization of Messaging Engine 2540 * @priv: pointer to tsi721 private data 2541 * 2542 * Configures Tsi721 messaging engine. 2543 * 2544 * Returns: %0 2545 */ 2546static int tsi721_messages_init(struct tsi721_device *priv) 2547{ 2548 int ch; 2549 2550 iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG); 2551 iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT); 2552 iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT); 2553 2554 /* Set SRIO Message Request/Response Timeout */ 2555 iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO); 2556 2557 /* Initialize Inbound Messaging Engine Registers */ 2558 for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) { 2559 /* Clear interrupt bits */ 2560 iowrite32(TSI721_IBDMAC_INT_MASK, 2561 priv->regs + TSI721_IBDMAC_INT(ch)); 2562 /* Clear Status */ 2563 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch)); 2564 2565 iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK, 2566 priv->regs + TSI721_SMSG_ECC_COR_LOG(ch)); 2567 iowrite32(TSI721_SMSG_ECC_NCOR_MASK, 2568 priv->regs + TSI721_SMSG_ECC_NCOR(ch)); 2569 } 2570 2571 return 0; 2572} 2573 2574/** 2575 * tsi721_query_mport - Fetch inbound message from the Tsi721 MSG Queue 2576 * @mport: Master port implementing the Inbound Messaging Engine 2577 * @attr: mport device attributes 2578 * 2579 * Returns: pointer to the message on success or %NULL on failure. 2580 */ 2581static int tsi721_query_mport(struct rio_mport *mport, 2582 struct rio_mport_attr *attr) 2583{ 2584 struct tsi721_device *priv = mport->priv; 2585 u32 rval; 2586 2587 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_ERR_STS_CSR(0, 0)); 2588 if (rval & RIO_PORT_N_ERR_STS_PORT_OK) { 2589 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL2_CSR(0, 0)); 2590 attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28; 2591 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL_CSR(0, 0)); 2592 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27; 2593 } else 2594 attr->link_speed = RIO_LINK_DOWN; 2595 2596#ifdef CONFIG_RAPIDIO_DMA_ENGINE 2597 attr->flags = RIO_MPORT_DMA | RIO_MPORT_DMA_SG; 2598 attr->dma_max_sge = 0; 2599 attr->dma_max_size = TSI721_BDMA_MAX_BCOUNT; 2600 attr->dma_align = 0; 2601#else 2602 attr->flags = 0; 2603#endif 2604 return 0; 2605} 2606 2607/** 2608 * tsi721_disable_ints - disables all device interrupts 2609 * @priv: pointer to tsi721 private data 2610 */ 2611static void tsi721_disable_ints(struct tsi721_device *priv) 2612{ 2613 int ch; 2614 2615 /* Disable all device level interrupts */ 2616 iowrite32(0, priv->regs + TSI721_DEV_INTE); 2617 2618 /* Disable all Device Channel interrupts */ 2619 iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE); 2620 2621 /* Disable all Inbound Msg Channel interrupts */ 2622 for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) 2623 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch)); 2624 2625 /* Disable all Outbound Msg Channel interrupts */ 2626 for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++) 2627 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch)); 2628 2629 /* Disable all general messaging interrupts */ 2630 iowrite32(0, priv->regs + TSI721_SMSG_INTE); 2631 2632 /* Disable all BDMA Channel interrupts */ 2633 for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) 2634 iowrite32(0, 2635 priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE); 2636 2637 /* Disable all general BDMA interrupts */ 2638 iowrite32(0, priv->regs + TSI721_BDMA_INTE); 2639 2640 /* Disable all SRIO Channel interrupts */ 2641 for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++) 2642 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch)); 2643 2644 /* Disable all general SR2PC interrupts */ 2645 iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE); 2646 2647 /* Disable all PC2SR interrupts */ 2648 iowrite32(0, priv->regs + TSI721_PC2SR_INTE); 2649 2650 /* Disable all I2C interrupts */ 2651 iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE); 2652 2653 /* Disable SRIO MAC interrupts */ 2654 iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE); 2655 iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN); 2656} 2657 2658static struct rio_ops tsi721_rio_ops = { 2659 .lcread = tsi721_lcread, 2660 .lcwrite = tsi721_lcwrite, 2661 .cread = tsi721_cread_dma, 2662 .cwrite = tsi721_cwrite_dma, 2663 .dsend = tsi721_dsend, 2664 .open_inb_mbox = tsi721_open_inb_mbox, 2665 .close_inb_mbox = tsi721_close_inb_mbox, 2666 .open_outb_mbox = tsi721_open_outb_mbox, 2667 .close_outb_mbox = tsi721_close_outb_mbox, 2668 .add_outb_message = tsi721_add_outb_message, 2669 .add_inb_buffer = tsi721_add_inb_buffer, 2670 .get_inb_message = tsi721_get_inb_message, 2671 .map_inb = tsi721_rio_map_inb_mem, 2672 .unmap_inb = tsi721_rio_unmap_inb_mem, 2673 .pwenable = tsi721_pw_enable, 2674 .query_mport = tsi721_query_mport, 2675 .map_outb = tsi721_map_outb_win, 2676 .unmap_outb = tsi721_unmap_outb_win, 2677}; 2678 2679static void tsi721_mport_release(struct device *dev) 2680{ 2681 struct rio_mport *mport = to_rio_mport(dev); 2682 2683 tsi_debug(EXIT, dev, "%s id=%d", mport->name, mport->id); 2684} 2685 2686/** 2687 * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port 2688 * @priv: pointer to tsi721 private data 2689 * 2690 * Configures Tsi721 as RapidIO master port. 2691 * 2692 * Returns: %0 on success or -errno value on failure. 2693 */ 2694static int tsi721_setup_mport(struct tsi721_device *priv) 2695{ 2696 struct pci_dev *pdev = priv->pdev; 2697 int err = 0; 2698 struct rio_mport *mport = &priv->mport; 2699 2700 err = rio_mport_initialize(mport); 2701 if (err) 2702 return err; 2703 2704 mport->ops = &tsi721_rio_ops; 2705 mport->index = 0; 2706 mport->sys_size = 0; /* small system */ 2707 mport->priv = (void *)priv; 2708 mport->phys_efptr = 0x100; 2709 mport->phys_rmap = 1; 2710 mport->dev.parent = &pdev->dev; 2711 mport->dev.release = tsi721_mport_release; 2712 2713 INIT_LIST_HEAD(&mport->dbells); 2714 2715 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); 2716 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3); 2717 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3); 2718 snprintf(mport->name, RIO_MAX_MPORT_NAME, "%s(%s)", 2719 dev_driver_string(&pdev->dev), dev_name(&pdev->dev)); 2720 2721 /* Hook up interrupt handler */ 2722 2723#ifdef CONFIG_PCI_MSI 2724 if (!tsi721_enable_msix(priv)) 2725 priv->flags |= TSI721_USING_MSIX; 2726 else if (!pci_enable_msi(pdev)) 2727 priv->flags |= TSI721_USING_MSI; 2728 else 2729 tsi_debug(MPORT, &pdev->dev, 2730 "MSI/MSI-X is not available. Using legacy INTx."); 2731#endif /* CONFIG_PCI_MSI */ 2732 2733 err = tsi721_request_irq(priv); 2734 2735 if (err) { 2736 tsi_err(&pdev->dev, "Unable to get PCI IRQ %02X (err=0x%x)", 2737 pdev->irq, err); 2738 return err; 2739 } 2740 2741#ifdef CONFIG_RAPIDIO_DMA_ENGINE 2742 err = tsi721_register_dma(priv); 2743 if (err) 2744 goto err_exit; 2745#endif 2746 /* Enable SRIO link */ 2747 iowrite32(ioread32(priv->regs + TSI721_DEVCTL) | 2748 TSI721_DEVCTL_SRBOOT_CMPL, 2749 priv->regs + TSI721_DEVCTL); 2750 2751 if (mport->host_deviceid >= 0) 2752 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER | 2753 RIO_PORT_GEN_DISCOVERED, 2754 priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR)); 2755 else 2756 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR)); 2757 2758 err = rio_register_mport(mport); 2759 if (err) { 2760 tsi721_unregister_dma(priv); 2761 goto err_exit; 2762 } 2763 2764 return 0; 2765 2766err_exit: 2767 tsi721_free_irq(priv); 2768 return err; 2769} 2770 2771static int tsi721_probe(struct pci_dev *pdev, 2772 const struct pci_device_id *id) 2773{ 2774 struct tsi721_device *priv; 2775 int err; 2776 2777 priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL); 2778 if (!priv) { 2779 err = -ENOMEM; 2780 goto err_exit; 2781 } 2782 2783 err = pci_enable_device(pdev); 2784 if (err) { 2785 tsi_err(&pdev->dev, "Failed to enable PCI device"); 2786 goto err_clean; 2787 } 2788 2789 priv->pdev = pdev; 2790 2791#ifdef DEBUG 2792 { 2793 int i; 2794 2795 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 2796 tsi_debug(INIT, &pdev->dev, "res%d %pR", 2797 i, &pdev->resource[i]); 2798 } 2799 } 2800#endif 2801 /* 2802 * Verify BAR configuration 2803 */ 2804 2805 /* BAR_0 (registers) must be 512KB+ in 32-bit address space */ 2806 if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) || 2807 pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 || 2808 pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) { 2809 tsi_err(&pdev->dev, "Missing or misconfigured CSR BAR0"); 2810 err = -ENODEV; 2811 goto err_disable_pdev; 2812 } 2813 2814 /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */ 2815 if (!(pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM) || 2816 pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM_64 || 2817 pci_resource_len(pdev, BAR_1) < TSI721_DB_WIN_SIZE) { 2818 tsi_err(&pdev->dev, "Missing or misconfigured Doorbell BAR1"); 2819 err = -ENODEV; 2820 goto err_disable_pdev; 2821 } 2822 2823 /* 2824 * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address 2825 * space. 2826 * NOTE: BAR_2 and BAR_4 are not used by this version of driver. 2827 * It may be a good idea to keep them disabled using HW configuration 2828 * to save PCI memory space. 2829 */ 2830 2831 priv->p2r_bar[0].size = priv->p2r_bar[1].size = 0; 2832 2833 if (pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM_64) { 2834 if (pci_resource_flags(pdev, BAR_2) & IORESOURCE_PREFETCH) 2835 tsi_debug(INIT, &pdev->dev, 2836 "Prefetchable OBW BAR2 will not be used"); 2837 else { 2838 priv->p2r_bar[0].base = pci_resource_start(pdev, BAR_2); 2839 priv->p2r_bar[0].size = pci_resource_len(pdev, BAR_2); 2840 } 2841 } 2842 2843 if (pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM_64) { 2844 if (pci_resource_flags(pdev, BAR_4) & IORESOURCE_PREFETCH) 2845 tsi_debug(INIT, &pdev->dev, 2846 "Prefetchable OBW BAR4 will not be used"); 2847 else { 2848 priv->p2r_bar[1].base = pci_resource_start(pdev, BAR_4); 2849 priv->p2r_bar[1].size = pci_resource_len(pdev, BAR_4); 2850 } 2851 } 2852 2853 err = pci_request_regions(pdev, DRV_NAME); 2854 if (err) { 2855 tsi_err(&pdev->dev, "Unable to obtain PCI resources"); 2856 goto err_disable_pdev; 2857 } 2858 2859 pci_set_master(pdev); 2860 2861 priv->regs = pci_ioremap_bar(pdev, BAR_0); 2862 if (!priv->regs) { 2863 tsi_err(&pdev->dev, "Unable to map device registers space"); 2864 err = -ENOMEM; 2865 goto err_free_res; 2866 } 2867 2868 priv->odb_base = pci_ioremap_bar(pdev, BAR_1); 2869 if (!priv->odb_base) { 2870 tsi_err(&pdev->dev, "Unable to map outbound doorbells space"); 2871 err = -ENOMEM; 2872 goto err_unmap_bars; 2873 } 2874 2875 /* Configure DMA attributes. */ 2876 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2877 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 2878 if (err) { 2879 tsi_err(&pdev->dev, "Unable to set DMA mask"); 2880 goto err_unmap_bars; 2881 } 2882 2883 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) 2884 tsi_info(&pdev->dev, "Unable to set consistent DMA mask"); 2885 } else { 2886 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 2887 if (err) 2888 tsi_info(&pdev->dev, "Unable to set consistent DMA mask"); 2889 } 2890 2891 BUG_ON(!pci_is_pcie(pdev)); 2892 2893 /* Clear "no snoop" and "relaxed ordering" bits. */ 2894 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, 2895 PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0); 2896 2897 /* Override PCIe Maximum Read Request Size setting if requested */ 2898 if (pcie_mrrs >= 0) { 2899 if (pcie_mrrs <= 5) 2900 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, 2901 PCI_EXP_DEVCTL_READRQ, pcie_mrrs << 12); 2902 else 2903 tsi_info(&pdev->dev, 2904 "Invalid MRRS override value %d", pcie_mrrs); 2905 } 2906 2907 /* Set PCIe completion timeout to 1-10ms */ 2908 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 2909 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0x2); 2910 2911 /* 2912 * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block 2913 */ 2914 pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0x01); 2915 pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXTBL, 2916 TSI721_MSIXTBL_OFFSET); 2917 pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXPBA, 2918 TSI721_MSIXPBA_OFFSET); 2919 pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0); 2920 /* End of FIXUP */ 2921 2922 tsi721_disable_ints(priv); 2923 2924 tsi721_init_pc2sr_mapping(priv); 2925 tsi721_init_sr2pc_mapping(priv); 2926 2927 if (tsi721_bdma_maint_init(priv)) { 2928 tsi_err(&pdev->dev, "BDMA initialization failed"); 2929 err = -ENOMEM; 2930 goto err_unmap_bars; 2931 } 2932 2933 err = tsi721_doorbell_init(priv); 2934 if (err) 2935 goto err_free_bdma; 2936 2937 tsi721_port_write_init(priv); 2938 2939 err = tsi721_messages_init(priv); 2940 if (err) 2941 goto err_free_consistent; 2942 2943 err = tsi721_setup_mport(priv); 2944 if (err) 2945 goto err_free_consistent; 2946 2947 pci_set_drvdata(pdev, priv); 2948 tsi721_interrupts_init(priv); 2949 2950 return 0; 2951 2952err_free_consistent: 2953 tsi721_port_write_free(priv); 2954 tsi721_doorbell_free(priv); 2955err_free_bdma: 2956 tsi721_bdma_maint_free(priv); 2957err_unmap_bars: 2958 if (priv->regs) 2959 iounmap(priv->regs); 2960 if (priv->odb_base) 2961 iounmap(priv->odb_base); 2962err_free_res: 2963 pci_release_regions(pdev); 2964err_disable_pdev: 2965 pci_disable_device(pdev); 2966err_clean: 2967 kfree(priv); 2968err_exit: 2969 return err; 2970} 2971 2972static void tsi721_remove(struct pci_dev *pdev) 2973{ 2974 struct tsi721_device *priv = pci_get_drvdata(pdev); 2975 2976 tsi_debug(EXIT, &pdev->dev, "enter"); 2977 2978 tsi721_disable_ints(priv); 2979 tsi721_free_irq(priv); 2980 flush_work(&priv->idb_work); 2981 flush_work(&priv->pw_work); 2982 rio_unregister_mport(&priv->mport); 2983 2984 tsi721_unregister_dma(priv); 2985 tsi721_bdma_maint_free(priv); 2986 tsi721_doorbell_free(priv); 2987 tsi721_port_write_free(priv); 2988 tsi721_close_sr2pc_mapping(priv); 2989 2990 if (priv->regs) 2991 iounmap(priv->regs); 2992 if (priv->odb_base) 2993 iounmap(priv->odb_base); 2994#ifdef CONFIG_PCI_MSI 2995 if (priv->flags & TSI721_USING_MSIX) 2996 pci_disable_msix(priv->pdev); 2997 else if (priv->flags & TSI721_USING_MSI) 2998 pci_disable_msi(priv->pdev); 2999#endif 3000 pci_release_regions(pdev); 3001 pci_disable_device(pdev); 3002 pci_set_drvdata(pdev, NULL); 3003 kfree(priv); 3004 tsi_debug(EXIT, &pdev->dev, "exit"); 3005} 3006 3007static void tsi721_shutdown(struct pci_dev *pdev) 3008{ 3009 struct tsi721_device *priv = pci_get_drvdata(pdev); 3010 3011 tsi_debug(EXIT, &pdev->dev, "enter"); 3012 3013 tsi721_disable_ints(priv); 3014 tsi721_dma_stop_all(priv); 3015 pci_disable_device(pdev); 3016} 3017 3018static const struct pci_device_id tsi721_pci_tbl[] = { 3019 { PCI_DEVICE(PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_TSI721) }, 3020 { 0, } /* terminate list */ 3021}; 3022 3023MODULE_DEVICE_TABLE(pci, tsi721_pci_tbl); 3024 3025static struct pci_driver tsi721_driver = { 3026 .name = "tsi721", 3027 .id_table = tsi721_pci_tbl, 3028 .probe = tsi721_probe, 3029 .remove = tsi721_remove, 3030 .shutdown = tsi721_shutdown, 3031}; 3032 3033module_pci_driver(tsi721_driver); 3034 3035MODULE_DESCRIPTION("IDT Tsi721 PCIExpress-to-SRIO bridge driver"); 3036MODULE_AUTHOR("Integrated Device Technology, Inc."); 3037MODULE_LICENSE("GPL"); 3038