1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * sl28cpld PWM driver
4 *
5 * Copyright (c) 2020 Michael Walle <michael@walle.cc>
6 *
7 * There is no public datasheet available for this PWM core. But it is easy
8 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
9 * supports four distinct frequencies by selecting when to reset the counter.
10 * With the prescaler setting you can select which bit of the counter is used
11 * to reset it. This implies that the higher the frequency the less remaining
12 * bits are available for the actual counter.
13 *
14 * Let cnt[7:0] be the counter, clocked at 32kHz:
15 * +-----------+--------+--------------+-----------+---------------+
16 * | prescaler |  reset | counter bits | frequency | period length |
17 * +-----------+--------+--------------+-----------+---------------+
18 * |         0 | cnt[7] |     cnt[6:0] |    250 Hz |    4000000 ns |
19 * |         1 | cnt[6] |     cnt[5:0] |    500 Hz |    2000000 ns |
20 * |         2 | cnt[5] |     cnt[4:0] |     1 kHz |    1000000 ns |
21 * |         3 | cnt[4] |     cnt[3:0] |     2 kHz |     500000 ns |
22 * +-----------+--------+--------------+-----------+---------------+
23 *
24 * Limitations:
25 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
26 * - The hardware cannot atomically set the prescaler and the counter value,
27 *   which might lead to glitches and inconsistent states if a write fails.
28 * - The counter is not reset if you switch the prescaler which leads
29 *   to glitches, too.
30 * - The duty cycle will switch immediately and not after a complete cycle.
31 * - Depending on the actual implementation, disabling the PWM might have
32 *   side effects. For example, if the output pin is shared with a GPIO pin
33 *   it will automatically switch back to GPIO mode.
34 */
35
36#include <linux/bitfield.h>
37#include <linux/kernel.h>
38#include <linux/mod_devicetable.h>
39#include <linux/module.h>
40#include <linux/platform_device.h>
41#include <linux/property.h>
42#include <linux/pwm.h>
43#include <linux/regmap.h>
44
45/*
46 * PWM timer block registers.
47 */
48#define SL28CPLD_PWM_CTRL			0x00
49#define   SL28CPLD_PWM_CTRL_ENABLE		BIT(7)
50#define   SL28CPLD_PWM_CTRL_PRESCALER_MASK	GENMASK(1, 0)
51#define SL28CPLD_PWM_CYCLE			0x01
52#define   SL28CPLD_PWM_CYCLE_MAX		GENMASK(6, 0)
53
54#define SL28CPLD_PWM_CLK			32000 /* 32 kHz */
55#define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)	(1 << (7 - (prescaler)))
56#define SL28CPLD_PWM_PERIOD(prescaler) \
57	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
58
59/*
60 * We calculate the duty cycle like this:
61 *   duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
62 *
63 * With
64 *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
65 *   max_duty_cycle = 1 << (7 - prescaler)
66 * this then simplifies to:
67 *   duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
68 *                 = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
69 *
70 * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
71 * precision by doing the divison first.
72 */
73#define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
74	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
75#define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
76	(DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
77
78#define sl28cpld_pwm_read(priv, reg, val) \
79	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
80#define sl28cpld_pwm_write(priv, reg, val) \
81	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
82
83struct sl28cpld_pwm {
84	struct regmap *regmap;
85	u32 offset;
86};
87
88static inline struct sl28cpld_pwm *sl28cpld_pwm_from_chip(struct pwm_chip *chip)
89{
90	return pwmchip_get_drvdata(chip);
91}
92
93static int sl28cpld_pwm_get_state(struct pwm_chip *chip,
94				  struct pwm_device *pwm,
95				  struct pwm_state *state)
96{
97	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
98	unsigned int reg;
99	int prescaler;
100
101	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, &reg);
102
103	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;
104
105	prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
106	state->period = SL28CPLD_PWM_PERIOD(prescaler);
107
108	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, &reg);
109	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
110	state->polarity = PWM_POLARITY_NORMAL;
111
112	/*
113	 * Sanitize values for the PWM core. Depending on the prescaler it
114	 * might happen that we calculate a duty_cycle greater than the actual
115	 * period. This might happen if someone (e.g. the bootloader) sets an
116	 * invalid combination of values. The behavior of the hardware is
117	 * undefined in this case. But we need to report sane values back to
118	 * the PWM core.
119	 */
120	state->duty_cycle = min(state->duty_cycle, state->period);
121
122	return 0;
123}
124
125static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
126			      const struct pwm_state *state)
127{
128	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
129	unsigned int cycle, prescaler;
130	bool write_duty_cycle_first;
131	int ret;
132	u8 ctrl;
133
134	/* Polarity inversion is not supported */
135	if (state->polarity != PWM_POLARITY_NORMAL)
136		return -EINVAL;
137
138	/*
139	 * Calculate the prescaler. Pick the biggest period that isn't
140	 * bigger than the requested period.
141	 */
142	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
143	prescaler = order_base_2(prescaler);
144
145	if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
146		return -ERANGE;
147
148	ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
149	if (state->enabled)
150		ctrl |= SL28CPLD_PWM_CTRL_ENABLE;
151
152	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
153	cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
154
155	/*
156	 * Work around the hardware limitation. See also above. Trap 100% duty
157	 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
158	 * care about the frequency because its "all-one" in either case.
159	 *
160	 * We don't need to check the actual prescaler setting, because only
161	 * if the prescaler is 0 we can have this particular value.
162	 */
163	if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
164		ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
165		ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
166		cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
167	}
168
169	/*
170	 * To avoid glitches when we switch the prescaler, we have to make sure
171	 * we have a valid duty cycle for the new mode.
172	 *
173	 * Take the current prescaler (or the current period length) into
174	 * account to decide whether we have to write the duty cycle or the new
175	 * prescaler first. If the period length is decreasing we have to
176	 * write the duty cycle first.
177	 */
178	write_duty_cycle_first = pwm->state.period > state->period;
179
180	if (write_duty_cycle_first) {
181		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
182		if (ret)
183			return ret;
184	}
185
186	ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
187	if (ret)
188		return ret;
189
190	if (!write_duty_cycle_first) {
191		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
192		if (ret)
193			return ret;
194	}
195
196	return 0;
197}
198
199static const struct pwm_ops sl28cpld_pwm_ops = {
200	.apply = sl28cpld_pwm_apply,
201	.get_state = sl28cpld_pwm_get_state,
202};
203
204static int sl28cpld_pwm_probe(struct platform_device *pdev)
205{
206	struct sl28cpld_pwm *priv;
207	struct pwm_chip *chip;
208	int ret;
209
210	if (!pdev->dev.parent) {
211		dev_err(&pdev->dev, "no parent device\n");
212		return -ENODEV;
213	}
214
215	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv));
216	if (IS_ERR(chip))
217		return PTR_ERR(chip);
218	priv = sl28cpld_pwm_from_chip(chip);
219
220	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
221	if (!priv->regmap) {
222		dev_err(&pdev->dev, "could not get parent regmap\n");
223		return -ENODEV;
224	}
225
226	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
227	if (ret) {
228		dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
229			ERR_PTR(ret));
230		return -EINVAL;
231	}
232
233	/* Initialize the pwm_chip structure */
234	chip->ops = &sl28cpld_pwm_ops;
235
236	ret = devm_pwmchip_add(&pdev->dev, chip);
237	if (ret) {
238		dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
239			ERR_PTR(ret));
240		return ret;
241	}
242
243	return 0;
244}
245
246static const struct of_device_id sl28cpld_pwm_of_match[] = {
247	{ .compatible = "kontron,sl28cpld-pwm" },
248	{}
249};
250MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);
251
252static struct platform_driver sl28cpld_pwm_driver = {
253	.probe = sl28cpld_pwm_probe,
254	.driver = {
255		.name = "sl28cpld-pwm",
256		.of_match_table = sl28cpld_pwm_of_match,
257	},
258};
259module_platform_driver(sl28cpld_pwm_driver);
260
261MODULE_DESCRIPTION("sl28cpld PWM Driver");
262MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
263MODULE_LICENSE("GPL");
264