1/* 2 * Allwinner H5 SoC pinctrl driver. 3 * 4 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 5 * 6 * Based on pinctrl-sun8i-h3.c, which is: 7 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 8 * 9 * Based on pinctrl-sun8i-a23.c, which is: 10 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> 11 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> 12 * 13 * This file is licensed under the terms of the GNU General Public 14 * License version 2. This program is licensed "as is" without any 15 * warranty of any kind, whether express or implied. 16 */ 17 18#include <linux/module.h> 19#include <linux/platform_device.h> 20#include <linux/of.h> 21#include <linux/pinctrl/pinctrl.h> 22 23#include "pinctrl-sunxi.h" 24 25static const struct sunxi_desc_pin sun50i_h5_pins[] = { 26 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), 27 SUNXI_FUNCTION(0x0, "gpio_in"), 28 SUNXI_FUNCTION(0x1, "gpio_out"), 29 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 30 SUNXI_FUNCTION(0x3, "jtag"), /* MS */ 31 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ 32 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 33 SUNXI_FUNCTION(0x0, "gpio_in"), 34 SUNXI_FUNCTION(0x1, "gpio_out"), 35 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 36 SUNXI_FUNCTION(0x3, "jtag"), /* CK */ 37 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ 38 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 39 SUNXI_FUNCTION(0x0, "gpio_in"), 40 SUNXI_FUNCTION(0x1, "gpio_out"), 41 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 42 SUNXI_FUNCTION(0x3, "jtag"), /* DO */ 43 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ 44 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 45 SUNXI_FUNCTION(0x0, "gpio_in"), 46 SUNXI_FUNCTION(0x1, "gpio_out"), 47 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 48 SUNXI_FUNCTION(0x3, "jtag"), /* DI */ 49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ 50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 51 SUNXI_FUNCTION(0x0, "gpio_in"), 52 SUNXI_FUNCTION(0x1, "gpio_out"), 53 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 54 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ 55 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 56 SUNXI_FUNCTION(0x0, "gpio_in"), 57 SUNXI_FUNCTION(0x1, "gpio_out"), 58 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 59 SUNXI_FUNCTION(0x3, "pwm0"), 60 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ 61 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 62 SUNXI_FUNCTION(0x0, "gpio_in"), 63 SUNXI_FUNCTION(0x1, "gpio_out"), 64 SUNXI_FUNCTION(0x2, "sim"), /* PWREN */ 65 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ 66 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 67 SUNXI_FUNCTION(0x0, "gpio_in"), 68 SUNXI_FUNCTION(0x1, "gpio_out"), 69 SUNXI_FUNCTION(0x2, "sim"), /* CLK */ 70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ 71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 72 SUNXI_FUNCTION(0x0, "gpio_in"), 73 SUNXI_FUNCTION(0x1, "gpio_out"), 74 SUNXI_FUNCTION(0x2, "sim"), /* DATA */ 75 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ 76 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 77 SUNXI_FUNCTION(0x0, "gpio_in"), 78 SUNXI_FUNCTION(0x1, "gpio_out"), 79 SUNXI_FUNCTION(0x2, "sim"), /* RST */ 80 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ 81 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 82 SUNXI_FUNCTION(0x0, "gpio_in"), 83 SUNXI_FUNCTION(0x1, "gpio_out"), 84 SUNXI_FUNCTION(0x2, "sim"), /* DET */ 85 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ 86 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 87 SUNXI_FUNCTION(0x0, "gpio_in"), 88 SUNXI_FUNCTION(0x1, "gpio_out"), 89 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ 90 SUNXI_FUNCTION(0x3, "di"), /* TX */ 91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ 92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 93 SUNXI_FUNCTION(0x0, "gpio_in"), 94 SUNXI_FUNCTION(0x1, "gpio_out"), 95 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ 96 SUNXI_FUNCTION(0x3, "di"), /* RX */ 97 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ 98 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), 99 SUNXI_FUNCTION(0x0, "gpio_in"), 100 SUNXI_FUNCTION(0x1, "gpio_out"), 101 SUNXI_FUNCTION(0x2, "spi1"), /* CS */ 102 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 103 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */ 104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), 105 SUNXI_FUNCTION(0x0, "gpio_in"), 106 SUNXI_FUNCTION(0x1, "gpio_out"), 107 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 108 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 109 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */ 110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), 111 SUNXI_FUNCTION(0x0, "gpio_in"), 112 SUNXI_FUNCTION(0x1, "gpio_out"), 113 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 114 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 115 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ 116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 117 SUNXI_FUNCTION(0x0, "gpio_in"), 118 SUNXI_FUNCTION(0x1, "gpio_out"), 119 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 120 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 121 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ 122 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 123 SUNXI_FUNCTION(0x0, "gpio_in"), 124 SUNXI_FUNCTION(0x1, "gpio_out"), 125 SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ 126 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ 127 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 128 SUNXI_FUNCTION(0x0, "gpio_in"), 129 SUNXI_FUNCTION(0x1, "gpio_out"), 130 SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */ 131 SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ 132 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ 133 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 134 SUNXI_FUNCTION(0x0, "gpio_in"), 135 SUNXI_FUNCTION(0x1, "gpio_out"), 136 SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */ 137 SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ 138 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */ 139 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20), 140 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x1, "gpio_out"), 142 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */ 143 SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */ 144 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */ 145 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21), 146 SUNXI_FUNCTION(0x0, "gpio_in"), 147 SUNXI_FUNCTION(0x1, "gpio_out"), 148 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */ 149 SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */ 150 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */ 151 /* Hole */ 152 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 153 SUNXI_FUNCTION(0x0, "gpio_in"), 154 SUNXI_FUNCTION(0x1, "gpio_out"), 155 SUNXI_FUNCTION(0x2, "nand0"), /* WE */ 156 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 157 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 158 SUNXI_FUNCTION(0x0, "gpio_in"), 159 SUNXI_FUNCTION(0x1, "gpio_out"), 160 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ 161 SUNXI_FUNCTION(0x3, "spi0"), /* MISO */ 162 SUNXI_FUNCTION(0x4, "mmc2")), /* DS */ 163 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 164 SUNXI_FUNCTION(0x0, "gpio_in"), 165 SUNXI_FUNCTION(0x1, "gpio_out"), 166 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ 167 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 168 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 169 SUNXI_FUNCTION(0x0, "gpio_in"), 170 SUNXI_FUNCTION(0x1, "gpio_out"), 171 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ 172 SUNXI_FUNCTION(0x3, "spi0")), /* CS */ 173 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 174 SUNXI_FUNCTION(0x0, "gpio_in"), 175 SUNXI_FUNCTION(0x1, "gpio_out"), 176 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ 177 SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ 178 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 179 SUNXI_FUNCTION(0x0, "gpio_in"), 180 SUNXI_FUNCTION(0x1, "gpio_out"), 181 SUNXI_FUNCTION(0x2, "nand0"), /* RE */ 182 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 183 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 184 SUNXI_FUNCTION(0x0, "gpio_in"), 185 SUNXI_FUNCTION(0x1, "gpio_out"), 186 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ 187 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 188 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 189 SUNXI_FUNCTION(0x0, "gpio_in"), 190 SUNXI_FUNCTION(0x1, "gpio_out"), 191 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ 192 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), 193 SUNXI_FUNCTION(0x0, "gpio_in"), 194 SUNXI_FUNCTION(0x1, "gpio_out"), 195 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ 196 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 197 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), 198 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x1, "gpio_out"), 200 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ 201 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 202 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), 203 SUNXI_FUNCTION(0x0, "gpio_in"), 204 SUNXI_FUNCTION(0x1, "gpio_out"), 205 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ 206 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 207 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), 208 SUNXI_FUNCTION(0x0, "gpio_in"), 209 SUNXI_FUNCTION(0x1, "gpio_out"), 210 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ 211 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 212 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), 213 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x1, "gpio_out"), 215 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ 216 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 217 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), 218 SUNXI_FUNCTION(0x0, "gpio_in"), 219 SUNXI_FUNCTION(0x1, "gpio_out"), 220 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ 221 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 222 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), 223 SUNXI_FUNCTION(0x0, "gpio_in"), 224 SUNXI_FUNCTION(0x1, "gpio_out"), 225 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ 226 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 227 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), 228 SUNXI_FUNCTION(0x0, "gpio_in"), 229 SUNXI_FUNCTION(0x1, "gpio_out"), 230 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ 231 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 232 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), 233 SUNXI_FUNCTION(0x0, "gpio_in"), 234 SUNXI_FUNCTION(0x1, "gpio_out"), 235 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ 236 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ 237 /* Hole */ 238 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), 239 SUNXI_FUNCTION(0x0, "gpio_in"), 240 SUNXI_FUNCTION(0x1, "gpio_out"), 241 SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */ 242 SUNXI_FUNCTION(0x3, "di"), /* TX */ 243 SUNXI_FUNCTION(0x4, "ts2")), /* CLK */ 244 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), 245 SUNXI_FUNCTION(0x0, "gpio_in"), 246 SUNXI_FUNCTION(0x1, "gpio_out"), 247 SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */ 248 SUNXI_FUNCTION(0x3, "di"), /* RX */ 249 SUNXI_FUNCTION(0x4, "ts2")), /* ERR */ 250 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 251 SUNXI_FUNCTION(0x0, "gpio_in"), 252 SUNXI_FUNCTION(0x1, "gpio_out"), 253 SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */ 254 SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */ 255 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 256 SUNXI_FUNCTION(0x0, "gpio_in"), 257 SUNXI_FUNCTION(0x1, "gpio_out"), 258 SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */ 259 SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */ 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 261 SUNXI_FUNCTION(0x0, "gpio_in"), 262 SUNXI_FUNCTION(0x1, "gpio_out"), 263 SUNXI_FUNCTION(0x2, "emac"), /* RXCK */ 264 SUNXI_FUNCTION(0x4, "ts2")), /* D0 */ 265 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 266 SUNXI_FUNCTION(0x0, "gpio_in"), 267 SUNXI_FUNCTION(0x1, "gpio_out"), 268 SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */ 269 SUNXI_FUNCTION(0x4, "ts2")), /* D1 */ 270 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 271 SUNXI_FUNCTION(0x0, "gpio_in"), 272 SUNXI_FUNCTION(0x1, "gpio_out"), 273 SUNXI_FUNCTION(0x2, "emac"), /* RXERR */ 274 SUNXI_FUNCTION(0x4, "ts2")), /* D2 */ 275 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 276 SUNXI_FUNCTION(0x0, "gpio_in"), 277 SUNXI_FUNCTION(0x1, "gpio_out"), 278 SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */ 279 SUNXI_FUNCTION(0x4, "ts2"), /* D3 */ 280 SUNXI_FUNCTION(0x5, "ts3")), /* CLK */ 281 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), 282 SUNXI_FUNCTION(0x0, "gpio_in"), 283 SUNXI_FUNCTION(0x1, "gpio_out"), 284 SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */ 285 SUNXI_FUNCTION(0x4, "ts2"), /* D4 */ 286 SUNXI_FUNCTION(0x5, "ts3")), /* ERR */ 287 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), 288 SUNXI_FUNCTION(0x0, "gpio_in"), 289 SUNXI_FUNCTION(0x1, "gpio_out"), 290 SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */ 291 SUNXI_FUNCTION(0x4, "ts2"), /* D5 */ 292 SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */ 293 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 294 SUNXI_FUNCTION(0x0, "gpio_in"), 295 SUNXI_FUNCTION(0x1, "gpio_out"), 296 SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */ 297 SUNXI_FUNCTION(0x4, "ts2"), /* D6 */ 298 SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */ 299 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 300 SUNXI_FUNCTION(0x0, "gpio_in"), 301 SUNXI_FUNCTION(0x1, "gpio_out"), 302 SUNXI_FUNCTION(0x2, "emac"), /* CRS */ 303 SUNXI_FUNCTION(0x4, "ts2"), /* D7 */ 304 SUNXI_FUNCTION(0x5, "ts3")), /* D0 */ 305 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 306 SUNXI_FUNCTION(0x0, "gpio_in"), 307 SUNXI_FUNCTION(0x1, "gpio_out"), 308 SUNXI_FUNCTION(0x2, "emac"), /* TXCK */ 309 SUNXI_FUNCTION(0x4, "sim")), /* PWREN */ 310 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 311 SUNXI_FUNCTION(0x0, "gpio_in"), 312 SUNXI_FUNCTION(0x1, "gpio_out"), 313 SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */ 314 SUNXI_FUNCTION(0x4, "sim")), /* CLK */ 315 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 316 SUNXI_FUNCTION(0x0, "gpio_in"), 317 SUNXI_FUNCTION(0x1, "gpio_out"), 318 SUNXI_FUNCTION(0x2, "emac"), /* TXERR */ 319 SUNXI_FUNCTION(0x4, "sim")), /* DATA */ 320 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 321 SUNXI_FUNCTION(0x0, "gpio_in"), 322 SUNXI_FUNCTION(0x1, "gpio_out"), 323 SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */ 324 SUNXI_FUNCTION(0x4, "sim")), /* RST */ 325 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), 326 SUNXI_FUNCTION(0x0, "gpio_in"), 327 SUNXI_FUNCTION(0x1, "gpio_out"), 328 SUNXI_FUNCTION(0x2, "emac"), /* MDC */ 329 SUNXI_FUNCTION(0x4, "sim")), /* DET */ 330 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), 331 SUNXI_FUNCTION(0x0, "gpio_in"), 332 SUNXI_FUNCTION(0x1, "gpio_out"), 333 SUNXI_FUNCTION(0x2, "emac")), /* MDIO */ 334 /* Hole */ 335 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 336 SUNXI_FUNCTION(0x0, "gpio_in"), 337 SUNXI_FUNCTION(0x1, "gpio_out"), 338 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 339 SUNXI_FUNCTION(0x3, "ts0")), /* CLK */ 340 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 341 SUNXI_FUNCTION(0x0, "gpio_in"), 342 SUNXI_FUNCTION(0x1, "gpio_out"), 343 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 344 SUNXI_FUNCTION(0x3, "ts0")), /* ERR */ 345 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 346 SUNXI_FUNCTION(0x0, "gpio_in"), 347 SUNXI_FUNCTION(0x1, "gpio_out"), 348 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 349 SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */ 350 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 351 SUNXI_FUNCTION(0x0, "gpio_in"), 352 SUNXI_FUNCTION(0x1, "gpio_out"), 353 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 354 SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */ 355 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 356 SUNXI_FUNCTION(0x0, "gpio_in"), 357 SUNXI_FUNCTION(0x1, "gpio_out"), 358 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 359 SUNXI_FUNCTION(0x3, "ts0")), /* D0 */ 360 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 361 SUNXI_FUNCTION(0x0, "gpio_in"), 362 SUNXI_FUNCTION(0x1, "gpio_out"), 363 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 364 SUNXI_FUNCTION(0x3, "ts0")), /* D1 */ 365 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 366 SUNXI_FUNCTION(0x0, "gpio_in"), 367 SUNXI_FUNCTION(0x1, "gpio_out"), 368 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 369 SUNXI_FUNCTION(0x3, "ts0")), /* D2 */ 370 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 371 SUNXI_FUNCTION(0x0, "gpio_in"), 372 SUNXI_FUNCTION(0x1, "gpio_out"), 373 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 374 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ 375 SUNXI_FUNCTION(0x4, "ts1")), /* CLK */ 376 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 377 SUNXI_FUNCTION(0x0, "gpio_in"), 378 SUNXI_FUNCTION(0x1, "gpio_out"), 379 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 380 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ 381 SUNXI_FUNCTION(0x4, "ts1")), /* ERR */ 382 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 383 SUNXI_FUNCTION(0x0, "gpio_in"), 384 SUNXI_FUNCTION(0x1, "gpio_out"), 385 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 386 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ 387 SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */ 388 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 389 SUNXI_FUNCTION(0x0, "gpio_in"), 390 SUNXI_FUNCTION(0x1, "gpio_out"), 391 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 392 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ 393 SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */ 394 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 395 SUNXI_FUNCTION(0x0, "gpio_in"), 396 SUNXI_FUNCTION(0x1, "gpio_out"), 397 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 398 SUNXI_FUNCTION(0x3, "ts"), /* D7 */ 399 SUNXI_FUNCTION(0x4, "ts1")), /* D0 */ 400 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 401 SUNXI_FUNCTION(0x0, "gpio_in"), 402 SUNXI_FUNCTION(0x1, "gpio_out"), 403 SUNXI_FUNCTION(0x2, "csi"), /* SCK */ 404 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ 405 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 406 SUNXI_FUNCTION(0x0, "gpio_in"), 407 SUNXI_FUNCTION(0x1, "gpio_out"), 408 SUNXI_FUNCTION(0x2, "csi"), /* SDA */ 409 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ 410 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 411 SUNXI_FUNCTION(0x0, "gpio_in"), 412 SUNXI_FUNCTION(0x1, "gpio_out"), 413 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ 414 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 415 SUNXI_FUNCTION(0x0, "gpio_in"), 416 SUNXI_FUNCTION(0x1, "gpio_out"), 417 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ 418 /* Hole */ 419 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 420 SUNXI_FUNCTION(0x0, "gpio_in"), 421 SUNXI_FUNCTION(0x1, "gpio_out"), 422 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 423 SUNXI_FUNCTION(0x3, "jtag"), /* MS */ 424 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ 425 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 426 SUNXI_FUNCTION(0x0, "gpio_in"), 427 SUNXI_FUNCTION(0x1, "gpio_out"), 428 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 429 SUNXI_FUNCTION(0x3, "jtag"), /* DI */ 430 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ 431 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 432 SUNXI_FUNCTION(0x0, "gpio_in"), 433 SUNXI_FUNCTION(0x1, "gpio_out"), 434 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 435 SUNXI_FUNCTION(0x3, "uart0"), /* TX */ 436 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ 437 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 438 SUNXI_FUNCTION(0x0, "gpio_in"), 439 SUNXI_FUNCTION(0x1, "gpio_out"), 440 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 441 SUNXI_FUNCTION(0x3, "jtag"), /* DO */ 442 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ 443 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 444 SUNXI_FUNCTION(0x0, "gpio_in"), 445 SUNXI_FUNCTION(0x1, "gpio_out"), 446 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 447 SUNXI_FUNCTION(0x3, "uart0"), /* RX */ 448 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ 449 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 450 SUNXI_FUNCTION(0x0, "gpio_in"), 451 SUNXI_FUNCTION(0x1, "gpio_out"), 452 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 453 SUNXI_FUNCTION(0x3, "jtag"), /* CK */ 454 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ 455 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 456 SUNXI_FUNCTION(0x0, "gpio_in"), 457 SUNXI_FUNCTION(0x1, "gpio_out"), 458 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ 459 /* Hole */ 460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 461 SUNXI_FUNCTION(0x0, "gpio_in"), 462 SUNXI_FUNCTION(0x1, "gpio_out"), 463 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 464 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ 465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 466 SUNXI_FUNCTION(0x0, "gpio_in"), 467 SUNXI_FUNCTION(0x1, "gpio_out"), 468 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 469 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ 470 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 471 SUNXI_FUNCTION(0x0, "gpio_in"), 472 SUNXI_FUNCTION(0x1, "gpio_out"), 473 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 474 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ 475 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 476 SUNXI_FUNCTION(0x0, "gpio_in"), 477 SUNXI_FUNCTION(0x1, "gpio_out"), 478 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 479 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ 480 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 481 SUNXI_FUNCTION(0x0, "gpio_in"), 482 SUNXI_FUNCTION(0x1, "gpio_out"), 483 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 484 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ 485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 486 SUNXI_FUNCTION(0x0, "gpio_in"), 487 SUNXI_FUNCTION(0x1, "gpio_out"), 488 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 489 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ 490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 491 SUNXI_FUNCTION(0x0, "gpio_in"), 492 SUNXI_FUNCTION(0x1, "gpio_out"), 493 SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 494 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ 495 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 496 SUNXI_FUNCTION(0x0, "gpio_in"), 497 SUNXI_FUNCTION(0x1, "gpio_out"), 498 SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 499 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ 500 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 501 SUNXI_FUNCTION(0x0, "gpio_in"), 502 SUNXI_FUNCTION(0x1, "gpio_out"), 503 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 504 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ 505 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 506 SUNXI_FUNCTION(0x0, "gpio_in"), 507 SUNXI_FUNCTION(0x1, "gpio_out"), 508 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 509 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ 510 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 511 SUNXI_FUNCTION(0x0, "gpio_in"), 512 SUNXI_FUNCTION(0x1, "gpio_out"), 513 SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */ 514 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ 515 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 516 SUNXI_FUNCTION(0x0, "gpio_in"), 517 SUNXI_FUNCTION(0x1, "gpio_out"), 518 SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */ 519 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ 520 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 521 SUNXI_FUNCTION(0x0, "gpio_in"), 522 SUNXI_FUNCTION(0x1, "gpio_out"), 523 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */ 524 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ 525 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 526 SUNXI_FUNCTION(0x0, "gpio_in"), 527 SUNXI_FUNCTION(0x1, "gpio_out"), 528 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */ 529 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ 530}; 531 532static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = { 533 .pins = sun50i_h5_pins, 534 .npins = ARRAY_SIZE(sun50i_h5_pins), 535 .irq_banks = 2, 536 .irq_read_needs_mux = true, 537 .disable_strict_mode = true, 538}; 539 540static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { 541 .pins = sun50i_h5_pins, 542 .npins = ARRAY_SIZE(sun50i_h5_pins), 543 .irq_banks = 3, 544 .irq_read_needs_mux = true, 545 .disable_strict_mode = true, 546}; 547 548static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) 549{ 550 int ret; 551 552 ret = platform_irq_count(pdev); 553 if (ret < 0) 554 return dev_err_probe(&pdev->dev, ret, 555 "Couldn't determine irq count\n"); 556 557 switch (ret) { 558 case 2: 559 dev_warn(&pdev->dev, 560 "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n"); 561 dev_warn(&pdev->dev, 562 "Please update the device tree, otherwise PG bank IRQ won't work.\n"); 563 return sunxi_pinctrl_init(pdev, 564 &sun50i_h5_pinctrl_data_broken); 565 case 3: 566 return sunxi_pinctrl_init(pdev, 567 &sun50i_h5_pinctrl_data); 568 default: 569 return -EINVAL; 570 } 571} 572 573static const struct of_device_id sun50i_h5_pinctrl_match[] = { 574 { .compatible = "allwinner,sun50i-h5-pinctrl", }, 575 {} 576}; 577 578static struct platform_driver sun50i_h5_pinctrl_driver = { 579 .probe = sun50i_h5_pinctrl_probe, 580 .driver = { 581 .name = "sun50i-h5-pinctrl", 582 .of_match_table = sun50i_h5_pinctrl_match, 583 }, 584}; 585builtin_platform_driver(sun50i_h5_pinctrl_driver); 586