1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2014-2018 Renesas Electronics Europe Limited 4 * 5 * Phil Edworthy <phil.edworthy@renesas.com> 6 * Based on a driver originally written by Michel Pollet at Renesas. 7 */ 8 9#include <dt-bindings/pinctrl/rzn1-pinctrl.h> 10 11#include <linux/clk.h> 12#include <linux/device.h> 13#include <linux/io.h> 14#include <linux/module.h> 15#include <linux/of.h> 16#include <linux/platform_device.h> 17#include <linux/slab.h> 18 19#include <linux/pinctrl/pinconf-generic.h> 20#include <linux/pinctrl/pinconf.h> 21#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinmux.h> 23 24#include "../core.h" 25#include "../pinconf.h" 26#include "../pinctrl-utils.h" 27 28/* Field positions and masks in the pinmux registers */ 29#define RZN1_L1_PIN_DRIVE_STRENGTH 10 30#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0 31#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1 32#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2 33#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3 34#define RZN1_L1_PIN_PULL 8 35#define RZN1_L1_PIN_PULL_NONE 0 36#define RZN1_L1_PIN_PULL_UP 1 37#define RZN1_L1_PIN_PULL_DOWN 3 38#define RZN1_L1_FUNCTION 0 39#define RZN1_L1_FUNC_MASK 0xf 40#define RZN1_L1_FUNCTION_L2 0xf 41 42/* 43 * The hardware manual describes two levels of multiplexing, but it's more 44 * logical to think of the hardware as three levels, with level 3 consisting of 45 * the multiplexing for Ethernet MDIO signals. 46 * 47 * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying 48 * that level 2 functions are used instead. Level 2 has a lot more options, 49 * going from 0 to 61. Level 3 allows selection of MDIO functions which can be 50 * floating, or one of seven internal peripherals. Unfortunately, there are two 51 * level 2 functions that can select MDIO, and two MDIO channels so we have four 52 * sets of level 3 functions. 53 * 54 * For this driver, we've compounded the numbers together, so: 55 * 0 to 9 is level 1 56 * 10 to 71 is 10 + level 2 number 57 * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function. 58 * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function. 59 * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function. 60 * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function. 61 * Examples: 62 * Function 28 corresponds UART0 63 * Function 73 corresponds to MDIO0 to GMAC0 64 * 65 * There are 170 configurable pins (called PL_GPIO in the datasheet). 66 */ 67 68/* 69 * Structure detailing the HW registers on the RZ/N1 devices. 70 * Both the Level 1 mux registers and Level 2 mux registers have the same 71 * structure. The only difference is that Level 2 has additional MDIO registers 72 * at the end. 73 */ 74struct rzn1_pinctrl_regs { 75 u32 conf[170]; 76 u32 pad0[86]; 77 u32 status_protect; /* 0x400 */ 78 /* MDIO mux registers, level2 only */ 79 u32 l2_mdio[2]; 80}; 81 82/** 83 * struct rzn1_pmx_func - describes rzn1 pinmux functions 84 * @name: the name of this specific function 85 * @groups: corresponding pin groups 86 * @num_groups: the number of groups 87 */ 88struct rzn1_pmx_func { 89 const char *name; 90 const char **groups; 91 unsigned int num_groups; 92}; 93 94/** 95 * struct rzn1_pin_group - describes an rzn1 pin group 96 * @name: the name of this specific pin group 97 * @func: the name of the function selected by this group 98 * @npins: the number of pins in this group array, i.e. the number of 99 * elements in .pins so we can iterate over that array 100 * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins() 101 * @pin_ids: array of pin_ids, i.e. the value used to select the mux 102 */ 103struct rzn1_pin_group { 104 const char *name; 105 const char *func; 106 unsigned int npins; 107 unsigned int *pins; 108 u8 *pin_ids; 109}; 110 111struct rzn1_pinctrl { 112 struct device *dev; 113 struct clk *clk; 114 struct pinctrl_dev *pctl; 115 struct rzn1_pinctrl_regs __iomem *lev1; 116 struct rzn1_pinctrl_regs __iomem *lev2; 117 u32 lev1_protect_phys; 118 u32 lev2_protect_phys; 119 int mdio_func[2]; 120 121 struct rzn1_pin_group *groups; 122 unsigned int ngroups; 123 124 struct rzn1_pmx_func *functions; 125 unsigned int nfunctions; 126}; 127 128#define RZN1_PINS_PROP "pinmux" 129 130#define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin) 131 132static const struct pinctrl_pin_desc rzn1_pins[] = { 133 RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4), 134 RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9), 135 RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14), 136 RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19), 137 RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24), 138 RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29), 139 RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34), 140 RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39), 141 RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44), 142 RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49), 143 RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54), 144 RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59), 145 RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64), 146 RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69), 147 RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74), 148 RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79), 149 RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84), 150 RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89), 151 RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94), 152 RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99), 153 RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103), 154 RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107), 155 RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111), 156 RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115), 157 RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119), 158 RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123), 159 RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127), 160 RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131), 161 RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135), 162 RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139), 163 RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143), 164 RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147), 165 RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151), 166 RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155), 167 RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159), 168 RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163), 169 RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167), 170 RZN1_PIN(168), RZN1_PIN(169), 171}; 172 173enum { 174 LOCK_LEVEL1 = 0x1, 175 LOCK_LEVEL2 = 0x2, 176 LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2, 177}; 178 179static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value) 180{ 181 /* 182 * The pinmux configuration is locked by writing the physical address of 183 * the status_protect register to itself. It is unlocked by writing the 184 * address | 1. 185 */ 186 if (lock & LOCK_LEVEL1) { 187 u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1); 188 189 writel(val, &ipctl->lev1->status_protect); 190 } 191 192 if (lock & LOCK_LEVEL2) { 193 u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2); 194 195 writel(val, &ipctl->lev2->status_protect); 196 } 197} 198 199static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio, 200 u32 func) 201{ 202 if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func) 203 dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio); 204 ipctl->mdio_func[mdio] = func; 205 206 dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func); 207 208 writel(func, &ipctl->lev2->l2_mdio[mdio]); 209} 210 211/* 212 * Using a composite pin description, set the hardware pinmux registers 213 * with the corresponding values. 214 * Make sure to unlock write protection and reset it afterward. 215 * 216 * NOTE: There is no protection for potential concurrency, it is assumed these 217 * calls are serialized already. 218 */ 219static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin, 220 u32 pin_config, u8 use_locks) 221{ 222 u32 l1_cache; 223 u32 l2_cache; 224 u32 l1; 225 u32 l2; 226 227 /* Level 3 MDIO multiplexing */ 228 if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ && 229 pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) { 230 int mdio_channel; 231 u32 mdio_func; 232 233 if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ) 234 mdio_channel = 0; 235 else 236 mdio_channel = 1; 237 238 /* Get MDIO func, and convert the func to the level 2 number */ 239 if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) { 240 mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ; 241 pin_config = RZN1_FUNC_ETH_MDIO; 242 } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) { 243 mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ; 244 pin_config = RZN1_FUNC_ETH_MDIO_E1; 245 } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) { 246 mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ; 247 pin_config = RZN1_FUNC_ETH_MDIO; 248 } else { 249 mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ; 250 pin_config = RZN1_FUNC_ETH_MDIO_E1; 251 } 252 rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func); 253 } 254 255 /* Note here, we do not allow anything past the MDIO Mux values */ 256 if (pin >= ARRAY_SIZE(ipctl->lev1->conf) || 257 pin_config >= RZN1_FUNC_MDIO0_HIGHZ) 258 return -EINVAL; 259 260 l1 = readl(&ipctl->lev1->conf[pin]); 261 l1_cache = l1; 262 l2 = readl(&ipctl->lev2->conf[pin]); 263 l2_cache = l2; 264 265 dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config); 266 267 l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION); 268 269 if (pin_config < RZN1_FUNC_L2_OFFSET) { 270 l1 |= (pin_config << RZN1_L1_FUNCTION); 271 } else { 272 l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION); 273 274 l2 = pin_config - RZN1_FUNC_L2_OFFSET; 275 } 276 277 /* If either configuration changes, we update both anyway */ 278 if (l1 != l1_cache || l2 != l2_cache) { 279 writel(l1, &ipctl->lev1->conf[pin]); 280 writel(l2, &ipctl->lev2->conf[pin]); 281 } 282 283 return 0; 284} 285 286static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name( 287 const struct rzn1_pinctrl *ipctl, const char *name) 288{ 289 unsigned int i; 290 291 for (i = 0; i < ipctl->ngroups; i++) { 292 if (!strcmp(ipctl->groups[i].name, name)) 293 return &ipctl->groups[i]; 294 } 295 296 return NULL; 297} 298 299static int rzn1_get_groups_count(struct pinctrl_dev *pctldev) 300{ 301 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 302 303 return ipctl->ngroups; 304} 305 306static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev, 307 unsigned int selector) 308{ 309 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 310 311 return ipctl->groups[selector].name; 312} 313 314static int rzn1_get_group_pins(struct pinctrl_dev *pctldev, 315 unsigned int selector, const unsigned int **pins, 316 unsigned int *npins) 317{ 318 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 319 320 if (selector >= ipctl->ngroups) 321 return -EINVAL; 322 323 *pins = ipctl->groups[selector].pins; 324 *npins = ipctl->groups[selector].npins; 325 326 return 0; 327} 328 329/* 330 * This function is called for each pinctl 'Function' node. 331 * Sub-nodes can be used to describe multiple 'Groups' for the 'Function' 332 * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'. 333 * Each 'Group' uses pinmux = <...> to detail the pins and data used to select 334 * the functionality. Each 'Group' has optional pin configurations that apply 335 * to all pins in the 'Group'. 336 */ 337static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev, 338 struct device_node *np, 339 struct pinctrl_map **map, 340 unsigned int *num_maps) 341{ 342 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 343 const struct rzn1_pin_group *grp; 344 unsigned long *configs = NULL; 345 unsigned int reserved_maps = *num_maps; 346 unsigned int num_configs = 0; 347 unsigned int reserve = 1; 348 int ret; 349 350 dev_dbg(ipctl->dev, "processing node %pOF\n", np); 351 352 grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name); 353 if (!grp) { 354 dev_err(ipctl->dev, "unable to find group for node %pOF\n", np); 355 356 return -EINVAL; 357 } 358 359 /* Get the group's pin configuration */ 360 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, 361 &num_configs); 362 if (ret < 0) { 363 dev_err(ipctl->dev, "%pOF: could not parse property\n", np); 364 365 return ret; 366 } 367 368 if (num_configs) 369 reserve++; 370 371 /* Increase the number of maps to cover this group */ 372 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, 373 reserve); 374 if (ret < 0) 375 goto out; 376 377 /* Associate the group with the function */ 378 ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps, 379 grp->name, grp->func); 380 if (ret < 0) 381 goto out; 382 383 if (num_configs) { 384 /* Associate the group's pin configuration with the group */ 385 ret = pinctrl_utils_add_map_configs(pctldev, map, 386 &reserved_maps, num_maps, grp->name, 387 configs, num_configs, 388 PIN_MAP_TYPE_CONFIGS_GROUP); 389 if (ret < 0) 390 goto out; 391 } 392 393 dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n", 394 grp->func, grp->name, grp->npins); 395 396out: 397 kfree(configs); 398 399 return ret; 400} 401 402static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev, 403 struct device_node *np, 404 struct pinctrl_map **map, 405 unsigned int *num_maps) 406{ 407 struct device_node *child; 408 int ret; 409 410 *map = NULL; 411 *num_maps = 0; 412 413 ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps); 414 if (ret < 0) 415 return ret; 416 417 for_each_child_of_node(np, child) { 418 ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps); 419 if (ret < 0) { 420 of_node_put(child); 421 return ret; 422 } 423 } 424 425 return 0; 426} 427 428static const struct pinctrl_ops rzn1_pctrl_ops = { 429 .get_groups_count = rzn1_get_groups_count, 430 .get_group_name = rzn1_get_group_name, 431 .get_group_pins = rzn1_get_group_pins, 432 .dt_node_to_map = rzn1_dt_node_to_map, 433 .dt_free_map = pinctrl_utils_free_map, 434}; 435 436static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 437{ 438 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 439 440 return ipctl->nfunctions; 441} 442 443static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev, 444 unsigned int selector) 445{ 446 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 447 448 return ipctl->functions[selector].name; 449} 450 451static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev, 452 unsigned int selector, 453 const char * const **groups, 454 unsigned int * const num_groups) 455{ 456 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 457 458 *groups = ipctl->functions[selector].groups; 459 *num_groups = ipctl->functions[selector].num_groups; 460 461 return 0; 462} 463 464static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 465 unsigned int group) 466{ 467 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 468 struct rzn1_pin_group *grp = &ipctl->groups[group]; 469 unsigned int i, grp_pins = grp->npins; 470 471 dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n", 472 ipctl->functions[selector].name, selector, grp->name, group); 473 474 rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL); 475 for (i = 0; i < grp_pins; i++) 476 rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0); 477 rzn1_hw_set_lock(ipctl, LOCK_ALL, 0); 478 479 return 0; 480} 481 482static const struct pinmux_ops rzn1_pmx_ops = { 483 .get_functions_count = rzn1_pmx_get_funcs_count, 484 .get_function_name = rzn1_pmx_get_func_name, 485 .get_function_groups = rzn1_pmx_get_groups, 486 .set_mux = rzn1_set_mux, 487}; 488 489static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 490 unsigned long *config) 491{ 492 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 493 enum pin_config_param param = pinconf_to_config_param(*config); 494 static const u32 reg_drive[4] = { 4, 6, 8, 12 }; 495 u32 pull, drive, l1mux; 496 u32 l1, l2, arg = 0; 497 498 if (pin >= ARRAY_SIZE(ipctl->lev1->conf)) 499 return -EINVAL; 500 501 l1 = readl(&ipctl->lev1->conf[pin]); 502 503 l1mux = l1 & RZN1_L1_FUNC_MASK; 504 pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3; 505 drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3; 506 507 switch (param) { 508 case PIN_CONFIG_BIAS_PULL_UP: 509 if (pull != RZN1_L1_PIN_PULL_UP) 510 return -EINVAL; 511 break; 512 case PIN_CONFIG_BIAS_PULL_DOWN: 513 if (pull != RZN1_L1_PIN_PULL_DOWN) 514 return -EINVAL; 515 break; 516 case PIN_CONFIG_BIAS_DISABLE: 517 if (pull != RZN1_L1_PIN_PULL_NONE) 518 return -EINVAL; 519 break; 520 case PIN_CONFIG_DRIVE_STRENGTH: 521 arg = reg_drive[drive]; 522 break; 523 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 524 l2 = readl(&ipctl->lev2->conf[pin]); 525 if (l1mux == RZN1_L1_FUNCTION_L2) { 526 if (l2 != 0) 527 return -EINVAL; 528 } else if (l1mux != RZN1_FUNC_HIGHZ) { 529 return -EINVAL; 530 } 531 break; 532 default: 533 return -ENOTSUPP; 534 } 535 536 *config = pinconf_to_config_packed(param, arg); 537 538 return 0; 539} 540 541static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 542 unsigned long *configs, unsigned int num_configs) 543{ 544 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 545 enum pin_config_param param; 546 unsigned int i; 547 u32 l1, l1_cache; 548 u32 drv; 549 u32 arg; 550 551 if (pin >= ARRAY_SIZE(ipctl->lev1->conf)) 552 return -EINVAL; 553 554 l1 = readl(&ipctl->lev1->conf[pin]); 555 l1_cache = l1; 556 557 for (i = 0; i < num_configs; i++) { 558 param = pinconf_to_config_param(configs[i]); 559 arg = pinconf_to_config_argument(configs[i]); 560 561 switch (param) { 562 case PIN_CONFIG_BIAS_PULL_UP: 563 dev_dbg(ipctl->dev, "set pin %d pull up\n", pin); 564 l1 &= ~(0x3 << RZN1_L1_PIN_PULL); 565 l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL); 566 break; 567 case PIN_CONFIG_BIAS_PULL_DOWN: 568 dev_dbg(ipctl->dev, "set pin %d pull down\n", pin); 569 l1 &= ~(0x3 << RZN1_L1_PIN_PULL); 570 l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL); 571 break; 572 case PIN_CONFIG_BIAS_DISABLE: 573 dev_dbg(ipctl->dev, "set pin %d bias off\n", pin); 574 l1 &= ~(0x3 << RZN1_L1_PIN_PULL); 575 l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL); 576 break; 577 case PIN_CONFIG_DRIVE_STRENGTH: 578 dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg); 579 switch (arg) { 580 case 4: 581 drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA; 582 break; 583 case 6: 584 drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA; 585 break; 586 case 8: 587 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA; 588 break; 589 case 12: 590 drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA; 591 break; 592 default: 593 dev_err(ipctl->dev, 594 "Drive strength %umA not supported\n", 595 arg); 596 597 return -EINVAL; 598 } 599 600 l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH); 601 l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH); 602 break; 603 604 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 605 dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin); 606 l1 &= ~RZN1_L1_FUNC_MASK; 607 l1 |= RZN1_FUNC_HIGHZ; 608 break; 609 default: 610 return -ENOTSUPP; 611 } 612 } 613 614 if (l1 != l1_cache) { 615 rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1); 616 writel(l1, &ipctl->lev1->conf[pin]); 617 rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0); 618 } 619 620 return 0; 621} 622 623static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev, 624 unsigned int selector, 625 unsigned long *config) 626{ 627 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 628 struct rzn1_pin_group *grp = &ipctl->groups[selector]; 629 unsigned long old = 0; 630 unsigned int i; 631 632 dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector); 633 634 for (i = 0; i < grp->npins; i++) { 635 if (rzn1_pinconf_get(pctldev, grp->pins[i], config)) 636 return -ENOTSUPP; 637 638 /* configs do not match between two pins */ 639 if (i && (old != *config)) 640 return -ENOTSUPP; 641 642 old = *config; 643 } 644 645 return 0; 646} 647 648static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev, 649 unsigned int selector, 650 unsigned long *configs, 651 unsigned int num_configs) 652{ 653 struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 654 struct rzn1_pin_group *grp = &ipctl->groups[selector]; 655 unsigned int i; 656 int ret; 657 658 dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n", 659 grp->name, selector, configs, num_configs); 660 661 for (i = 0; i < grp->npins; i++) { 662 unsigned int pin = grp->pins[i]; 663 664 ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs); 665 if (ret) 666 return ret; 667 } 668 669 return 0; 670} 671 672static const struct pinconf_ops rzn1_pinconf_ops = { 673 .is_generic = true, 674 .pin_config_get = rzn1_pinconf_get, 675 .pin_config_set = rzn1_pinconf_set, 676 .pin_config_group_get = rzn1_pinconf_group_get, 677 .pin_config_group_set = rzn1_pinconf_group_set, 678 .pin_config_config_dbg_show = pinconf_generic_dump_config, 679}; 680 681static struct pinctrl_desc rzn1_pinctrl_desc = { 682 .pctlops = &rzn1_pctrl_ops, 683 .pmxops = &rzn1_pmx_ops, 684 .confops = &rzn1_pinconf_ops, 685 .owner = THIS_MODULE, 686}; 687 688static int rzn1_pinctrl_parse_groups(struct device_node *np, 689 struct rzn1_pin_group *grp, 690 struct rzn1_pinctrl *ipctl) 691{ 692 const __be32 *list; 693 unsigned int i; 694 int size; 695 696 dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name); 697 698 /* Initialise group */ 699 grp->name = np->name; 700 701 /* 702 * The binding format is 703 * pinmux = <PIN_FUNC_ID CONFIG ...>, 704 * do sanity check and calculate pins number 705 */ 706 list = of_get_property(np, RZN1_PINS_PROP, &size); 707 if (!list) { 708 dev_err(ipctl->dev, 709 "no " RZN1_PINS_PROP " property in node %pOF\n", np); 710 711 return -EINVAL; 712 } 713 714 if (!size) { 715 dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n", 716 np); 717 718 return -EINVAL; 719 } 720 721 grp->npins = size / sizeof(list[0]); 722 grp->pin_ids = devm_kmalloc_array(ipctl->dev, 723 grp->npins, sizeof(grp->pin_ids[0]), 724 GFP_KERNEL); 725 grp->pins = devm_kmalloc_array(ipctl->dev, 726 grp->npins, sizeof(grp->pins[0]), 727 GFP_KERNEL); 728 if (!grp->pin_ids || !grp->pins) 729 return -ENOMEM; 730 731 for (i = 0; i < grp->npins; i++) { 732 u32 pin_id = be32_to_cpu(*list++); 733 734 grp->pins[i] = pin_id & 0xff; 735 grp->pin_ids[i] = (pin_id >> 8) & 0x7f; 736 } 737 738 return grp->npins; 739} 740 741static int rzn1_pinctrl_count_function_groups(struct device_node *np) 742{ 743 struct device_node *child; 744 int count = 0; 745 746 if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) 747 count++; 748 749 for_each_child_of_node(np, child) { 750 if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0) 751 count++; 752 } 753 754 return count; 755} 756 757static int rzn1_pinctrl_parse_functions(struct device_node *np, 758 struct rzn1_pinctrl *ipctl, 759 unsigned int index) 760{ 761 struct rzn1_pmx_func *func; 762 struct rzn1_pin_group *grp; 763 struct device_node *child; 764 unsigned int i = 0; 765 int ret; 766 767 func = &ipctl->functions[index]; 768 769 /* Initialise function */ 770 func->name = np->name; 771 func->num_groups = rzn1_pinctrl_count_function_groups(np); 772 if (func->num_groups == 0) { 773 dev_err(ipctl->dev, "no groups defined in %pOF\n", np); 774 return -EINVAL; 775 } 776 dev_dbg(ipctl->dev, "function %s has %d groups\n", 777 np->name, func->num_groups); 778 779 func->groups = devm_kmalloc_array(ipctl->dev, 780 func->num_groups, sizeof(char *), 781 GFP_KERNEL); 782 if (!func->groups) 783 return -ENOMEM; 784 785 if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) { 786 func->groups[i] = np->name; 787 grp = &ipctl->groups[ipctl->ngroups]; 788 grp->func = func->name; 789 ret = rzn1_pinctrl_parse_groups(np, grp, ipctl); 790 if (ret < 0) 791 return ret; 792 i++; 793 ipctl->ngroups++; 794 } 795 796 for_each_child_of_node(np, child) { 797 func->groups[i] = child->name; 798 grp = &ipctl->groups[ipctl->ngroups]; 799 grp->func = func->name; 800 ret = rzn1_pinctrl_parse_groups(child, grp, ipctl); 801 if (ret < 0) { 802 of_node_put(child); 803 return ret; 804 } 805 i++; 806 ipctl->ngroups++; 807 } 808 809 dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n", 810 np->name, i, func->num_groups); 811 812 return 0; 813} 814 815static int rzn1_pinctrl_probe_dt(struct platform_device *pdev, 816 struct rzn1_pinctrl *ipctl) 817{ 818 struct device_node *np = pdev->dev.of_node; 819 struct device_node *child; 820 unsigned int maxgroups = 0; 821 unsigned int i = 0; 822 int nfuncs = 0; 823 int ret; 824 825 nfuncs = of_get_child_count(np); 826 if (nfuncs <= 0) 827 return 0; 828 829 ipctl->nfunctions = nfuncs; 830 ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs, 831 sizeof(*ipctl->functions), 832 GFP_KERNEL); 833 if (!ipctl->functions) 834 return -ENOMEM; 835 836 ipctl->ngroups = 0; 837 for_each_child_of_node(np, child) 838 maxgroups += rzn1_pinctrl_count_function_groups(child); 839 840 ipctl->groups = devm_kmalloc_array(&pdev->dev, 841 maxgroups, 842 sizeof(*ipctl->groups), 843 GFP_KERNEL); 844 if (!ipctl->groups) 845 return -ENOMEM; 846 847 for_each_child_of_node(np, child) { 848 ret = rzn1_pinctrl_parse_functions(child, ipctl, i++); 849 if (ret < 0) { 850 of_node_put(child); 851 return ret; 852 } 853 } 854 855 return 0; 856} 857 858static int rzn1_pinctrl_probe(struct platform_device *pdev) 859{ 860 struct rzn1_pinctrl *ipctl; 861 struct resource *res; 862 int ret; 863 864 /* Create state holders etc for this driver */ 865 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); 866 if (!ipctl) 867 return -ENOMEM; 868 869 ipctl->mdio_func[0] = -1; 870 ipctl->mdio_func[1] = -1; 871 872 ipctl->lev1 = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 873 if (IS_ERR(ipctl->lev1)) 874 return PTR_ERR(ipctl->lev1); 875 ipctl->lev1_protect_phys = (u32)res->start + 0x400; 876 877 ipctl->lev2 = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 878 if (IS_ERR(ipctl->lev2)) 879 return PTR_ERR(ipctl->lev2); 880 ipctl->lev2_protect_phys = (u32)res->start + 0x400; 881 882 ipctl->clk = devm_clk_get(&pdev->dev, NULL); 883 if (IS_ERR(ipctl->clk)) 884 return PTR_ERR(ipctl->clk); 885 ret = clk_prepare_enable(ipctl->clk); 886 if (ret) 887 return ret; 888 889 ipctl->dev = &pdev->dev; 890 rzn1_pinctrl_desc.name = dev_name(&pdev->dev); 891 rzn1_pinctrl_desc.pins = rzn1_pins; 892 rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins); 893 894 ret = rzn1_pinctrl_probe_dt(pdev, ipctl); 895 if (ret) { 896 dev_err(&pdev->dev, "fail to probe dt properties\n"); 897 goto err_clk; 898 } 899 900 platform_set_drvdata(pdev, ipctl); 901 902 ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc, 903 ipctl, &ipctl->pctl); 904 if (ret) { 905 dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n"); 906 goto err_clk; 907 } 908 909 ret = pinctrl_enable(ipctl->pctl); 910 if (ret) 911 goto err_clk; 912 913 dev_info(&pdev->dev, "probed\n"); 914 915 return 0; 916 917err_clk: 918 clk_disable_unprepare(ipctl->clk); 919 920 return ret; 921} 922 923static void rzn1_pinctrl_remove(struct platform_device *pdev) 924{ 925 struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev); 926 927 clk_disable_unprepare(ipctl->clk); 928} 929 930static const struct of_device_id rzn1_pinctrl_match[] = { 931 { .compatible = "renesas,rzn1-pinctrl", }, 932 { /* sentinel */ } 933}; 934MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match); 935 936static struct platform_driver rzn1_pinctrl_driver = { 937 .probe = rzn1_pinctrl_probe, 938 .remove_new = rzn1_pinctrl_remove, 939 .driver = { 940 .name = "rzn1-pinctrl", 941 .of_match_table = rzn1_pinctrl_match, 942 }, 943}; 944 945static int __init _pinctrl_drv_register(void) 946{ 947 return platform_driver_register(&rzn1_pinctrl_driver); 948} 949subsys_initcall(_pinctrl_drv_register); 950 951MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>"); 952MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver"); 953