1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> 5 */ 6 7#ifndef __PINCTRL_MTK_COMMON_H 8#define __PINCTRL_MTK_COMMON_H 9 10#include <linux/pinctrl/pinctrl.h> 11#include <linux/regmap.h> 12#include <linux/pinctrl/pinconf-generic.h> 13 14#include "mtk-eint.h" 15 16#define NO_EINT_SUPPORT 255 17#define MT_EDGE_SENSITIVE 0 18#define MT_LEVEL_SENSITIVE 1 19#define EINT_DBNC_SET_DBNC_BITS 4 20#define EINT_DBNC_RST_BIT (0x1 << 1) 21#define EINT_DBNC_SET_EN (0x1 << 0) 22 23#define MTK_PINCTRL_NOT_SUPPORT (0xffff) 24 25struct mtk_desc_function { 26 const char *name; 27 unsigned char muxval; 28}; 29 30struct mtk_desc_eint { 31 unsigned char eintmux; 32 unsigned char eintnum; 33}; 34 35struct mtk_desc_pin { 36 struct pinctrl_pin_desc pin; 37 const struct mtk_desc_eint eint; 38 const struct mtk_desc_function *functions; 39}; 40 41#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ 42 { \ 43 .pin = _pin, \ 44 .eint = _eint, \ 45 .functions = (struct mtk_desc_function[]){ \ 46 __VA_ARGS__, { } }, \ 47 } 48 49#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \ 50 { \ 51 .eintmux = _eintmux, \ 52 .eintnum = _eintnum, \ 53 } 54 55#define MTK_FUNCTION(_val, _name) \ 56 { \ 57 .muxval = _val, \ 58 .name = _name, \ 59 } 60 61#define SET_ADDR(x, y) (x + (y->devdata->port_align)) 62#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1)) 63 64struct mtk_pinctrl_group { 65 const char *name; 66 unsigned long config; 67 unsigned pin; 68}; 69 70/** 71 * struct mtk_drv_group_desc - Provide driving group data. 72 * @max_drv: The maximum current of this group. 73 * @min_drv: The minimum current of this group. 74 * @low_bit: The lowest bit of this group. 75 * @high_bit: The highest bit of this group. 76 * @step: The step current of this group. 77 */ 78struct mtk_drv_group_desc { 79 unsigned char min_drv; 80 unsigned char max_drv; 81 unsigned char low_bit; 82 unsigned char high_bit; 83 unsigned char step; 84}; 85 86#define MTK_DRV_GRP(_min, _max, _low, _high, _step) \ 87 { \ 88 .min_drv = _min, \ 89 .max_drv = _max, \ 90 .low_bit = _low, \ 91 .high_bit = _high, \ 92 .step = _step, \ 93 } 94 95/** 96 * struct mtk_pin_drv_grp - Provide each pin driving info. 97 * @pin: The pin number. 98 * @offset: The offset of driving register for this pin. 99 * @bit: The bit of driving register for this pin. 100 * @grp: The group for this pin belongs to. 101 */ 102struct mtk_pin_drv_grp { 103 unsigned short pin; 104 unsigned short offset; 105 unsigned char bit; 106 unsigned char grp; 107}; 108 109#define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ 110 { \ 111 .pin = _pin, \ 112 .offset = _offset, \ 113 .bit = _bit, \ 114 .grp = _grp, \ 115 } 116 117/** 118 * struct mtk_pin_spec_pupd_set_samereg 119 * - For special pins' pull up/down setting which resides in same register 120 * @pin: The pin number. 121 * @offset: The offset of special pull up/down setting register. 122 * @pupd_bit: The pull up/down bit in this register. 123 * @r0_bit: The r0 bit of pull resistor. 124 * @r1_bit: The r1 bit of pull resistor. 125 */ 126struct mtk_pin_spec_pupd_set_samereg { 127 unsigned short pin; 128 unsigned short offset; 129 unsigned char pupd_bit; 130 unsigned char r1_bit; 131 unsigned char r0_bit; 132}; 133 134#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ 135 { \ 136 .pin = _pin, \ 137 .offset = _offset, \ 138 .pupd_bit = _pupd, \ 139 .r1_bit = _r1, \ 140 .r0_bit = _r0, \ 141 } 142 143/** 144 * struct mtk_pin_ies_set - For special pins' ies and smt setting. 145 * @start: The start pin number of those special pins. 146 * @end: The end pin number of those special pins. 147 * @offset: The offset of special setting register. 148 * @bit: The bit of special setting register. 149 */ 150struct mtk_pin_ies_smt_set { 151 unsigned short start; 152 unsigned short end; 153 unsigned short offset; 154 unsigned char bit; 155}; 156 157#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ 158 { \ 159 .start = _start, \ 160 .end = _end, \ 161 .bit = _bit, \ 162 .offset = _offset, \ 163 } 164 165struct mtk_eint_offsets { 166 const char *name; 167 unsigned int stat; 168 unsigned int ack; 169 unsigned int mask; 170 unsigned int mask_set; 171 unsigned int mask_clr; 172 unsigned int sens; 173 unsigned int sens_set; 174 unsigned int sens_clr; 175 unsigned int soft; 176 unsigned int soft_set; 177 unsigned int soft_clr; 178 unsigned int pol; 179 unsigned int pol_set; 180 unsigned int pol_clr; 181 unsigned int dom_en; 182 unsigned int dbnc_ctrl; 183 unsigned int dbnc_set; 184 unsigned int dbnc_clr; 185 u8 port_mask; 186 u8 ports; 187}; 188 189/** 190 * struct mtk_pinctrl_devdata - Provide HW GPIO related data. 191 * @pins: An array describing all pins the pin controller affects. 192 * @npins: The number of entries in @pins. 193 * 194 * @grp_desc: The driving group info. 195 * @pin_drv_grp: The driving group for all pins. 196 * @spec_ies: Special pin setting for input enable 197 * @n_spec_ies: Number of entries in spec_ies 198 * @spec_pupd: Special pull up/down setting 199 * @n_spec_pupd: Number of entries in spec_pupd 200 * @spec_smt: Special pin setting for schmitt 201 * @n_spec_smt: Number of entries in spec_smt 202 * @spec_pull_set: Each SoC may have special pins for pull up/down setting, 203 * these pins' pull setting are very different, they have separate pull 204 * up/down bit, R0 and R1 resistor bit, so they need special pull setting. 205 * If special setting is success, this should return 0, otherwise it should 206 * return non-zero value. 207 * @spec_ies_smt_set: Some pins are irregular, their input enable and smt 208 * control register are discontinuous, but they are mapping together. That 209 * means when user set smt, input enable is set at the same time. So they 210 * also need special control. If special control is success, this should 211 * return 0, otherwise return non-zero value. 212 * @spec_pinmux_set: In some cases, there are two pinmux functions share 213 * the same value in the same segment of pinmux control register. If user 214 * want to use one of the two functions, they need an extra bit setting to 215 * select the right one. 216 * @spec_dir_set: In very few SoCs, direction control registers are not 217 * arranged continuously, they may be cut to parts. So they need special 218 * dir setting. 219 * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they 220 * need to use the main R/W register to read/update/write the modes instead of 221 * the SET/CLR register. 222 * 223 * @dir_offset: The direction register offset. 224 * @pullen_offset: The pull-up/pull-down enable register offset. 225 * @pinmux_offset: The pinmux register offset. 226 * 227 * @type1_start: Some chips have two base addresses for pull select register, 228 * that means some pins use the first address and others use the second. This 229 * member record the start of pin number to use the second address. 230 * @type1_end: The end of pin number to use the second address. 231 * 232 * @port_shf: The shift between two registers. 233 * @port_mask: The mask of register. 234 * @port_align: Provide clear register and set register step. 235 */ 236struct mtk_pinctrl_devdata { 237 const struct mtk_desc_pin *pins; 238 unsigned int npins; 239 const struct mtk_drv_group_desc *grp_desc; 240 unsigned int n_grp_cls; 241 const struct mtk_pin_drv_grp *pin_drv_grp; 242 unsigned int n_pin_drv_grps; 243 const struct mtk_pin_ies_smt_set *spec_ies; 244 unsigned int n_spec_ies; 245 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd; 246 unsigned int n_spec_pupd; 247 const struct mtk_pin_ies_smt_set *spec_smt; 248 unsigned int n_spec_smt; 249 int (*spec_pull_set)(struct regmap *regmap, 250 const struct mtk_pinctrl_devdata *devdata, 251 unsigned int pin, bool isup, unsigned int r1r0); 252 int (*spec_ies_smt_set)(struct regmap *reg, 253 const struct mtk_pinctrl_devdata *devdata, 254 unsigned int pin, int value, enum pin_config_param arg); 255 void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, 256 unsigned int mode); 257 void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); 258 int (*mt8365_set_clr_mode)(struct regmap *regmap, 259 unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, 260 bool enable, bool isup); 261 unsigned int dir_offset; 262 unsigned int ies_offset; 263 unsigned int smt_offset; 264 unsigned int pullen_offset; 265 unsigned int pullsel_offset; 266 unsigned int drv_offset; 267 unsigned int dout_offset; 268 unsigned int din_offset; 269 unsigned int pinmux_offset; 270 unsigned short type1_start; 271 unsigned short type1_end; 272 unsigned char port_shf; 273 unsigned char port_mask; 274 unsigned char port_align; 275 struct mtk_eint_hw eint_hw; 276 struct mtk_eint_regs *eint_regs; 277 unsigned int mode_mask; 278 unsigned int mode_per_reg; 279 unsigned int mode_shf; 280}; 281 282struct mtk_pinctrl { 283 struct regmap *regmap1; 284 struct regmap *regmap2; 285 struct pinctrl_desc pctl_desc; 286 struct device *dev; 287 struct gpio_chip *chip; 288 struct mtk_pinctrl_group *groups; 289 unsigned ngroups; 290 const char **grp_names; 291 struct pinctrl_dev *pctl_dev; 292 const struct mtk_pinctrl_devdata *devdata; 293 struct mtk_eint *eint; 294}; 295 296int mtk_pctrl_init(struct platform_device *pdev, 297 const struct mtk_pinctrl_devdata *data, 298 struct regmap *regmap); 299 300int mtk_pctrl_common_probe(struct platform_device *pdev); 301 302int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, 303 const struct mtk_pinctrl_devdata *devdata, 304 unsigned int pin, bool isup, unsigned int r1r0); 305 306int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, 307 const struct mtk_pinctrl_devdata *devdata, 308 unsigned int pin, int value, enum pin_config_param arg); 309 310extern const struct dev_pm_ops mtk_eint_pm_ops; 311 312#endif /* __PINCTRL_MTK_COMMON_H */ 313