1 2/* SPDX-License-Identifier: GPL-2.0 */ 3/* 4 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 5 */ 6 7#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_ 8#define QCOM_PHY_QMP_QSERDES_COM_V3_H_ 9 10/* Only for QMP V3 PHY - QSERDES COM registers */ 11#define QSERDES_V3_COM_ATB_SEL1 0x000 12#define QSERDES_V3_COM_ATB_SEL2 0x004 13#define QSERDES_V3_COM_FREQ_UPDATE 0x008 14#define QSERDES_V3_COM_BG_TIMER 0x00c 15#define QSERDES_V3_COM_SSC_EN_CENTER 0x010 16#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 17#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 18#define QSERDES_V3_COM_SSC_PER1 0x01c 19#define QSERDES_V3_COM_SSC_PER2 0x020 20#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 21#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 22#define QSERDES_V3_COM_POST_DIV 0x02c 23#define QSERDES_V3_COM_POST_DIV_MUX 0x030 24#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 25#define QSERDES_V3_COM_CLK_ENABLE1 0x038 26#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 27#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 28#define QSERDES_V3_COM_PLL_EN 0x044 29#define QSERDES_V3_COM_PLL_IVCO 0x048 30#define QSERDES_V3_COM_CMN_IETRIM 0x04c 31#define QSERDES_V3_COM_CMN_IPTRIM 0x050 32#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR 0x054 33#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS 0x058 34#define QSERDES_V3_COM_CLK_EP_DIV 0x05c 35#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 36#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 37#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 38#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 39#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 40#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 41#define QSERDES_V3_COM_PLL_CNTRL 0x078 42#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM 0x07c 43#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 44#define QSERDES_V3_COM_CML_SYSCLK_SEL 0x084 45#define QSERDES_V3_COM_RESETSM_CNTRL 0x088 46#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 47#define QSERDES_V3_COM_LOCK_CMP_EN 0x090 48#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 49#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 50#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 51#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 52#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 53#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 54#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 55#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 56#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 57#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 58#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 59#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 60#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 61#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 62#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 63#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 64#define QSERDES_V3_COM_INTEGLOOP_EN 0x0d4 65#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 66#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 67#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 68#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 69#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL 0x0e8 70#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 71#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 72#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 73#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 74#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 75#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 76#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 77#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 78#define QSERDES_V3_COM_VCO_TUNE_MINVAL1 0x10c 79#define QSERDES_V3_COM_VCO_TUNE_MINVAL2 0x110 80#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1 0x114 81#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2 0x118 82#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 83#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 84#define QSERDES_V3_COM_CMN_STATUS 0x124 85#define QSERDES_V3_COM_RESET_SM_STATUS 0x128 86#define QSERDES_V3_COM_RESTRIM_CODE_STATUS 0x12c 87#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS 0x130 88#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS 0x134 89#define QSERDES_V3_COM_CLK_SELECT 0x138 90#define QSERDES_V3_COM_HSCLK_SEL 0x13c 91#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS 0x140 92#define QSERDES_V3_COM_PLL_ANALOG 0x144 93#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 94#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 95#define QSERDES_V3_COM_SW_RESET 0x150 96#define QSERDES_V3_COM_CORE_CLK_EN 0x154 97#define QSERDES_V3_COM_C_READY_STATUS 0x158 98#define QSERDES_V3_COM_CMN_CONFIG 0x15c 99#define QSERDES_V3_COM_CMN_RATE_OVERRIDE 0x160 100#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 101#define QSERDES_V3_COM_DEBUG_BUS0 0x168 102#define QSERDES_V3_COM_DEBUG_BUS1 0x16c 103#define QSERDES_V3_COM_DEBUG_BUS2 0x170 104#define QSERDES_V3_COM_DEBUG_BUS3 0x174 105#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 106#define QSERDES_V3_COM_CMN_MISC1 0x17c 107#define QSERDES_V3_COM_CMN_MISC2 0x180 108#define QSERDES_V3_COM_CMN_MODE 0x184 109#define QSERDES_V3_COM_CMN_VREG_SEL 0x188 110 111#endif 112