1/* 2 * ricoh.h 1.9 1999/10/25 20:03:34 3 * 4 * The contents of this file are subject to the Mozilla Public License 5 * Version 1.1 (the "License"); you may not use this file except in 6 * compliance with the License. You may obtain a copy of the License 7 * at http://www.mozilla.org/MPL/ 8 * 9 * Software distributed under the License is distributed on an "AS IS" 10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See 11 * the License for the specific language governing rights and 12 * limitations under the License. 13 * 14 * The initial developer of the original code is David A. Hinds 15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 17 * 18 * Alternatively, the contents of this file may be used under the 19 * terms of the GNU General Public License version 2 (the "GPL"), in which 20 * case the provisions of the GPL are applicable instead of the 21 * above. If you wish to allow the use of your version of this file 22 * only under the terms of the GPL and not to allow others to use 23 * your version of this file under the MPL, indicate your decision by 24 * deleting the provisions above and replace them with the notice and 25 * other provisions required by the GPL. If you do not delete the 26 * provisions above, a recipient may use your version of this file 27 * under either the MPL or the GPL. 28 */ 29 30#ifndef _LINUX_RICOH_H 31#define _LINUX_RICOH_H 32 33 34#define RF5C_MODE_CTL 0x1f /* Mode control */ 35#define RF5C_PWR_CTL 0x2f /* Mixed voltage control */ 36#define RF5C_CHIP_ID 0x3a /* Chip identification */ 37#define RF5C_MODE_CTL_3 0x3b /* Mode control 3 */ 38 39/* I/O window address offset */ 40#define RF5C_IO_OFF(w) (0x36+((w)<<1)) 41 42/* Flags for RF5C_MODE_CTL */ 43#define RF5C_MODE_ATA 0x01 /* ATA mode */ 44#define RF5C_MODE_LED_ENA 0x02 /* IRQ 12 is LED */ 45#define RF5C_MODE_CA21 0x04 46#define RF5C_MODE_CA22 0x08 47#define RF5C_MODE_CA23 0x10 48#define RF5C_MODE_CA24 0x20 49#define RF5C_MODE_CA25 0x40 50#define RF5C_MODE_3STATE_BIT7 0x80 51 52/* Flags for RF5C_PWR_CTL */ 53#define RF5C_PWR_VCC_3V 0x01 54#define RF5C_PWR_IREQ_HIGH 0x02 55#define RF5C_PWR_INPACK_ENA 0x04 56#define RF5C_PWR_5V_DET 0x08 57#define RF5C_PWR_TC_SEL 0x10 /* Terminal Count: irq 11 or 15 */ 58#define RF5C_PWR_DREQ_LOW 0x20 59#define RF5C_PWR_DREQ_OFF 0x00 /* DREQ steering control */ 60#define RF5C_PWR_DREQ_INPACK 0x40 61#define RF5C_PWR_DREQ_SPKR 0x80 62#define RF5C_PWR_DREQ_IOIS16 0xc0 63 64/* Values for RF5C_CHIP_ID */ 65#define RF5C_CHIP_RF5C296 0x32 66#define RF5C_CHIP_RF5C396 0xb2 67 68/* Flags for RF5C_MODE_CTL_3 */ 69#define RF5C_MCTL3_DISABLE 0x01 /* Disable PCMCIA interface */ 70#define RF5C_MCTL3_DMA_ENA 0x02 71 72/* Register definitions for Ricoh PCI-to-CardBus bridges */ 73 74/* Extra bits in CB_BRIDGE_CONTROL */ 75#define RL5C46X_BCR_3E0_ENA 0x0800 76#define RL5C46X_BCR_3E2_ENA 0x1000 77 78/* Bridge Configuration Register */ 79#define RL5C4XX_CONFIG 0x80 /* 16 bit */ 80#define RL5C4XX_CONFIG_IO_1_MODE 0x0200 81#define RL5C4XX_CONFIG_IO_0_MODE 0x0100 82#define RL5C4XX_CONFIG_PREFETCH 0x0001 83 84/* Misc Control Register */ 85#define RL5C4XX_MISC 0x0082 /* 16 bit */ 86#define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002 87#define RL5C4XX_MISC_VCCEN_POL 0x0100 88#define RL5C4XX_MISC_VPPEN_POL 0x0200 89#define RL5C46X_MISC_SUSPEND 0x0001 90#define RL5C46X_MISC_PWR_SAVE_2 0x0004 91#define RL5C46X_MISC_IFACE_BUSY 0x0008 92#define RL5C46X_MISC_B_LOCK 0x0010 93#define RL5C46X_MISC_A_LOCK 0x0020 94#define RL5C46X_MISC_PCI_LOCK 0x0040 95#define RL5C47X_MISC_IFACE_BUSY 0x0004 96#define RL5C47X_MISC_PCI_INT_MASK 0x0018 97#define RL5C47X_MISC_PCI_INT_DIS 0x0020 98#define RL5C47X_MISC_SUBSYS_WR 0x0040 99#define RL5C47X_MISC_SRIRQ_ENA 0x0080 100#define RL5C47X_MISC_5V_DISABLE 0x0400 101#define RL5C47X_MISC_LED_POL 0x0800 102 103/* 16-bit Interface Control Register */ 104#define RL5C4XX_16BIT_CTL 0x0084 /* 16 bit */ 105#define RL5C4XX_16CTL_IO_TIMING 0x0100 106#define RL5C4XX_16CTL_MEM_TIMING 0x0200 107#define RL5C46X_16CTL_LEVEL_1 0x0010 108#define RL5C46X_16CTL_LEVEL_2 0x0020 109 110/* 16-bit IO and memory timing registers */ 111#define RL5C4XX_16BIT_IO_0 0x0088 /* 16 bit */ 112#define RL5C4XX_16BIT_MEM_0 0x008a /* 16 bit */ 113#define RL5C4XX_SETUP_MASK 0x0007 114#define RL5C4XX_SETUP_SHIFT 0 115#define RL5C4XX_CMD_MASK 0x01f0 116#define RL5C4XX_CMD_SHIFT 4 117#define RL5C4XX_HOLD_MASK 0x1c00 118#define RL5C4XX_HOLD_SHIFT 10 119#define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */ 120#define RL5C4XX_ZV_ENABLE 0x08 121 122/* Misc Control 3 Register */ 123#define RL5C4XX_MISC3 0x00A2 /* 16 bit */ 124#define RL5C47X_MISC3_CB_CLKRUN_DIS BIT(1) 125 126#ifdef __YENTA_H 127 128#define rl_misc(socket) ((socket)->private[0]) 129#define rl_ctl(socket) ((socket)->private[1]) 130#define rl_io(socket) ((socket)->private[2]) 131#define rl_mem(socket) ((socket)->private[3]) 132#define rl_config(socket) ((socket)->private[4]) 133 134static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff) 135{ 136 u8 reg; 137 struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket); 138 139 reg = config_readb(socket, RL5C4XX_MISC_CONTROL); 140 if (onoff) 141 /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */ 142 reg |= RL5C4XX_ZV_ENABLE; 143 else 144 reg &= ~RL5C4XX_ZV_ENABLE; 145 146 config_writeb(socket, RL5C4XX_MISC_CONTROL, reg); 147} 148 149static void ricoh_set_zv(struct yenta_socket *socket) 150{ 151 if(socket->dev->vendor == PCI_VENDOR_ID_RICOH) 152 { 153 switch(socket->dev->device) 154 { 155 /* There may be more .. */ 156 case PCI_DEVICE_ID_RICOH_RL5C478: 157 socket->socket.zoom_video = ricoh_zoom_video; 158 break; 159 } 160 } 161} 162 163static void ricoh_set_clkrun(struct yenta_socket *socket, bool quiet) 164{ 165 u16 misc3; 166 167 /* 168 * RL5C475II likely has this setting, too, however no datasheet 169 * is publicly available for this chip 170 */ 171 if (socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C476 && 172 socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C478) 173 return; 174 175 if (socket->dev->revision < 0x80) 176 return; 177 178 misc3 = config_readw(socket, RL5C4XX_MISC3); 179 if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) { 180 if (!quiet) 181 dev_dbg(&socket->dev->dev, 182 "CLKRUN feature already disabled\n"); 183 } else if (disable_clkrun) { 184 if (!quiet) 185 dev_info(&socket->dev->dev, 186 "Disabling CLKRUN feature\n"); 187 misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS; 188 config_writew(socket, RL5C4XX_MISC3, misc3); 189 } 190} 191 192static void ricoh_save_state(struct yenta_socket *socket) 193{ 194 rl_misc(socket) = config_readw(socket, RL5C4XX_MISC); 195 rl_ctl(socket) = config_readw(socket, RL5C4XX_16BIT_CTL); 196 rl_io(socket) = config_readw(socket, RL5C4XX_16BIT_IO_0); 197 rl_mem(socket) = config_readw(socket, RL5C4XX_16BIT_MEM_0); 198 rl_config(socket) = config_readw(socket, RL5C4XX_CONFIG); 199} 200 201static void ricoh_restore_state(struct yenta_socket *socket) 202{ 203 config_writew(socket, RL5C4XX_MISC, rl_misc(socket)); 204 config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket)); 205 config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket)); 206 config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket)); 207 config_writew(socket, RL5C4XX_CONFIG, rl_config(socket)); 208 ricoh_set_clkrun(socket, true); 209} 210 211 212/* 213 * Magic Ricoh initialization code.. 214 */ 215static int ricoh_override(struct yenta_socket *socket) 216{ 217 u16 config, ctl; 218 219 config = config_readw(socket, RL5C4XX_CONFIG); 220 221 /* Set the default timings, don't trust the original values */ 222 ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING; 223 224 if(socket->dev->device < PCI_DEVICE_ID_RICOH_RL5C475) { 225 ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2; 226 } else { 227 config |= RL5C4XX_CONFIG_PREFETCH; 228 } 229 230 config_writew(socket, RL5C4XX_16BIT_CTL, ctl); 231 config_writew(socket, RL5C4XX_CONFIG, config); 232 233 ricoh_set_zv(socket); 234 ricoh_set_clkrun(socket, false); 235 236 return 0; 237} 238 239#endif /* CONFIG_CARDBUS */ 240 241#endif /* _LINUX_RICOH_H */ 242