1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Express I/O Virtualization (IOV) support
4 *   Address Translation Service 1.0
5 *   Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
6 *   PASID support added by Joerg Roedel <joerg.roedel@amd.com>
7 *
8 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
9 * Copyright (C) 2011 Advanced Micro Devices,
10 */
11
12#include <linux/bitfield.h>
13#include <linux/export.h>
14#include <linux/pci-ats.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17
18#include "pci.h"
19
20void pci_ats_init(struct pci_dev *dev)
21{
22	int pos;
23
24	if (pci_ats_disabled())
25		return;
26
27	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
28	if (!pos)
29		return;
30
31	dev->ats_cap = pos;
32}
33
34/**
35 * pci_ats_supported - check if the device can use ATS
36 * @dev: the PCI device
37 *
38 * Returns true if the device supports ATS and is allowed to use it, false
39 * otherwise.
40 */
41bool pci_ats_supported(struct pci_dev *dev)
42{
43	if (!dev->ats_cap)
44		return false;
45
46	return (dev->untrusted == 0);
47}
48EXPORT_SYMBOL_GPL(pci_ats_supported);
49
50/**
51 * pci_enable_ats - enable the ATS capability
52 * @dev: the PCI device
53 * @ps: the IOMMU page shift
54 *
55 * Returns 0 on success, or negative on failure.
56 */
57int pci_enable_ats(struct pci_dev *dev, int ps)
58{
59	u16 ctrl;
60	struct pci_dev *pdev;
61
62	if (!pci_ats_supported(dev))
63		return -EINVAL;
64
65	if (WARN_ON(dev->ats_enabled))
66		return -EBUSY;
67
68	if (ps < PCI_ATS_MIN_STU)
69		return -EINVAL;
70
71	/*
72	 * Note that enabling ATS on a VF fails unless it's already enabled
73	 * with the same STU on the PF.
74	 */
75	ctrl = PCI_ATS_CTRL_ENABLE;
76	if (dev->is_virtfn) {
77		pdev = pci_physfn(dev);
78		if (pdev->ats_stu != ps)
79			return -EINVAL;
80	} else {
81		dev->ats_stu = ps;
82		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
83	}
84	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
85
86	dev->ats_enabled = 1;
87	return 0;
88}
89EXPORT_SYMBOL_GPL(pci_enable_ats);
90
91/**
92 * pci_disable_ats - disable the ATS capability
93 * @dev: the PCI device
94 */
95void pci_disable_ats(struct pci_dev *dev)
96{
97	u16 ctrl;
98
99	if (WARN_ON(!dev->ats_enabled))
100		return;
101
102	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
103	ctrl &= ~PCI_ATS_CTRL_ENABLE;
104	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
105
106	dev->ats_enabled = 0;
107}
108EXPORT_SYMBOL_GPL(pci_disable_ats);
109
110void pci_restore_ats_state(struct pci_dev *dev)
111{
112	u16 ctrl;
113
114	if (!dev->ats_enabled)
115		return;
116
117	ctrl = PCI_ATS_CTRL_ENABLE;
118	if (!dev->is_virtfn)
119		ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
120	pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
121}
122
123/**
124 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
125 * @dev: the PCI device
126 *
127 * Returns the queue depth on success, or negative on failure.
128 *
129 * The ATS spec uses 0 in the Invalidate Queue Depth field to
130 * indicate that the function can accept 32 Invalidate Request.
131 * But here we use the `real' values (i.e. 1~32) for the Queue
132 * Depth; and 0 indicates the function shares the Queue with
133 * other functions (doesn't exclusively own a Queue).
134 */
135int pci_ats_queue_depth(struct pci_dev *dev)
136{
137	u16 cap;
138
139	if (!dev->ats_cap)
140		return -EINVAL;
141
142	if (dev->is_virtfn)
143		return 0;
144
145	pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
146	return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
147}
148
149/**
150 * pci_ats_page_aligned - Return Page Aligned Request bit status.
151 * @pdev: the PCI device
152 *
153 * Returns 1, if the Untranslated Addresses generated by the device
154 * are always aligned or 0 otherwise.
155 *
156 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
157 * is set, it indicates the Untranslated Addresses generated by the
158 * device are always aligned to a 4096 byte boundary.
159 */
160int pci_ats_page_aligned(struct pci_dev *pdev)
161{
162	u16 cap;
163
164	if (!pdev->ats_cap)
165		return 0;
166
167	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
168
169	if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
170		return 1;
171
172	return 0;
173}
174
175#ifdef CONFIG_PCI_PRI
176void pci_pri_init(struct pci_dev *pdev)
177{
178	u16 status;
179
180	pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
181
182	if (!pdev->pri_cap)
183		return;
184
185	pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
186	if (status & PCI_PRI_STATUS_PASID)
187		pdev->pasid_required = 1;
188}
189
190/**
191 * pci_enable_pri - Enable PRI capability
192 * @pdev: PCI device structure
193 * @reqs: outstanding requests
194 *
195 * Returns 0 on success, negative value on error
196 */
197int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
198{
199	u16 control, status;
200	u32 max_requests;
201	int pri = pdev->pri_cap;
202
203	/*
204	 * VFs must not implement the PRI Capability.  If their PF
205	 * implements PRI, it is shared by the VFs, so if the PF PRI is
206	 * enabled, it is also enabled for the VF.
207	 */
208	if (pdev->is_virtfn) {
209		if (pci_physfn(pdev)->pri_enabled)
210			return 0;
211		return -EINVAL;
212	}
213
214	if (WARN_ON(pdev->pri_enabled))
215		return -EBUSY;
216
217	if (!pri)
218		return -EINVAL;
219
220	pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
221	if (!(status & PCI_PRI_STATUS_STOPPED))
222		return -EBUSY;
223
224	pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
225	reqs = min(max_requests, reqs);
226	pdev->pri_reqs_alloc = reqs;
227	pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
228
229	control = PCI_PRI_CTRL_ENABLE;
230	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
231
232	pdev->pri_enabled = 1;
233
234	return 0;
235}
236
237/**
238 * pci_disable_pri - Disable PRI capability
239 * @pdev: PCI device structure
240 *
241 * Only clears the enabled-bit, regardless of its former value
242 */
243void pci_disable_pri(struct pci_dev *pdev)
244{
245	u16 control;
246	int pri = pdev->pri_cap;
247
248	/* VFs share the PF PRI */
249	if (pdev->is_virtfn)
250		return;
251
252	if (WARN_ON(!pdev->pri_enabled))
253		return;
254
255	if (!pri)
256		return;
257
258	pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
259	control &= ~PCI_PRI_CTRL_ENABLE;
260	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
261
262	pdev->pri_enabled = 0;
263}
264EXPORT_SYMBOL_GPL(pci_disable_pri);
265
266/**
267 * pci_restore_pri_state - Restore PRI
268 * @pdev: PCI device structure
269 */
270void pci_restore_pri_state(struct pci_dev *pdev)
271{
272	u16 control = PCI_PRI_CTRL_ENABLE;
273	u32 reqs = pdev->pri_reqs_alloc;
274	int pri = pdev->pri_cap;
275
276	if (pdev->is_virtfn)
277		return;
278
279	if (!pdev->pri_enabled)
280		return;
281
282	if (!pri)
283		return;
284
285	pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
286	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
287}
288
289/**
290 * pci_reset_pri - Resets device's PRI state
291 * @pdev: PCI device structure
292 *
293 * The PRI capability must be disabled before this function is called.
294 * Returns 0 on success, negative value on error.
295 */
296int pci_reset_pri(struct pci_dev *pdev)
297{
298	u16 control;
299	int pri = pdev->pri_cap;
300
301	if (pdev->is_virtfn)
302		return 0;
303
304	if (WARN_ON(pdev->pri_enabled))
305		return -EBUSY;
306
307	if (!pri)
308		return -EINVAL;
309
310	control = PCI_PRI_CTRL_RESET;
311	pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
312
313	return 0;
314}
315
316/**
317 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
318 *				 status.
319 * @pdev: PCI device structure
320 *
321 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
322 */
323int pci_prg_resp_pasid_required(struct pci_dev *pdev)
324{
325	if (pdev->is_virtfn)
326		pdev = pci_physfn(pdev);
327
328	return pdev->pasid_required;
329}
330
331/**
332 * pci_pri_supported - Check if PRI is supported.
333 * @pdev: PCI device structure
334 *
335 * Returns true if PRI capability is present, false otherwise.
336 */
337bool pci_pri_supported(struct pci_dev *pdev)
338{
339	/* VFs share the PF PRI */
340	if (pci_physfn(pdev)->pri_cap)
341		return true;
342	return false;
343}
344EXPORT_SYMBOL_GPL(pci_pri_supported);
345#endif /* CONFIG_PCI_PRI */
346
347#ifdef CONFIG_PCI_PASID
348void pci_pasid_init(struct pci_dev *pdev)
349{
350	pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
351}
352
353/**
354 * pci_enable_pasid - Enable the PASID capability
355 * @pdev: PCI device structure
356 * @features: Features to enable
357 *
358 * Returns 0 on success, negative value on error. This function checks
359 * whether the features are actually supported by the device and returns
360 * an error if not.
361 */
362int pci_enable_pasid(struct pci_dev *pdev, int features)
363{
364	u16 control, supported;
365	int pasid = pdev->pasid_cap;
366
367	/*
368	 * VFs must not implement the PASID Capability, but if a PF
369	 * supports PASID, its VFs share the PF PASID configuration.
370	 */
371	if (pdev->is_virtfn) {
372		if (pci_physfn(pdev)->pasid_enabled)
373			return 0;
374		return -EINVAL;
375	}
376
377	if (WARN_ON(pdev->pasid_enabled))
378		return -EBUSY;
379
380	if (!pdev->eetlp_prefix_path && !pdev->pasid_no_tlp)
381		return -EINVAL;
382
383	if (!pasid)
384		return -EINVAL;
385
386	if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR | PCI_ACS_UF))
387		return -EINVAL;
388
389	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
390	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
391
392	/* User wants to enable anything unsupported? */
393	if ((supported & features) != features)
394		return -EINVAL;
395
396	control = PCI_PASID_CTRL_ENABLE | features;
397	pdev->pasid_features = features;
398
399	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
400
401	pdev->pasid_enabled = 1;
402
403	return 0;
404}
405EXPORT_SYMBOL_GPL(pci_enable_pasid);
406
407/**
408 * pci_disable_pasid - Disable the PASID capability
409 * @pdev: PCI device structure
410 */
411void pci_disable_pasid(struct pci_dev *pdev)
412{
413	u16 control = 0;
414	int pasid = pdev->pasid_cap;
415
416	/* VFs share the PF PASID configuration */
417	if (pdev->is_virtfn)
418		return;
419
420	if (WARN_ON(!pdev->pasid_enabled))
421		return;
422
423	if (!pasid)
424		return;
425
426	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
427
428	pdev->pasid_enabled = 0;
429}
430EXPORT_SYMBOL_GPL(pci_disable_pasid);
431
432/**
433 * pci_restore_pasid_state - Restore PASID capabilities
434 * @pdev: PCI device structure
435 */
436void pci_restore_pasid_state(struct pci_dev *pdev)
437{
438	u16 control;
439	int pasid = pdev->pasid_cap;
440
441	if (pdev->is_virtfn)
442		return;
443
444	if (!pdev->pasid_enabled)
445		return;
446
447	if (!pasid)
448		return;
449
450	control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
451	pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
452}
453
454/**
455 * pci_pasid_features - Check which PASID features are supported
456 * @pdev: PCI device structure
457 *
458 * Returns a negative value when no PASI capability is present.
459 * Otherwise is returns a bitmask with supported features. Current
460 * features reported are:
461 * PCI_PASID_CAP_EXEC - Execute permission supported
462 * PCI_PASID_CAP_PRIV - Privileged mode supported
463 */
464int pci_pasid_features(struct pci_dev *pdev)
465{
466	u16 supported;
467	int pasid;
468
469	if (pdev->is_virtfn)
470		pdev = pci_physfn(pdev);
471
472	pasid = pdev->pasid_cap;
473	if (!pasid)
474		return -EINVAL;
475
476	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
477
478	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
479
480	return supported;
481}
482EXPORT_SYMBOL_GPL(pci_pasid_features);
483
484/**
485 * pci_max_pasids - Get maximum number of PASIDs supported by device
486 * @pdev: PCI device structure
487 *
488 * Returns negative value when PASID capability is not present.
489 * Otherwise it returns the number of supported PASIDs.
490 */
491int pci_max_pasids(struct pci_dev *pdev)
492{
493	u16 supported;
494	int pasid;
495
496	if (pdev->is_virtfn)
497		pdev = pci_physfn(pdev);
498
499	pasid = pdev->pasid_cap;
500	if (!pasid)
501		return -EINVAL;
502
503	pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
504
505	return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported));
506}
507EXPORT_SYMBOL_GPL(pci_max_pasids);
508#endif /* CONFIG_PCI_PASID */
509