1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-21 Intel Corporation.
4 */
5
6#include <linux/wwan.h>
7
8#include "iosm_ipc_chnl_cfg.h"
9
10/* Max. sizes of a downlink buffers */
11#define IPC_MEM_MAX_DL_FLASH_BUF_SIZE (64 * 1024)
12#define IPC_MEM_MAX_DL_LOOPBACK_SIZE (1 * 1024 * 1024)
13#define IPC_MEM_MAX_DL_AT_BUF_SIZE 2048
14#define IPC_MEM_MAX_DL_RPC_BUF_SIZE (32 * 1024)
15#define IPC_MEM_MAX_DL_MBIM_BUF_SIZE IPC_MEM_MAX_DL_RPC_BUF_SIZE
16
17/* Max. transfer descriptors for a pipe. */
18#define IPC_MEM_MAX_TDS_FLASH_DL 3
19#define IPC_MEM_MAX_TDS_FLASH_UL 6
20#define IPC_MEM_MAX_TDS_AT 4
21#define IPC_MEM_MAX_TDS_RPC 4
22#define IPC_MEM_MAX_TDS_MBIM IPC_MEM_MAX_TDS_RPC
23#define IPC_MEM_MAX_TDS_LOOPBACK 11
24
25/* Accumulation backoff usec */
26#define IRQ_ACC_BACKOFF_OFF 0
27
28/* MUX acc backoff 1ms */
29#define IRQ_ACC_BACKOFF_MUX 1000
30
31/* Modem channel configuration table
32 * Always reserve element zero for flash channel.
33 */
34static struct ipc_chnl_cfg modem_cfg[] = {
35	/* IP Mux */
36	{ IPC_MEM_IP_CHL_ID_0, IPC_MEM_PIPE_0, IPC_MEM_PIPE_1,
37	  IPC_MEM_MAX_TDS_MUX_LITE_UL, IPC_MEM_MAX_TDS_MUX_LITE_DL,
38	  IPC_MEM_MAX_DL_MUX_LITE_BUF_SIZE, WWAN_PORT_UNKNOWN },
39	/* RPC - 0 */
40	{ IPC_MEM_CTRL_CHL_ID_1, IPC_MEM_PIPE_2, IPC_MEM_PIPE_3,
41	  IPC_MEM_MAX_TDS_RPC, IPC_MEM_MAX_TDS_RPC,
42	  IPC_MEM_MAX_DL_RPC_BUF_SIZE, WWAN_PORT_XMMRPC },
43	/* IAT0 */
44	{ IPC_MEM_CTRL_CHL_ID_2, IPC_MEM_PIPE_4, IPC_MEM_PIPE_5,
45	  IPC_MEM_MAX_TDS_AT, IPC_MEM_MAX_TDS_AT, IPC_MEM_MAX_DL_AT_BUF_SIZE,
46	  WWAN_PORT_AT },
47	/* Trace */
48	{ IPC_MEM_CTRL_CHL_ID_3, IPC_MEM_PIPE_6, IPC_MEM_PIPE_7,
49	  IPC_MEM_TDS_TRC, IPC_MEM_TDS_TRC, IPC_MEM_MAX_DL_TRC_BUF_SIZE,
50	  WWAN_PORT_UNKNOWN },
51	/* IAT1 */
52	{ IPC_MEM_CTRL_CHL_ID_4, IPC_MEM_PIPE_8, IPC_MEM_PIPE_9,
53	  IPC_MEM_MAX_TDS_AT, IPC_MEM_MAX_TDS_AT, IPC_MEM_MAX_DL_AT_BUF_SIZE,
54	  WWAN_PORT_AT },
55	/* Loopback */
56	{ IPC_MEM_CTRL_CHL_ID_5, IPC_MEM_PIPE_10, IPC_MEM_PIPE_11,
57	  IPC_MEM_MAX_TDS_LOOPBACK, IPC_MEM_MAX_TDS_LOOPBACK,
58	  IPC_MEM_MAX_DL_LOOPBACK_SIZE, WWAN_PORT_UNKNOWN },
59	/* MBIM Channel */
60	{ IPC_MEM_CTRL_CHL_ID_6, IPC_MEM_PIPE_12, IPC_MEM_PIPE_13,
61	  IPC_MEM_MAX_TDS_MBIM, IPC_MEM_MAX_TDS_MBIM,
62	  IPC_MEM_MAX_DL_MBIM_BUF_SIZE, WWAN_PORT_MBIM },
63	/* Flash Channel/Coredump Channel */
64	{ IPC_MEM_CTRL_CHL_ID_7, IPC_MEM_PIPE_0, IPC_MEM_PIPE_1,
65	  IPC_MEM_MAX_TDS_FLASH_UL, IPC_MEM_MAX_TDS_FLASH_DL,
66	  IPC_MEM_MAX_DL_FLASH_BUF_SIZE, WWAN_PORT_UNKNOWN },
67};
68
69int ipc_chnl_cfg_get(struct ipc_chnl_cfg *chnl_cfg, int index)
70{
71	if (index >= ARRAY_SIZE(modem_cfg)) {
72		pr_err("index: %d and array size %zu", index,
73		       ARRAY_SIZE(modem_cfg));
74		return -ECHRNG;
75	}
76
77	if (index == IPC_MEM_MUX_IP_CH_IF_ID)
78		chnl_cfg->accumulation_backoff = IRQ_ACC_BACKOFF_MUX;
79	else
80		chnl_cfg->accumulation_backoff = IRQ_ACC_BACKOFF_OFF;
81
82	chnl_cfg->ul_nr_of_entries = modem_cfg[index].ul_nr_of_entries;
83	chnl_cfg->dl_nr_of_entries = modem_cfg[index].dl_nr_of_entries;
84	chnl_cfg->dl_buf_size = modem_cfg[index].dl_buf_size;
85	chnl_cfg->id = modem_cfg[index].id;
86	chnl_cfg->ul_pipe = modem_cfg[index].ul_pipe;
87	chnl_cfg->dl_pipe = modem_cfg[index].dl_pipe;
88	chnl_cfg->wwan_port_type = modem_cfg[index].wwan_port_type;
89
90	return 0;
91}
92