1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5#include "cam.h" 6#include "chan.h" 7#include "debug.h" 8#include "efuse.h" 9#include "fw.h" 10#include "mac.h" 11#include "pci.h" 12#include "ps.h" 13#include "reg.h" 14#include "util.h" 15 16static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38}; 39 40static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42{ 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48} 49 50static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52{ 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58} 59 60static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62{ 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82} 83 84int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85{ 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98} 99 100int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101{ 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114} 115 116int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117{ 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154} 155 156int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158{ 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174} 175 176int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178{ 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193} 194 195static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196{ 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209} 210 211static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212{ 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300} 301 302void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304{ 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319} 320 321void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322{ 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654} 655 656static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658{ 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745} 746 747static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749{ 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777} 778 779static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780{ 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810} 811 812u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813{ 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843} 844EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 846int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847{ 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873} 874EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 876static int hfc_reset_param(struct rtw89_dev *rtwdev) 877{ 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905} 906 907static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908{ 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924} 925 926static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927{ 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940} 941 942static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943{ 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951} 952 953static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954{ 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979} 980 981static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982{ 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006} 1007 1008static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009{ 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032} 1033 1034static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035{ 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087} 1088 1089static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090{ 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106} 1107 1108static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109{ 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122} 1123 1124static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125{ 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157} 1158 1159static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160{ 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173} 1174 1175int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176{ 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227} 1228 1229#define PWR_POLL_CNT 2000 1230static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232{ 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249} 1250 1251static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253{ 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292} 1293 1294static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296{ 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307} 1308 1309static enum rtw89_rpwm_req_pwr_state 1310rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311{ 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329} 1330 1331static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334{ 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357} 1358 1359static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361{ 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404} 1405 1406void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407{ 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434} 1435 1436void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437{ 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442} 1443 1444static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445{ 1446#define PWR_ACT 1 1447 const struct rtw89_chip_info *chip = rtwdev->chip; 1448 const struct rtw89_pwr_cfg * const *cfg_seq; 1449 int (*cfg_func)(struct rtw89_dev *rtwdev); 1450 int ret; 1451 u8 val; 1452 1453 if (on) { 1454 cfg_seq = chip->pwr_on_seq; 1455 cfg_func = chip->ops->pwr_on_func; 1456 } else { 1457 cfg_seq = chip->pwr_off_seq; 1458 cfg_func = chip->ops->pwr_off_func; 1459 } 1460 1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462 __rtw89_leave_ps_mode(rtwdev); 1463 1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465 if (on && val == PWR_ACT) { 1466 rtw89_err(rtwdev, "MAC has already powered on\n"); 1467 return -EBUSY; 1468 } 1469 1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471 if (ret) 1472 return ret; 1473 1474 if (on) { 1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479 } else { 1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486 rtw89_set_entity_state(rtwdev, false); 1487 } 1488 1489 return 0; 1490#undef PWR_ACT 1491} 1492 1493void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494{ 1495 rtw89_mac_power_switch(rtwdev, false); 1496} 1497 1498static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499{ 1500 u32 func_en = 0; 1501 u32 ck_en = 0; 1502 u32 c1pc_en = 0; 1503 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505 1506 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1508 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1509 B_AX_CMAC_CRPRT; 1510 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512 B_AX_RMAC_CKEN; 1513 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518 1519 if (en) { 1520 if (mac_idx == RTW89_MAC_1) { 1521 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523 B_AX_R_SYM_ISO_CMAC12PP); 1524 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525 B_AX_CMAC1_FEN); 1526 } 1527 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529 } else { 1530 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532 if (mac_idx == RTW89_MAC_1) { 1533 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534 B_AX_CMAC1_FEN); 1535 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536 B_AX_R_SYM_ISO_CMAC12PP); 1537 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538 } 1539 } 1540 1541 return 0; 1542} 1543 1544static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545{ 1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547 u32 val32; 1548 1549 if (chip_id == RTL8852C) 1550 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557 else 1558 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564 B_AX_DMAC_CRPRT); 1565 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566 1567 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1572 1573 return 0; 1574} 1575 1576static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1577{ 1578 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1579 1580 if (chip_id == RTL8852A || chip_id == RTL8852B) 1581 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1582 B_AX_OCP_L1_MASK); 1583 1584 return 0; 1585} 1586 1587static int sys_init_ax(struct rtw89_dev *rtwdev) 1588{ 1589 int ret; 1590 1591 ret = dmac_func_en_ax(rtwdev); 1592 if (ret) 1593 return ret; 1594 1595 ret = cmac_func_en_ax(rtwdev, 0, true); 1596 if (ret) 1597 return ret; 1598 1599 ret = chip_func_en_ax(rtwdev); 1600 if (ret) 1601 return ret; 1602 1603 return ret; 1604} 1605 1606const struct rtw89_mac_size_set rtw89_mac_size = { 1607 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1608 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1609 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1610 /* PCIE 64 */ 1611 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1612 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1613 /* DLFW */ 1614 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1615 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1616 /* PCIE 64 */ 1617 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1618 /* 8852B PCIE SCC */ 1619 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1620 /* DLFW */ 1621 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1622 /* 8852C DLFW */ 1623 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1624 /* 8852C PCIE SCC */ 1625 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1626 /* PCIE */ 1627 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1628 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1629 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1630 /* DLFW */ 1631 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1632 /* PCIE 64 */ 1633 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1634 /* DLFW */ 1635 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1636 /* 8852C DLFW */ 1637 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1638 /* 8852C PCIE SCC */ 1639 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1640 /* PCIE 64 */ 1641 .wde_qt0 = {3792, 196, 0, 107,}, 1642 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1643 /* DLFW */ 1644 .wde_qt4 = {0, 0, 0, 0,}, 1645 /* PCIE 64 */ 1646 .wde_qt6 = {448, 48, 0, 16,}, 1647 /* 8852B PCIE SCC */ 1648 .wde_qt7 = {446, 48, 0, 16,}, 1649 /* 8852C DLFW */ 1650 .wde_qt17 = {0, 0, 0, 0,}, 1651 /* 8852C PCIE SCC */ 1652 .wde_qt18 = {3228, 60, 0, 40,}, 1653 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1654 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1655 /* PCIE SCC */ 1656 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1657 /* PCIE SCC */ 1658 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1659 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1660 /* DLFW */ 1661 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1662 /* PCIE 64 */ 1663 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1664 /* DLFW 52C */ 1665 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1666 /* DLFW 52C */ 1667 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1668 /* 8852C PCIE SCC */ 1669 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1670 /* 8852C PCIE SCC */ 1671 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1672 /* PCIE 64 */ 1673 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1674 /* 8852A PCIE WOW */ 1675 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1676 /* 8852B PCIE WOW */ 1677 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1678 /* 8851B PCIE WOW */ 1679 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1680 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1681 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1682 .rsvd0_size0 = {212992, 0,}, 1683 .rsvd1_size0 = {587776, 2048,}, 1684}; 1685EXPORT_SYMBOL(rtw89_mac_size); 1686 1687static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1688 enum rtw89_qta_mode mode) 1689{ 1690 struct rtw89_mac_info *mac = &rtwdev->mac; 1691 const struct rtw89_dle_mem *cfg; 1692 1693 cfg = &rtwdev->chip->dle_mem[mode]; 1694 if (!cfg) 1695 return NULL; 1696 1697 if (cfg->mode != mode) { 1698 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1699 return NULL; 1700 } 1701 1702 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1703 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1704 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1705 mac->dle_info.qta_mode = mode; 1706 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1707 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1708 1709 return cfg; 1710} 1711 1712int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1713 enum rtw89_mac_dle_rsvd_qt_type type, 1714 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1715{ 1716 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1717 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1718 1719 switch (type) { 1720 case DLE_RSVD_QT_MPDU_INFO: 1721 cfg->pktid = dle_info->ple_free_pg; 1722 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1723 break; 1724 case DLE_RSVD_QT_B0_CSI: 1725 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1726 cfg->pg_num = rsvd_qt->b0_csi; 1727 break; 1728 case DLE_RSVD_QT_B1_CSI: 1729 cfg->pktid = dle_info->ple_free_pg + 1730 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1731 cfg->pg_num = rsvd_qt->b1_csi; 1732 break; 1733 case DLE_RSVD_QT_B0_LMR: 1734 cfg->pktid = dle_info->ple_free_pg + 1735 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1736 cfg->pg_num = rsvd_qt->b0_lmr; 1737 break; 1738 case DLE_RSVD_QT_B1_LMR: 1739 cfg->pktid = dle_info->ple_free_pg + 1740 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1741 rsvd_qt->b0_lmr; 1742 cfg->pg_num = rsvd_qt->b1_lmr; 1743 break; 1744 case DLE_RSVD_QT_B0_FTM: 1745 cfg->pktid = dle_info->ple_free_pg + 1746 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1747 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1748 cfg->pg_num = rsvd_qt->b0_ftm; 1749 break; 1750 case DLE_RSVD_QT_B1_FTM: 1751 cfg->pktid = dle_info->ple_free_pg + 1752 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1753 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1754 cfg->pg_num = rsvd_qt->b1_ftm; 1755 break; 1756 default: 1757 return -EINVAL; 1758 } 1759 1760 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1761 1762 return 0; 1763} 1764 1765static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1766{ 1767 struct rtw89_mac_dle_dfi_qempty qempty; 1768 u32 grpnum, qtmp, val32, msk32; 1769 int i, j, ret; 1770 1771 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1772 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1773 1774 for (i = 0; i < grpnum; i++) { 1775 qempty.grpsel = i; 1776 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1777 if (ret) { 1778 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1779 return false; 1780 } 1781 qtmp = qempty.qempty; 1782 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1783 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1784 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1785 return false; 1786 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1787 } 1788 } 1789 1790 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1791 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1792 if (ret) { 1793 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1794 return false; 1795 } 1796 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1797 if ((qempty.qempty & msk32) != msk32) 1798 return false; 1799 1800 if (rtwdev->dbcc_en) { 1801 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1802 if ((qempty.qempty & msk32) != msk32) 1803 return false; 1804 } 1805 1806 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1807 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1808 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1809 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1810 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1811 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1812 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1813 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1814 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1815 1816 return (val32 & msk32) == msk32; 1817} 1818 1819static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1820{ 1821 const struct rtw89_dle_size *wde = cfg->wde_size; 1822 const struct rtw89_dle_size *ple = cfg->ple_size; 1823 u32 used; 1824 1825 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1826 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1827 1828 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1829 used += cfg->rsvd0_size->size; 1830 used += cfg->rsvd1_size->size; 1831 } 1832 1833 return used; 1834} 1835 1836static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1837 enum rtw89_qta_mode mode) 1838{ 1839 u32 size = rtwdev->chip->fifo_size; 1840 1841 if (mode == RTW89_QTA_SCC) 1842 size -= rtwdev->chip->dle_scc_rsvd_size; 1843 1844 return size; 1845} 1846 1847static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1848{ 1849 if (enable) 1850 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1851 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1852 else 1853 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1854 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1855} 1856 1857static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1858{ 1859 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1860 1861 if (enable) { 1862 if (rtwdev->chip->chip_id == RTL8851B) 1863 val |= B_AX_AXIDMA_CLK_EN; 1864 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1865 } else { 1866 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1867 } 1868} 1869 1870static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1871{ 1872 const struct rtw89_dle_size *size_cfg; 1873 u32 val; 1874 u8 bound = 0; 1875 1876 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1877 size_cfg = cfg->wde_size; 1878 1879 switch (size_cfg->pge_size) { 1880 default: 1881 case RTW89_WDE_PG_64: 1882 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1883 B_AX_WDE_PAGE_SEL_MASK); 1884 break; 1885 case RTW89_WDE_PG_128: 1886 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1887 B_AX_WDE_PAGE_SEL_MASK); 1888 break; 1889 case RTW89_WDE_PG_256: 1890 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1891 return -EINVAL; 1892 } 1893 1894 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1895 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1896 B_AX_WDE_FREE_PAGE_NUM_MASK); 1897 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1898 1899 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1900 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1901 * size_cfg->pge_size / DLE_BOUND_UNIT; 1902 size_cfg = cfg->ple_size; 1903 1904 switch (size_cfg->pge_size) { 1905 default: 1906 case RTW89_PLE_PG_64: 1907 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1908 return -EINVAL; 1909 case RTW89_PLE_PG_128: 1910 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1911 B_AX_PLE_PAGE_SEL_MASK); 1912 break; 1913 case RTW89_PLE_PG_256: 1914 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1915 B_AX_PLE_PAGE_SEL_MASK); 1916 break; 1917 } 1918 1919 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1920 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1921 B_AX_PLE_FREE_PAGE_NUM_MASK); 1922 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1923 1924 return 0; 1925} 1926 1927static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1928{ 1929 u32 reg, mask; 1930 u32 ini; 1931 1932 if (wde_or_ple) { 1933 reg = R_AX_WDE_INI_STATUS; 1934 mask = WDE_MGN_INI_RDY; 1935 } else { 1936 reg = R_AX_PLE_INI_STATUS; 1937 mask = PLE_MGN_INI_RDY; 1938 } 1939 1940 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1941 2000, false, rtwdev, reg); 1942} 1943 1944#define INVALID_QT_WCPU U16_MAX 1945#define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1946 do { \ 1947 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1948 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1949 rtw89_write32(rtwdev, \ 1950 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1951 val); \ 1952 } while (0) 1953#define SET_QUOTA(_x, _module, _idx) \ 1954 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1955 1956static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1957 const struct rtw89_wde_quota *min_cfg, 1958 const struct rtw89_wde_quota *max_cfg, 1959 u16 ext_wde_min_qt_wcpu) 1960{ 1961 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1962 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1963 u32 val; 1964 1965 SET_QUOTA(hif, WDE, 0); 1966 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1967 SET_QUOTA(pkt_in, WDE, 3); 1968 SET_QUOTA(cpu_io, WDE, 4); 1969} 1970 1971static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1972 const struct rtw89_ple_quota *min_cfg, 1973 const struct rtw89_ple_quota *max_cfg) 1974{ 1975 u32 val; 1976 1977 SET_QUOTA(cma0_tx, PLE, 0); 1978 SET_QUOTA(cma1_tx, PLE, 1); 1979 SET_QUOTA(c2h, PLE, 2); 1980 SET_QUOTA(h2c, PLE, 3); 1981 SET_QUOTA(wcpu, PLE, 4); 1982 SET_QUOTA(mpdu_proc, PLE, 5); 1983 SET_QUOTA(cma0_dma, PLE, 6); 1984 SET_QUOTA(cma1_dma, PLE, 7); 1985 SET_QUOTA(bb_rpt, PLE, 8); 1986 SET_QUOTA(wd_rel, PLE, 9); 1987 SET_QUOTA(cpu_io, PLE, 10); 1988 if (rtwdev->chip->chip_id == RTL8852C) 1989 SET_QUOTA(tx_rpt, PLE, 11); 1990} 1991 1992int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1993{ 1994 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1995 const struct rtw89_dle_mem *cfg; 1996 u32 val; 1997 1998 if (rtwdev->chip->chip_id == RTL8852C) 1999 return 0; 2000 2001 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2002 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2003 return -EINVAL; 2004 } 2005 2006 if (wow) 2007 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2008 else 2009 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2010 if (!cfg) { 2011 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2012 return -EINVAL; 2013 } 2014 2015 min_cfg = cfg->ple_min_qt; 2016 max_cfg = cfg->ple_max_qt; 2017 SET_QUOTA(cma0_dma, PLE, 6); 2018 SET_QUOTA(cma1_dma, PLE, 7); 2019 2020 return 0; 2021} 2022#undef SET_QUOTA 2023 2024void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2025{ 2026 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2027 2028 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2029 return; 2030 2031 if (enable) 2032 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2033 else 2034 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2035} 2036 2037static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2038 const struct rtw89_dle_mem *cfg, 2039 u16 ext_wde_min_qt_wcpu) 2040{ 2041 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2042 2043 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2044 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2045} 2046 2047int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2048 enum rtw89_qta_mode ext_mode) 2049{ 2050 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2051 const struct rtw89_dle_mem *cfg, *ext_cfg; 2052 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2053 int ret; 2054 2055 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2056 if (ret) 2057 return ret; 2058 2059 cfg = get_dle_mem_cfg(rtwdev, mode); 2060 if (!cfg) { 2061 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2062 ret = -EINVAL; 2063 goto error; 2064 } 2065 2066 if (mode == RTW89_QTA_DLFW) { 2067 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2068 if (!ext_cfg) { 2069 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2070 ext_mode); 2071 ret = -EINVAL; 2072 goto error; 2073 } 2074 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2075 } 2076 2077 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2078 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2079 ret = -EINVAL; 2080 goto error; 2081 } 2082 2083 mac->dle_func_en(rtwdev, false); 2084 mac->dle_clk_en(rtwdev, true); 2085 2086 ret = mac->dle_mix_cfg(rtwdev, cfg); 2087 if (ret) { 2088 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2089 goto error; 2090 } 2091 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2092 2093 mac->dle_func_en(rtwdev, true); 2094 2095 ret = mac->chk_dle_rdy(rtwdev, true); 2096 if (ret) { 2097 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2098 return ret; 2099 } 2100 2101 ret = mac->chk_dle_rdy(rtwdev, false); 2102 if (ret) { 2103 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2104 return ret; 2105 } 2106 2107 return 0; 2108error: 2109 mac->dle_func_en(rtwdev, false); 2110 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2111 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2112 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2113 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2114 2115 return ret; 2116} 2117 2118static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2119 enum rtw89_qta_mode mode) 2120{ 2121 u32 reg, max_preld_size, min_rsvd_size; 2122 2123 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2124 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2125 reg = mac_idx == RTW89_MAC_0 ? 2126 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2127 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2128 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2129 2130 min_rsvd_size = PRELD_AMSDU_SIZE; 2131 reg = mac_idx == RTW89_MAC_0 ? 2132 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2133 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2134 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2135 2136 return 0; 2137} 2138 2139static bool is_qta_poh(struct rtw89_dev *rtwdev) 2140{ 2141 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2142} 2143 2144int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2145 enum rtw89_qta_mode mode) 2146{ 2147 const struct rtw89_chip_info *chip = rtwdev->chip; 2148 2149 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2150 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 2151 return 0; 2152 2153 return preload_init_set(rtwdev, mac_idx, mode); 2154} 2155 2156static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2157{ 2158 u32 msk32; 2159 u32 val32; 2160 2161 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2162 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2163 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2164 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2165 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2166 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2167 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2168 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2169 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2170 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2171 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2172 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2173 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2174 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2175 2176 if ((val32 & msk32) == msk32) 2177 return true; 2178 2179 return false; 2180} 2181 2182static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2183{ 2184 const struct rtw89_chip_info *chip = rtwdev->chip; 2185 2186 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2187 chip->chip_id == RTL8851B) 2188 return; 2189 2190 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2191 SS2F_PATH_WLCPU); 2192} 2193 2194static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2195{ 2196 u32 p_val; 2197 u8 val; 2198 int ret; 2199 2200 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2201 if (ret) 2202 return ret; 2203 2204 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2205 val |= B_AX_SS_EN; 2206 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2207 2208 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2209 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2210 if (ret) { 2211 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2212 return ret; 2213 } 2214 2215 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2216 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2217 2218 _patch_ss2f_path(rtwdev); 2219 2220 return 0; 2221} 2222 2223static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2224{ 2225 int ret; 2226 2227 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2228 if (ret) 2229 return ret; 2230 2231 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2232 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2233 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2234 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2235 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2236 2237 return 0; 2238} 2239 2240static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2241{ 2242 const struct rtw89_chip_info *chip = rtwdev->chip; 2243 u32 val = 0; 2244 int ret; 2245 2246 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2247 if (ret) 2248 return ret; 2249 2250 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2251 /* init clock */ 2252 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2253 /* init TX encryption */ 2254 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2255 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2256 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2257 chip->chip_id == RTL8851B) 2258 val &= ~B_AX_TX_PARTIAL_MODE; 2259 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2260 2261 /* init MIC ICV append */ 2262 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2263 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2264 2265 /* option init */ 2266 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2267 2268 if (chip->chip_id == RTL8852C) 2269 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2270 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2271 2272 return 0; 2273} 2274 2275static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2276{ 2277 int ret; 2278 2279 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2280 if (ret) { 2281 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2282 return ret; 2283 } 2284 2285 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2286 if (ret) { 2287 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2288 return ret; 2289 } 2290 2291 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2292 if (ret) { 2293 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2294 return ret; 2295 } 2296 2297 ret = sta_sch_init_ax(rtwdev); 2298 if (ret) { 2299 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2300 return ret; 2301 } 2302 2303 ret = mpdu_proc_init_ax(rtwdev); 2304 if (ret) { 2305 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2306 return ret; 2307 } 2308 2309 ret = sec_eng_init_ax(rtwdev); 2310 if (ret) { 2311 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2312 return ret; 2313 } 2314 2315 return ret; 2316} 2317 2318static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2319{ 2320 u32 val, reg; 2321 u16 p_val; 2322 int ret; 2323 2324 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2325 if (ret) 2326 return ret; 2327 2328 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2329 2330 val = rtw89_read32(rtwdev, reg); 2331 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2332 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2333 rtw89_write32(rtwdev, reg, val); 2334 2335 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2336 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2337 if (ret) { 2338 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2339 return ret; 2340 } 2341 2342 return 0; 2343} 2344 2345static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2346{ 2347 u32 ret; 2348 u32 reg; 2349 u32 val; 2350 2351 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2352 if (ret) 2353 return ret; 2354 2355 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2356 if (rtwdev->chip->chip_id == RTL8852C) 2357 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2358 SIFS_MACTXEN_T1_V1); 2359 else 2360 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2361 SIFS_MACTXEN_T1); 2362 2363 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2364 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2365 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2366 } 2367 2368 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2369 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2370 2371 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2372 if (rtwdev->chip->chip_id == RTL8852C) { 2373 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2374 B_AX_TX_PARTIAL_MODE); 2375 if (!val) 2376 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2377 SCH_PREBKF_24US); 2378 } else { 2379 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2380 SCH_PREBKF_24US); 2381 } 2382 2383 return 0; 2384} 2385 2386static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2387 enum rtw89_machdr_frame_type type, 2388 enum rtw89_mac_fwd_target fwd_target, 2389 u8 mac_idx) 2390{ 2391 u32 reg; 2392 u32 val; 2393 2394 switch (fwd_target) { 2395 case RTW89_FWD_DONT_CARE: 2396 val = RX_FLTR_FRAME_DROP; 2397 break; 2398 case RTW89_FWD_TO_HOST: 2399 val = RX_FLTR_FRAME_TO_HOST; 2400 break; 2401 case RTW89_FWD_TO_WLAN_CPU: 2402 val = RX_FLTR_FRAME_TO_WLCPU; 2403 break; 2404 default: 2405 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2406 return -EINVAL; 2407 } 2408 2409 switch (type) { 2410 case RTW89_MGNT: 2411 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2412 break; 2413 case RTW89_CTRL: 2414 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2415 break; 2416 case RTW89_DATA: 2417 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2418 break; 2419 default: 2420 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2421 return -EINVAL; 2422 } 2423 rtw89_write32(rtwdev, reg, val); 2424 2425 return 0; 2426} 2427 2428static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2429{ 2430 int ret, i; 2431 u32 mac_ftlr, plcp_ftlr; 2432 2433 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2434 if (ret) 2435 return ret; 2436 2437 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2438 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2439 mac_idx); 2440 if (ret) 2441 return ret; 2442 } 2443 mac_ftlr = rtwdev->hal.rx_fltr; 2444 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2445 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2446 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2447 B_AX_HE_SIGB_CRC_CHK; 2448 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2449 mac_ftlr); 2450 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2451 plcp_ftlr); 2452 2453 return 0; 2454} 2455 2456static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2457{ 2458 u32 reg, val32; 2459 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2460 2461 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2462 B_AX_RSP_CHK_BASIC_NAV; 2463 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2464 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2465 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2466 2467 switch (rtwdev->chip->chip_id) { 2468 case RTL8852A: 2469 case RTL8852B: 2470 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2471 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2472 rtw89_write32(rtwdev, reg, val32); 2473 2474 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2475 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2476 rtw89_write32(rtwdev, reg, val32); 2477 break; 2478 default: 2479 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2480 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2481 rtw89_write32(rtwdev, reg, val32); 2482 2483 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2484 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2485 rtw89_write32(rtwdev, reg, val32); 2486 break; 2487 } 2488} 2489 2490static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2491{ 2492 u32 val, reg; 2493 int ret; 2494 2495 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2496 if (ret) 2497 return ret; 2498 2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2500 val = rtw89_read32(rtwdev, reg); 2501 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2502 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2503 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2504 B_AX_CTN_CHK_INTRA_NAV | 2505 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2506 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2507 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2508 B_AX_CTN_CHK_CCA_P20); 2509 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2510 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2511 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2512 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2513 B_AX_SIFS_CHK_EDCCA); 2514 2515 rtw89_write32(rtwdev, reg, val); 2516 2517 _patch_dis_resp_chk(rtwdev, mac_idx); 2518 2519 return 0; 2520} 2521 2522static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2523{ 2524 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2525 B_AX_WMAC_TF_UP_NAV_EN | 2526 B_AX_WMAC_NAV_UPPER_EN); 2527 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2528 2529 return 0; 2530} 2531 2532static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2533{ 2534 u32 reg; 2535 int ret; 2536 2537 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2538 if (ret) 2539 return ret; 2540 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2541 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2542 2543 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2544 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2545 2546 return 0; 2547} 2548 2549static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2550{ 2551 u32 reg; 2552 int ret; 2553 2554 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2555 if (ret) 2556 return ret; 2557 2558 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2559 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2560 2561 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2562 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2563 2564 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2565 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2566 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2567 2568 return 0; 2569} 2570 2571static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2572{ 2573 const struct rtw89_chip_info *chip = rtwdev->chip; 2574 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2575 u32 reg, val, sifs; 2576 int ret; 2577 2578 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2579 if (ret) 2580 return ret; 2581 2582 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2583 val = rtw89_read32(rtwdev, reg); 2584 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2585 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2586 2587 switch (rtwdev->chip->chip_id) { 2588 case RTL8852A: 2589 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2590 break; 2591 case RTL8852B: 2592 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2593 break; 2594 default: 2595 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2596 break; 2597 } 2598 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2599 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2600 rtw89_write32(rtwdev, reg, val); 2601 2602 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2603 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2604 2605 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2606 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2607 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2608 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2609 2610 return 0; 2611} 2612 2613static void rst_bacam(struct rtw89_dev *rtwdev) 2614{ 2615 u32 val32; 2616 int ret; 2617 2618 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2619 S_AX_BACAM_RST_ALL); 2620 2621 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2622 1, 1000, false, 2623 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2624 if (ret) 2625 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2626} 2627 2628static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2629{ 2630#define TRXCFG_RMAC_CCA_TO 32 2631#define TRXCFG_RMAC_DATA_TO 15 2632#define RX_MAX_LEN_UNIT 512 2633#define PLD_RLS_MAX_PG 127 2634#define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2635 int ret; 2636 u32 reg, rx_max_len, rx_qta; 2637 u16 val; 2638 2639 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2640 if (ret) 2641 return ret; 2642 2643 if (mac_idx == RTW89_MAC_0) 2644 rst_bacam(rtwdev); 2645 2646 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2647 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2648 2649 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2650 val = rtw89_read16(rtwdev, reg); 2651 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2652 B_AX_RX_DLK_DATA_TIME_MASK); 2653 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2654 B_AX_RX_DLK_CCA_TIME_MASK); 2655 rtw89_write16(rtwdev, reg, val); 2656 2657 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2658 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2659 2660 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2661 if (mac_idx == RTW89_MAC_0) 2662 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2663 else 2664 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2665 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2666 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2667 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2668 rx_max_len /= RX_MAX_LEN_UNIT; 2669 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2670 2671 if (rtwdev->chip->chip_id == RTL8852A && 2672 rtwdev->hal.cv == CHIP_CBV) { 2673 rtw89_write16_mask(rtwdev, 2674 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2675 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2676 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2677 BIT(12)); 2678 } 2679 2680 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2681 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2682 2683 return ret; 2684} 2685 2686static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2687{ 2688 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2689 u32 val, reg; 2690 int ret; 2691 2692 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2693 if (ret) 2694 return ret; 2695 2696 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2697 val = rtw89_read32(rtwdev, reg); 2698 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2699 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2700 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2701 rtw89_write32(rtwdev, reg, val); 2702 2703 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2704 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2705 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2706 } 2707 2708 return 0; 2709} 2710 2711bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2712{ 2713 const struct rtw89_dle_mem *cfg; 2714 2715 cfg = get_dle_mem_cfg(rtwdev, mode); 2716 if (!cfg) { 2717 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2718 return false; 2719 } 2720 2721 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2722} 2723 2724static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2725{ 2726 u32 val, reg; 2727 int ret; 2728 2729 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2730 if (ret) 2731 return ret; 2732 2733 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2734 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2735 val = rtw89_read32(rtwdev, reg); 2736 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2737 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2738 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2739 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2740 val |= B_AX_HW_CTS2SELF_EN; 2741 rtw89_write32(rtwdev, reg, val); 2742 2743 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2744 val = rtw89_read32(rtwdev, reg); 2745 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2746 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2747 rtw89_write32(rtwdev, reg, val); 2748 } 2749 2750 if (mac_idx == RTW89_MAC_0) { 2751 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2752 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2753 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2754 B_AX_PTCL_TRIGGER_SS_EN_0 | 2755 B_AX_PTCL_TRIGGER_SS_EN_1 | 2756 B_AX_PTCL_TRIGGER_SS_EN_UL); 2757 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2758 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2759 } else if (mac_idx == RTW89_MAC_1) { 2760 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2761 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2762 } 2763 2764 return 0; 2765} 2766 2767static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2768{ 2769 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2770 u32 reg; 2771 int ret; 2772 2773 if (chip_id != RTL8852B) 2774 return 0; 2775 2776 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2777 if (ret) 2778 return ret; 2779 2780 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2781 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2782 2783 return 0; 2784} 2785 2786static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2787{ 2788 int ret; 2789 2790 ret = scheduler_init_ax(rtwdev, mac_idx); 2791 if (ret) { 2792 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2793 return ret; 2794 } 2795 2796 ret = addr_cam_init_ax(rtwdev, mac_idx); 2797 if (ret) { 2798 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2799 ret); 2800 return ret; 2801 } 2802 2803 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2804 if (ret) { 2805 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2806 ret); 2807 return ret; 2808 } 2809 2810 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2811 if (ret) { 2812 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2813 ret); 2814 return ret; 2815 } 2816 2817 ret = nav_ctrl_init_ax(rtwdev); 2818 if (ret) { 2819 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2820 ret); 2821 return ret; 2822 } 2823 2824 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2825 if (ret) { 2826 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2827 mac_idx, ret); 2828 return ret; 2829 } 2830 2831 ret = tmac_init_ax(rtwdev, mac_idx); 2832 if (ret) { 2833 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2834 return ret; 2835 } 2836 2837 ret = trxptcl_init_ax(rtwdev, mac_idx); 2838 if (ret) { 2839 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2840 return ret; 2841 } 2842 2843 ret = rmac_init_ax(rtwdev, mac_idx); 2844 if (ret) { 2845 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2846 return ret; 2847 } 2848 2849 ret = cmac_com_init_ax(rtwdev, mac_idx); 2850 if (ret) { 2851 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2852 return ret; 2853 } 2854 2855 ret = ptcl_init_ax(rtwdev, mac_idx); 2856 if (ret) { 2857 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2858 return ret; 2859 } 2860 2861 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2862 if (ret) { 2863 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2864 return ret; 2865 } 2866 2867 return ret; 2868} 2869 2870static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2871 struct rtw89_mac_c2h_info *c2h_info) 2872{ 2873 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2874 struct rtw89_mac_h2c_info h2c_info = {0}; 2875 u32 ret; 2876 2877 mac->cnv_efuse_state(rtwdev, false); 2878 2879 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2880 h2c_info.content_len = 0; 2881 2882 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2883 if (ret) 2884 goto out; 2885 2886 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2887 ret = -EINVAL; 2888 2889out: 2890 mac->cnv_efuse_state(rtwdev, true); 2891 2892 return ret; 2893} 2894 2895int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2896{ 2897 struct rtw89_efuse *efuse = &rtwdev->efuse; 2898 struct rtw89_hal *hal = &rtwdev->hal; 2899 const struct rtw89_chip_info *chip = rtwdev->chip; 2900 struct rtw89_mac_c2h_info c2h_info = {0}; 2901 const struct rtw89_c2hreg_phycap *phycap; 2902 u8 tx_nss; 2903 u8 rx_nss; 2904 u8 tx_ant; 2905 u8 rx_ant; 2906 u32 ret; 2907 2908 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2909 if (ret) 2910 return ret; 2911 2912 phycap = &c2h_info.u.phycap; 2913 2914 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2915 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2916 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2917 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2918 2919 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2920 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2921 2922 if (tx_ant == 1) 2923 hal->antenna_tx = RF_B; 2924 if (rx_ant == 1) 2925 hal->antenna_rx = RF_B; 2926 2927 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2928 hal->antenna_tx = RF_B; 2929 hal->tx_path_diversity = true; 2930 } 2931 2932 if (chip->rf_path_num == 1) { 2933 hal->antenna_tx = RF_A; 2934 hal->antenna_rx = RF_A; 2935 if ((efuse->rfe_type % 3) == 2) 2936 hal->ant_diversity = true; 2937 } 2938 2939 rtw89_debug(rtwdev, RTW89_DBG_FW, 2940 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2941 hal->tx_nss, tx_nss, chip->tx_nss, 2942 hal->rx_nss, rx_nss, chip->rx_nss); 2943 rtw89_debug(rtwdev, RTW89_DBG_FW, 2944 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2945 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2946 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2947 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2948 2949 return 0; 2950} 2951 2952static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2953 u16 tx_en_u16, u16 mask_u16) 2954{ 2955 u32 ret; 2956 struct rtw89_mac_c2h_info c2h_info = {0}; 2957 struct rtw89_mac_h2c_info h2c_info = {0}; 2958 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2959 2960 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2961 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2962 2963 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2964 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2965 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2966 2967 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2968 if (ret) 2969 return ret; 2970 2971 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2972 return -EINVAL; 2973 2974 return 0; 2975} 2976 2977static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2978 u16 tx_en, u16 tx_en_mask) 2979{ 2980 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 2981 u16 val; 2982 int ret; 2983 2984 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2985 if (ret) 2986 return ret; 2987 2988 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2989 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2990 tx_en, tx_en_mask); 2991 2992 val = rtw89_read16(rtwdev, reg); 2993 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2994 rtw89_write16(rtwdev, reg, val); 2995 2996 return 0; 2997} 2998 2999static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3000 u32 tx_en, u32 tx_en_mask) 3001{ 3002 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3003 u32 val; 3004 int ret; 3005 3006 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3007 if (ret) 3008 return ret; 3009 3010 val = rtw89_read32(rtwdev, reg); 3011 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3012 rtw89_write32(rtwdev, reg, val); 3013 3014 return 0; 3015} 3016 3017int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3018 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3019{ 3020 int ret; 3021 3022 *tx_en = rtw89_read16(rtwdev, 3023 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3024 3025 switch (sel) { 3026 case RTW89_SCH_TX_SEL_ALL: 3027 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3028 B_AX_CTN_TXEN_ALL_MASK); 3029 if (ret) 3030 return ret; 3031 break; 3032 case RTW89_SCH_TX_SEL_HIQ: 3033 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3034 0, B_AX_CTN_TXEN_HGQ); 3035 if (ret) 3036 return ret; 3037 break; 3038 case RTW89_SCH_TX_SEL_MG0: 3039 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3040 0, B_AX_CTN_TXEN_MGQ); 3041 if (ret) 3042 return ret; 3043 break; 3044 case RTW89_SCH_TX_SEL_MACID: 3045 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3046 B_AX_CTN_TXEN_ALL_MASK); 3047 if (ret) 3048 return ret; 3049 break; 3050 default: 3051 return 0; 3052 } 3053 3054 return 0; 3055} 3056EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3057 3058int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3059 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3060{ 3061 int ret; 3062 3063 *tx_en = rtw89_read32(rtwdev, 3064 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3065 3066 switch (sel) { 3067 case RTW89_SCH_TX_SEL_ALL: 3068 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3069 B_AX_CTN_TXEN_ALL_MASK_V1); 3070 if (ret) 3071 return ret; 3072 break; 3073 case RTW89_SCH_TX_SEL_HIQ: 3074 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3075 0, B_AX_CTN_TXEN_HGQ); 3076 if (ret) 3077 return ret; 3078 break; 3079 case RTW89_SCH_TX_SEL_MG0: 3080 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3081 0, B_AX_CTN_TXEN_MGQ); 3082 if (ret) 3083 return ret; 3084 break; 3085 case RTW89_SCH_TX_SEL_MACID: 3086 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3087 B_AX_CTN_TXEN_ALL_MASK_V1); 3088 if (ret) 3089 return ret; 3090 break; 3091 default: 3092 return 0; 3093 } 3094 3095 return 0; 3096} 3097EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3098 3099int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3100{ 3101 int ret; 3102 3103 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3104 if (ret) 3105 return ret; 3106 3107 return 0; 3108} 3109EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3110 3111int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3112{ 3113 int ret; 3114 3115 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3116 B_AX_CTN_TXEN_ALL_MASK_V1); 3117 if (ret) 3118 return ret; 3119 3120 return 0; 3121} 3122EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3123 3124static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3125{ 3126 u32 val, reg; 3127 int ret; 3128 3129 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3130 val = buf_len; 3131 val |= B_AX_WD_BUF_REQ_EXEC; 3132 rtw89_write32(rtwdev, reg, val); 3133 3134 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3135 3136 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3137 1, 2000, false, rtwdev, reg); 3138 if (ret) 3139 return ret; 3140 3141 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3142 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3143 return -ENOENT; 3144 3145 return 0; 3146} 3147 3148static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3149 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3150{ 3151 u32 val, cmd_type, reg; 3152 int ret; 3153 3154 cmd_type = ctrl_para->cmd_type; 3155 3156 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3157 val = 0; 3158 val = u32_replace_bits(val, ctrl_para->start_pktid, 3159 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3160 val = u32_replace_bits(val, ctrl_para->end_pktid, 3161 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3162 rtw89_write32(rtwdev, reg, val); 3163 3164 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3165 val = 0; 3166 val = u32_replace_bits(val, ctrl_para->src_pid, 3167 B_AX_CPUQ_OP_SRC_PID_MASK); 3168 val = u32_replace_bits(val, ctrl_para->src_qid, 3169 B_AX_CPUQ_OP_SRC_QID_MASK); 3170 val = u32_replace_bits(val, ctrl_para->dst_pid, 3171 B_AX_CPUQ_OP_DST_PID_MASK); 3172 val = u32_replace_bits(val, ctrl_para->dst_qid, 3173 B_AX_CPUQ_OP_DST_QID_MASK); 3174 rtw89_write32(rtwdev, reg, val); 3175 3176 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3177 val = 0; 3178 val = u32_replace_bits(val, cmd_type, 3179 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3180 val = u32_replace_bits(val, ctrl_para->macid, 3181 B_AX_CPUQ_OP_MACID_MASK); 3182 val = u32_replace_bits(val, ctrl_para->pkt_num, 3183 B_AX_CPUQ_OP_PKTNUM_MASK); 3184 val |= B_AX_WD_CPUQ_OP_EXEC; 3185 rtw89_write32(rtwdev, reg, val); 3186 3187 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3188 3189 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3190 1, 2000, false, rtwdev, reg); 3191 if (ret) 3192 return ret; 3193 3194 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3195 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3196 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3197 3198 return 0; 3199} 3200 3201int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3202 bool band1_en) 3203{ 3204 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3205 const struct rtw89_dle_mem *cfg; 3206 3207 cfg = get_dle_mem_cfg(rtwdev, mode); 3208 if (!cfg) { 3209 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3210 return -EINVAL; 3211 } 3212 3213 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3214 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3215 return -EINVAL; 3216 } 3217 3218 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3219 3220 return mac->dle_quota_change(rtwdev, band1_en); 3221} 3222 3223static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3224{ 3225 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3226 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3227 u16 pkt_id; 3228 int ret; 3229 3230 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3231 if (ret) { 3232 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3233 return ret; 3234 } 3235 3236 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3237 ctrl_para.start_pktid = pkt_id; 3238 ctrl_para.end_pktid = pkt_id; 3239 ctrl_para.pkt_num = 0; 3240 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3241 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3242 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3243 if (ret) { 3244 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3245 return -EFAULT; 3246 } 3247 3248 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3249 if (ret) { 3250 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3251 return ret; 3252 } 3253 3254 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3255 ctrl_para.start_pktid = pkt_id; 3256 ctrl_para.end_pktid = pkt_id; 3257 ctrl_para.pkt_num = 0; 3258 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3259 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3260 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3261 if (ret) { 3262 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3263 return -EFAULT; 3264 } 3265 3266 return 0; 3267} 3268 3269static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3270{ 3271 int ret; 3272 u32 reg; 3273 u8 val; 3274 3275 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3276 if (ret) 3277 return ret; 3278 3279 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3280 3281 ret = read_poll_timeout(rtw89_read8, val, 3282 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3283 SW_CVR_DUR_US, 3284 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3285 false, rtwdev, reg); 3286 if (ret) 3287 return ret; 3288 3289 return 0; 3290} 3291 3292static int band1_enable_ax(struct rtw89_dev *rtwdev) 3293{ 3294 int ret, i; 3295 u32 sleep_bak[4] = {0}; 3296 u32 pause_bak[4] = {0}; 3297 u32 tx_en; 3298 3299 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3300 if (ret) { 3301 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3302 return ret; 3303 } 3304 3305 for (i = 0; i < 4; i++) { 3306 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3307 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3308 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3309 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3310 } 3311 3312 ret = band_idle_ck_b(rtwdev, 0); 3313 if (ret) { 3314 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3315 return ret; 3316 } 3317 3318 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3319 if (ret) { 3320 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3321 return ret; 3322 } 3323 3324 for (i = 0; i < 4; i++) { 3325 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3326 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3327 } 3328 3329 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3330 if (ret) { 3331 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3332 return ret; 3333 } 3334 3335 ret = cmac_func_en_ax(rtwdev, 1, true); 3336 if (ret) { 3337 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3338 return ret; 3339 } 3340 3341 ret = cmac_init_ax(rtwdev, 1); 3342 if (ret) { 3343 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3344 return ret; 3345 } 3346 3347 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3348 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3349 3350 return 0; 3351} 3352 3353static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3354{ 3355 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3356 3357 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3358 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3359} 3360 3361static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3362{ 3363 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3364 3365 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3366} 3367 3368static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3369{ 3370 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3371 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3372 3373 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3374 B_AX_TX_GET_ERRPKTID_INT_EN | 3375 B_AX_TX_NXT_ERRPKTID_INT_EN | 3376 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3377 B_AX_TX_OFFSET_ERR_INT_EN | 3378 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3379 if (chip_id == RTL8852C) 3380 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3381 B_AX_TX_ETH_TYPE_ERR_EN | 3382 B_AX_TX_LLC_PRE_ERR_EN | 3383 B_AX_TX_NW_TYPE_ERR_EN | 3384 B_AX_TX_KSRCH_ERR_EN); 3385 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3386 imr->mpdu_tx_imr_set); 3387 3388 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3389 B_AX_GETPKTID_ERR_INT_EN | 3390 B_AX_MHDRLEN_ERR_INT_EN | 3391 B_AX_RPT_ERR_INT_EN); 3392 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3393 imr->mpdu_rx_imr_set); 3394} 3395 3396static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3397{ 3398 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3399 3400 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3401 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3402 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3403 B_AX_PLE_B_PKTID_ERR_INT_EN); 3404 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3405 imr->sta_sch_imr_set); 3406} 3407 3408static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3409{ 3410 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3411 3412 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3413 imr->txpktctl_imr_b0_clr); 3414 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3415 imr->txpktctl_imr_b0_set); 3416 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3417 imr->txpktctl_imr_b1_clr); 3418 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3419 imr->txpktctl_imr_b1_set); 3420} 3421 3422static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3423{ 3424 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3425 3426 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3427 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3428} 3429 3430static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3431{ 3432 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3433 3434 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3435 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3436} 3437 3438static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3439{ 3440 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3441 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3442} 3443 3444static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3445{ 3446 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3447 3448 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3449 imr->host_disp_imr_clr); 3450 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3451 imr->host_disp_imr_set); 3452 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3453 imr->cpu_disp_imr_clr); 3454 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3455 imr->cpu_disp_imr_set); 3456 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3457 imr->other_disp_imr_clr); 3458 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3459 imr->other_disp_imr_set); 3460} 3461 3462static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3463{ 3464 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3465 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3466} 3467 3468static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3469{ 3470 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3471 3472 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3473 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3474 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3475 B_AX_BBRPT_CHINFO_IMR_CLR); 3476 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3477 imr->bbrpt_err_imr_set); 3478 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3479 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3480 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3481} 3482 3483static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3484{ 3485 u32 reg; 3486 3487 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3488 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3489 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3490 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3491} 3492 3493static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3494{ 3495 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3496 u32 reg; 3497 3498 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3499 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3500 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3501} 3502 3503static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3504{ 3505 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3506 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3507 u32 reg; 3508 3509 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3510 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3511 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3512 3513 if (chip_id == RTL8852C) { 3514 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3515 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3516 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3517 } 3518} 3519 3520static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3521{ 3522 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3523 u32 reg; 3524 3525 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3526 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3527 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3528} 3529 3530static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3531{ 3532 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3533 u32 reg; 3534 3535 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3536 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3537 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3538} 3539 3540static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3541{ 3542 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3543 u32 reg; 3544 3545 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3546 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3547 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3548} 3549 3550static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3551 enum rtw89_mac_hwmod_sel sel) 3552{ 3553 int ret; 3554 3555 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3556 if (ret) { 3557 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3558 sel, mac_idx); 3559 return ret; 3560 } 3561 3562 if (sel == RTW89_DMAC_SEL) { 3563 rtw89_wdrls_imr_enable(rtwdev); 3564 rtw89_wsec_imr_enable(rtwdev); 3565 rtw89_mpdu_trx_imr_enable(rtwdev); 3566 rtw89_sta_sch_imr_enable(rtwdev); 3567 rtw89_txpktctl_imr_enable(rtwdev); 3568 rtw89_wde_imr_enable(rtwdev); 3569 rtw89_ple_imr_enable(rtwdev); 3570 rtw89_pktin_imr_enable(rtwdev); 3571 rtw89_dispatcher_imr_enable(rtwdev); 3572 rtw89_cpuio_imr_enable(rtwdev); 3573 rtw89_bbrpt_imr_enable(rtwdev); 3574 } else if (sel == RTW89_CMAC_SEL) { 3575 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3576 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3577 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3578 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3579 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3580 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3581 } else { 3582 return -EINVAL; 3583 } 3584 3585 return 0; 3586} 3587 3588static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3589{ 3590 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3591 3592 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3593 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3594 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3595 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3596 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3597 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3598 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3599} 3600 3601static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3602{ 3603 int ret = 0; 3604 3605 if (enable) { 3606 ret = band1_enable_ax(rtwdev); 3607 if (ret) { 3608 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3609 return ret; 3610 } 3611 3612 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3613 if (ret) { 3614 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3615 return ret; 3616 } 3617 } else { 3618 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3619 return -EINVAL; 3620 } 3621 3622 return 0; 3623} 3624 3625static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3626{ 3627 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3628 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3629 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3630 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3631 B_AX_RLSRPT0_FLTR_MAP_MASK); 3632 } else { 3633 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3634 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3635 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3636 B_AX_RLSRPT0_FLTR_MAP_MASK); 3637 } 3638 3639 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3640 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3641 3642 return 0; 3643} 3644 3645static int trx_init_ax(struct rtw89_dev *rtwdev) 3646{ 3647 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3648 int ret; 3649 3650 ret = dmac_init_ax(rtwdev, 0); 3651 if (ret) { 3652 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3653 return ret; 3654 } 3655 3656 ret = cmac_init_ax(rtwdev, 0); 3657 if (ret) { 3658 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3659 return ret; 3660 } 3661 3662 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3663 ret = dbcc_enable_ax(rtwdev, true); 3664 if (ret) { 3665 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3666 return ret; 3667 } 3668 } 3669 3670 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3671 if (ret) { 3672 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3673 return ret; 3674 } 3675 3676 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3677 if (ret) { 3678 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3679 return ret; 3680 } 3681 3682 err_imr_ctrl_ax(rtwdev, true); 3683 3684 ret = set_host_rpr_ax(rtwdev); 3685 if (ret) { 3686 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3687 return ret; 3688 } 3689 3690 return 0; 3691} 3692 3693static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3694{ 3695#define BACAM_1024BMP_OCC_ENTRY 4 3696#define BACAM_MAX_RU_SUPPORT_B0_STA 1 3697#define BACAM_MAX_RU_SUPPORT_B1_STA 1 3698 const struct rtw89_chip_info *chip = rtwdev->chip; 3699 u8 users, offset; 3700 3701 if (chip->bacam_ver != RTW89_BACAM_V1) 3702 return 0; 3703 3704 offset = 0; 3705 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3706 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3707 3708 offset += users * BACAM_1024BMP_OCC_ENTRY; 3709 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3710 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3711 3712 return 0; 3713} 3714 3715static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3716{ 3717 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3718 u32 val32; 3719 3720 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3721 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3722 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3723 return; 3724 } 3725 3726 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3727 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3728 3729 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3730 val32 |= B_AX_FS_WDT_INT; 3731 val32 &= ~B_AX_FS_WDT_INT_MSK; 3732 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3733} 3734 3735static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3736{ 3737 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3738 3739 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3740 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3741 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3742 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3743 3744 rtw89_disable_fw_watchdog(rtwdev); 3745 3746 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3747 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3748} 3749 3750static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3751 bool dlfw, bool include_bb) 3752{ 3753 u32 val; 3754 int ret; 3755 3756 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3757 return -EFAULT; 3758 3759 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3760 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3761 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3762 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3763 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3764 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3765 3766 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3767 3768 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3769 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3770 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3771 B_AX_WCPU_FWDL_STS_MASK); 3772 3773 if (dlfw) 3774 val |= B_AX_WCPU_FWDL_EN; 3775 3776 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3777 3778 if (rtwdev->chip->chip_id == RTL8852B) 3779 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3780 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3781 3782 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3783 boot_reason); 3784 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3785 3786 if (!dlfw) { 3787 mdelay(5); 3788 3789 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3790 if (ret) 3791 return ret; 3792 } 3793 3794 return 0; 3795} 3796 3797static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3798{ 3799 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3800 u32 val; 3801 3802 if (chip_id == RTL8852C) 3803 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3804 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3805 else 3806 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3807 B_AX_PKT_BUF_EN; 3808 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3809} 3810 3811static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3812{ 3813 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3814 u32 val; 3815 3816 if (chip_id == RTL8851B) 3817 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3818 else 3819 val = B_AX_DISPATCHER_CLK_EN; 3820 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3821 3822 if (chip_id != RTL8852C) 3823 return; 3824 3825 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3826 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3827 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3828 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3829 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3830 3831 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3832 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3833 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3834 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3835 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3836 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3837 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3838} 3839 3840static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3841{ 3842 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3843 int ret; 3844 3845 mac->hci_func_en(rtwdev); 3846 mac->dmac_func_pre_en(rtwdev); 3847 3848 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3849 if (ret) { 3850 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3851 return ret; 3852 } 3853 3854 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3855 if (ret) { 3856 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3857 return ret; 3858 } 3859 3860 return ret; 3861} 3862 3863int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3864{ 3865 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3866 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3867 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3868 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3869 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3870 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3871 3872 return 0; 3873} 3874EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3875 3876int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3877{ 3878 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3879 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3880 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3881 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3882 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3883 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3884 3885 return 0; 3886} 3887EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3888 3889int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3890{ 3891 int ret; 3892 3893 ret = rtw89_mac_power_switch(rtwdev, true); 3894 if (ret) { 3895 rtw89_mac_power_switch(rtwdev, false); 3896 ret = rtw89_mac_power_switch(rtwdev, true); 3897 if (ret) 3898 return ret; 3899 } 3900 3901 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3902 3903 if (include_bb) { 3904 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3905 if (rtwdev->dbcc_en) 3906 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3907 } 3908 3909 ret = rtw89_mac_dmac_pre_init(rtwdev); 3910 if (ret) 3911 return ret; 3912 3913 if (rtwdev->hci.ops->mac_pre_init) { 3914 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3915 if (ret) 3916 return ret; 3917 } 3918 3919 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3920 if (ret) 3921 return ret; 3922 3923 return 0; 3924} 3925 3926int rtw89_mac_init(struct rtw89_dev *rtwdev) 3927{ 3928 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3929 const struct rtw89_chip_info *chip = rtwdev->chip; 3930 bool include_bb = !!chip->bbmcu_nr; 3931 int ret; 3932 3933 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3934 if (ret) 3935 goto fail; 3936 3937 ret = rtw89_chip_enable_bb_rf(rtwdev); 3938 if (ret) 3939 goto fail; 3940 3941 ret = mac->sys_init(rtwdev); 3942 if (ret) 3943 goto fail; 3944 3945 ret = mac->trx_init(rtwdev); 3946 if (ret) 3947 goto fail; 3948 3949 ret = rtw89_mac_feat_init(rtwdev); 3950 if (ret) 3951 goto fail; 3952 3953 if (rtwdev->hci.ops->mac_post_init) { 3954 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3955 if (ret) 3956 goto fail; 3957 } 3958 3959 rtw89_fw_send_all_early_h2c(rtwdev); 3960 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3961 3962 return ret; 3963fail: 3964 rtw89_mac_power_switch(rtwdev, false); 3965 3966 return ret; 3967} 3968 3969static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3970{ 3971 u8 i; 3972 3973 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3974 return; 3975 3976 for (i = 0; i < 4; i++) { 3977 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3978 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3979 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3980 } 3981} 3982 3983static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3984{ 3985 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 3986 return; 3987 3988 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3989 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3990 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3991 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3992 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3993 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3994 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3995 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3996 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3997 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3998} 3999 4000int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4001{ 4002 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4003 u8 grp = macid >> 5; 4004 int ret; 4005 4006 /* If this is called by change_interface() in the case of P2P, it could 4007 * be power-off, so ignore this operation. 4008 */ 4009 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4010 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4011 return 0; 4012 4013 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4014 if (ret) 4015 return ret; 4016 4017 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4018 4019 return 0; 4020} 4021 4022static const struct rtw89_port_reg rtw89_port_base_ax = { 4023 .port_cfg = R_AX_PORT_CFG_P0, 4024 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4025 .bcn_area = R_AX_BCN_AREA_P0, 4026 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4027 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4028 .tbtt_agg = R_AX_TBTT_AGG_P0, 4029 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4030 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4031 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4032 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4033 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4034 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4035 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4036 .tsftr_l = R_AX_TSFTR_LOW_P0, 4037 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4038 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4039 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4040 .mbssid = R_AX_MBSSID_CTRL, 4041 .mbssid_drop = R_AX_MBSSID_DROP_0, 4042 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4043 .ptcl_dbg = R_AX_PTCL_DBG, 4044 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4045 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4046 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4047 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4048 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4049}; 4050 4051static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4052 struct rtw89_vif *rtwvif, u8 type) 4053{ 4054 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4055 const struct rtw89_port_reg *p = mac->port_base; 4056 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 4057 u32 reg_info, reg_ctrl; 4058 u32 val; 4059 int ret; 4060 4061 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx); 4062 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx); 4063 4064 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4065 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4066 fsleep(100); 4067 4068 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4069 true, rtwdev, reg_info, mask); 4070 if (ret) 4071 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4072} 4073 4074static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4075{ 4076 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4077 const struct rtw89_port_reg *p = mac->port_base; 4078 4079 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4080 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 4081 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 4082 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 4083 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4084 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 4085 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 4086 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4087 4088 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 4089 if (rtwvif->port == RTW89_PORT_0) 4090 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 4091 4092 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4093 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4094 fsleep(2000); 4095} 4096 4097#define BCN_INTERVAL 100 4098#define BCN_ERLY_DEF 160 4099#define BCN_SETUP_DEF 2 4100#define BCN_HOLD_DEF 200 4101#define BCN_MASK_DEF 0 4102#define TBTT_ERLY_DEF 5 4103#define BCN_SET_UNIT 32 4104#define BCN_ERLY_SET_DLY (10 * 2) 4105 4106static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4107 struct rtw89_vif *rtwvif) 4108{ 4109 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4110 const struct rtw89_port_reg *p = mac->port_base; 4111 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4112 const struct rtw89_chip_info *chip = rtwdev->chip; 4113 bool need_backup = false; 4114 u32 backup_val; 4115 4116 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4117 return; 4118 4119 if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 4120 need_backup = true; 4121 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 4122 } 4123 4124 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4125 rtw89_mac_bcn_drop(rtwdev, rtwvif); 4126 4127 if (chip->chip_id == RTL8852A) { 4128 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4129 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4130 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4131 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 4132 } 4133 4134 msleep(vif->bss_conf.beacon_int + 1); 4135 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4136 B_AX_BRK_SETUP); 4137 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4138 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 4139 4140 if (need_backup) 4141 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4142} 4143 4144static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4145 struct rtw89_vif *rtwvif, bool en) 4146{ 4147 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4148 const struct rtw89_port_reg *p = mac->port_base; 4149 4150 if (en) 4151 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4152 else 4153 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4154} 4155 4156static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4157 struct rtw89_vif *rtwvif, bool en) 4158{ 4159 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4160 const struct rtw89_port_reg *p = mac->port_base; 4161 4162 if (en) 4163 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4164 else 4165 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4166} 4167 4168static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4169 struct rtw89_vif *rtwvif) 4170{ 4171 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4172 const struct rtw89_port_reg *p = mac->port_base; 4173 4174 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4175 rtwvif->net_type); 4176} 4177 4178static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4179 struct rtw89_vif *rtwvif) 4180{ 4181 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4182 const struct rtw89_port_reg *p = mac->port_base; 4183 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4184 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4185 4186 if (en) 4187 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4188 else 4189 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4190} 4191 4192static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4193 struct rtw89_vif *rtwvif) 4194{ 4195 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4196 const struct rtw89_port_reg *p = mac->port_base; 4197 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4198 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4199 u32 bit = B_AX_RX_BSSID_FIT_EN; 4200 4201 if (en) 4202 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4203 else 4204 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4205} 4206 4207void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4208 struct rtw89_vif *rtwvif, bool en) 4209{ 4210 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4211 const struct rtw89_port_reg *p = mac->port_base; 4212 4213 if (en) 4214 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4215 else 4216 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4217} 4218 4219static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4220 struct rtw89_vif *rtwvif) 4221{ 4222 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4223 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4224 4225 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en); 4226} 4227 4228static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4229 struct rtw89_vif *rtwvif, bool en) 4230{ 4231 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4232 const struct rtw89_port_reg *p = mac->port_base; 4233 4234 if (en) 4235 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4236 else 4237 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4238} 4239 4240static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4241 struct rtw89_vif *rtwvif) 4242{ 4243 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4244 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4245 4246 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4247} 4248 4249void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4250{ 4251 struct rtw89_vif *rtwvif; 4252 4253 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4254 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4255 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4256} 4257 4258static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4259 struct rtw89_vif *rtwvif) 4260{ 4261 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4262 const struct rtw89_port_reg *p = mac->port_base; 4263 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4264 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4265 4266 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4267 bcn_int); 4268} 4269 4270static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4271 struct rtw89_vif *rtwvif) 4272{ 4273 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4274 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4275 const struct rtw89_port_reg *p = mac->port_base; 4276 u8 port = rtwvif->port; 4277 u32 reg; 4278 4279 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4280 rtw89_write8(rtwdev, reg, win); 4281} 4282 4283static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4284 struct rtw89_vif *rtwvif) 4285{ 4286 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4287 const struct rtw89_port_reg *p = mac->port_base; 4288 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4289 u32 addr; 4290 4291 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4292 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4293 4294 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4295 vif->bss_conf.dtim_period); 4296} 4297 4298static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4299 struct rtw89_vif *rtwvif) 4300{ 4301 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4302 const struct rtw89_port_reg *p = mac->port_base; 4303 4304 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4305 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4306} 4307 4308static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4309 struct rtw89_vif *rtwvif) 4310{ 4311 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4312 const struct rtw89_port_reg *p = mac->port_base; 4313 4314 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4315 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4316} 4317 4318static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4319 struct rtw89_vif *rtwvif) 4320{ 4321 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4322 const struct rtw89_port_reg *p = mac->port_base; 4323 4324 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4325 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4326} 4327 4328static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4329 struct rtw89_vif *rtwvif) 4330{ 4331 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4332 const struct rtw89_port_reg *p = mac->port_base; 4333 4334 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4335 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4336} 4337 4338static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4339 struct rtw89_vif *rtwvif) 4340{ 4341 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4342 const struct rtw89_port_reg *p = mac->port_base; 4343 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4344 static const u32 masks[RTW89_PORT_NUM] = { 4345 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4346 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4347 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4348 }; 4349 u8 port = rtwvif->port; 4350 u32 reg_base; 4351 u32 reg; 4352 u8 bss_color; 4353 4354 bss_color = vif->bss_conf.he_bss_color.color; 4355 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4356 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4357 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4358} 4359 4360static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4361 struct rtw89_vif *rtwvif) 4362{ 4363 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4364 const struct rtw89_port_reg *p = mac->port_base; 4365 u8 port = rtwvif->port; 4366 u32 reg; 4367 4368 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4369 return; 4370 4371 if (port == 0) { 4372 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4373 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4374 } 4375} 4376 4377static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4378 struct rtw89_vif *rtwvif) 4379{ 4380 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4381 const struct rtw89_port_reg *p = mac->port_base; 4382 u8 port = rtwvif->port; 4383 u32 reg; 4384 u32 val; 4385 4386 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4387 val = rtw89_read32(rtwdev, reg); 4388 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4389 if (port == 0) 4390 val &= ~BIT(0); 4391 rtw89_write32(rtwdev, reg, val); 4392} 4393 4394static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4395 struct rtw89_vif *rtwvif, bool enable) 4396{ 4397 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4398 const struct rtw89_port_reg *p = mac->port_base; 4399 4400 if (enable) 4401 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4402 B_AX_PORT_FUNC_EN); 4403 else 4404 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4405 B_AX_PORT_FUNC_EN); 4406} 4407 4408static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4409 struct rtw89_vif *rtwvif) 4410{ 4411 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4412 const struct rtw89_port_reg *p = mac->port_base; 4413 4414 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4415 BCN_ERLY_DEF); 4416} 4417 4418static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4419 struct rtw89_vif *rtwvif) 4420{ 4421 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4422 const struct rtw89_port_reg *p = mac->port_base; 4423 u16 val; 4424 4425 if (rtwdev->chip->chip_id != RTL8852C) 4426 return; 4427 4428 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4429 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4430 return; 4431 4432 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4433 B_AX_TBTT_SHIFT_OFST_SIGN; 4434 4435 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4436 B_AX_TBTT_SHIFT_OFST_MASK, val); 4437} 4438 4439void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4440 struct rtw89_vif *rtwvif, 4441 struct rtw89_vif *rtwvif_src, 4442 u16 offset_tu) 4443{ 4444 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4445 const struct rtw89_port_reg *p = mac->port_base; 4446 u32 val, reg; 4447 4448 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4449 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4450 rtwvif->mac_idx); 4451 4452 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4453 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4454 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4455} 4456 4457static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4458 struct rtw89_vif *rtwvif, 4459 struct rtw89_vif *rtwvif_src, 4460 u8 offset, int *n_offset) 4461{ 4462 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4463 return; 4464 4465 /* adjust offset randomly to avoid beacon conflict */ 4466 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4467 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4468 (*n_offset) * offset); 4469 4470 (*n_offset)++; 4471} 4472 4473static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4474{ 4475 struct rtw89_vif *src = NULL, *tmp; 4476 u8 offset = 100, vif_aps = 0; 4477 int n_offset = 1; 4478 4479 rtw89_for_each_rtwvif(rtwdev, tmp) { 4480 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4481 src = tmp; 4482 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4483 vif_aps++; 4484 } 4485 4486 if (vif_aps == 0) 4487 return; 4488 4489 offset /= (vif_aps + 1); 4490 4491 rtw89_for_each_rtwvif(rtwdev, tmp) 4492 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4493} 4494 4495int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4496{ 4497 int ret; 4498 4499 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4500 if (ret) 4501 return ret; 4502 4503 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4504 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4505 4506 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4507 if (ret) 4508 return ret; 4509 4510 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4511 if (ret) 4512 return ret; 4513 4514 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4515 if (ret) 4516 return ret; 4517 4518 ret = rtw89_cam_init(rtwdev, rtwvif); 4519 if (ret) 4520 return ret; 4521 4522 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4523 if (ret) 4524 return ret; 4525 4526 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL); 4527 if (ret) 4528 return ret; 4529 4530 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL); 4531 if (ret) 4532 return ret; 4533 4534 return 0; 4535} 4536 4537int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4538{ 4539 int ret; 4540 4541 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4542 if (ret) 4543 return ret; 4544 4545 rtw89_cam_deinit(rtwdev, rtwvif); 4546 4547 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4548 if (ret) 4549 return ret; 4550 4551 return 0; 4552} 4553 4554int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4555{ 4556 u8 port = rtwvif->port; 4557 4558 if (port >= RTW89_PORT_NUM) 4559 return -EINVAL; 4560 4561 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4562 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4563 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4564 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4565 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4566 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4567 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif); 4568 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4569 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4570 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4571 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4572 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4573 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4574 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4575 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4576 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4577 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4578 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4579 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4580 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4581 rtw89_mac_port_tsf_resync_all(rtwdev); 4582 fsleep(BCN_ERLY_SET_DLY); 4583 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4584 4585 return 0; 4586} 4587 4588int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4589 u64 *tsf) 4590{ 4591 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4592 const struct rtw89_port_reg *p = mac->port_base; 4593 u32 tsf_low, tsf_high; 4594 int ret; 4595 4596 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4597 if (ret) 4598 return ret; 4599 4600 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4601 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4602 *tsf = (u64)tsf_high << 32 | tsf_low; 4603 4604 return 0; 4605} 4606 4607static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4608 struct cfg80211_bss *bss, 4609 void *data) 4610{ 4611 const struct cfg80211_bss_ies *ies; 4612 const struct element *elem; 4613 bool *tolerated = data; 4614 4615 rcu_read_lock(); 4616 ies = rcu_dereference(bss->ies); 4617 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4618 ies->len); 4619 4620 if (!elem || elem->datalen < 10 || 4621 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4622 *tolerated = false; 4623 rcu_read_unlock(); 4624} 4625 4626void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4627 struct ieee80211_vif *vif) 4628{ 4629 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4630 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4631 struct ieee80211_hw *hw = rtwdev->hw; 4632 bool tolerated = true; 4633 u32 reg; 4634 4635 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4636 return; 4637 4638 if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR)) 4639 return; 4640 4641 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper, 4642 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4643 &tolerated); 4644 4645 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4646 rtwvif->mac_idx); 4647 if (tolerated) 4648 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4649 else 4650 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4651} 4652 4653void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4654{ 4655 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4656} 4657 4658int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4659{ 4660 int ret; 4661 4662 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4663 RTW89_MAX_MAC_ID_NUM); 4664 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4665 return -ENOSPC; 4666 4667 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4668 if (ret) 4669 goto release_mac_id; 4670 4671 return 0; 4672 4673release_mac_id: 4674 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4675 4676 return ret; 4677} 4678 4679int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4680{ 4681 int ret; 4682 4683 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4684 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4685 4686 return ret; 4687} 4688 4689static void 4690rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4691{ 4692} 4693 4694static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4695{ 4696 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4697 4698 return band == op->band_type && channel == op->primary_channel; 4699} 4700 4701static void 4702rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4703 u32 len) 4704{ 4705 const struct rtw89_c2h_scanofld *c2h = 4706 (const struct rtw89_c2h_scanofld *)skb->data; 4707 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4708 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4709 struct rtw89_chan new; 4710 u8 reason, status, tx_fail, band, actual_period, expect_period; 4711 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4712 u8 mac_idx, sw_def, fw_def; 4713 u16 chan; 4714 int ret; 4715 4716 if (!rtwvif) 4717 return; 4718 4719 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4720 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4721 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4722 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4723 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4724 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4725 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4726 4727 4728 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4729 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4730 4731 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4732 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4733 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4734 4735 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4736 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4737 expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4738 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4739 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4740 4741 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4742 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4743 sw_def, fw_def, report_tsf, expect_period); 4744 } 4745 4746 switch (reason) { 4747 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4748 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4749 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4750 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4751 ieee80211_stop_queues(rtwdev->hw); 4752 } 4753 return; 4754 case RTW89_SCAN_END_SCAN_NOTIFY: 4755 if (rtwvif && rtwvif->scan_req && 4756 last_chan < rtwvif->scan_req->n_channels) { 4757 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4758 if (ret) { 4759 rtw89_hw_scan_abort(rtwdev, vif); 4760 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4761 } 4762 } else { 4763 rtw89_hw_scan_complete(rtwdev, vif, rtwdev->scan_info.abort); 4764 } 4765 break; 4766 case RTW89_SCAN_ENTER_OP_NOTIFY: 4767 case RTW89_SCAN_ENTER_CH_NOTIFY: 4768 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4769 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4770 &rtwdev->scan_info.op_chan); 4771 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4772 ieee80211_wake_queues(rtwdev->hw); 4773 } else { 4774 rtw89_chan_create(&new, chan, chan, band, 4775 RTW89_CHANNEL_WIDTH_20); 4776 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4777 &new); 4778 } 4779 break; 4780 default: 4781 return; 4782 } 4783} 4784 4785static void 4786rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4787 struct sk_buff *skb) 4788{ 4789 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4790 enum nl80211_cqm_rssi_threshold_event nl_event; 4791 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4792 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4793 u8 type, event, mac_id; 4794 s8 sig; 4795 4796 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4797 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4798 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4799 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4800 4801 if (mac_id != rtwvif->mac_id) 4802 return; 4803 4804 rtw89_debug(rtwdev, RTW89_DBG_FW, 4805 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4806 mac_id, type, sig, event); 4807 4808 switch (type) { 4809 case RTW89_BCN_FLTR_BEACON_LOSS: 4810 if (!rtwdev->scanning && !rtwvif->offchan) 4811 ieee80211_connection_loss(vif); 4812 else 4813 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4814 return; 4815 case RTW89_BCN_FLTR_NOTIFY: 4816 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4817 break; 4818 case RTW89_BCN_FLTR_RSSI: 4819 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4820 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4821 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4822 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4823 else 4824 return; 4825 break; 4826 default: 4827 return; 4828 } 4829 4830 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4831} 4832 4833static void 4834rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4835 u32 len) 4836{ 4837 struct rtw89_vif *rtwvif; 4838 4839 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4840 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4841} 4842 4843static void 4844rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4845{ 4846 /* N.B. This will run in interrupt context. */ 4847 4848 rtw89_debug(rtwdev, RTW89_DBG_FW, 4849 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4850 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4851 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4852 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4853 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4854} 4855 4856static void 4857rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4858{ 4859 /* N.B. This will run in interrupt context. */ 4860 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4861 const struct rtw89_c2h_done_ack *c2h = 4862 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4863 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4864 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4865 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4866 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4867 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4868 struct rtw89_completion_data data = {}; 4869 unsigned int cond; 4870 4871 rtw89_debug(rtwdev, RTW89_DBG_FW, 4872 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4873 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4874 4875 if (h2c_cat != H2C_CAT_MAC) 4876 return; 4877 4878 switch (h2c_class) { 4879 default: 4880 return; 4881 case H2C_CL_MAC_FW_OFLD: 4882 switch (h2c_func) { 4883 default: 4884 return; 4885 case H2C_FUNC_ADD_SCANOFLD_CH: 4886 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4887 break; 4888 case H2C_FUNC_SCANOFLD: 4889 cond = RTW89_SCANOFLD_WAIT_COND_START; 4890 break; 4891 case H2C_FUNC_SCANOFLD_BE: 4892 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 4893 break; 4894 } 4895 4896 data.err = !!h2c_return; 4897 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4898 return; 4899 } 4900} 4901 4902static void 4903rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4904{ 4905 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4906} 4907 4908static void 4909rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4910{ 4911} 4912 4913static void 4914rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4915 u32 len) 4916{ 4917 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4918 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4919 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4920 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4921 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4922 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4923 struct rtw89_completion_data data = {}; 4924 unsigned int cond; 4925 4926 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4927 pkt_id, pkt_op, pkt_len); 4928 4929 data.err = !pkt_len; 4930 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4931 4932 rtw89_complete_cond(wait, cond, &data); 4933} 4934 4935static void 4936rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4937 u32 len) 4938{ 4939 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4940} 4941 4942static void 4943rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4944{ 4945 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4946 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4947 4948 switch (func) { 4949 case H2C_FUNC_ADD_MCC: 4950 case H2C_FUNC_START_MCC: 4951 case H2C_FUNC_STOP_MCC: 4952 case H2C_FUNC_DEL_MCC_GROUP: 4953 case H2C_FUNC_RESET_MCC_GROUP: 4954 case H2C_FUNC_MCC_REQ_TSF: 4955 case H2C_FUNC_MCC_MACID_BITMAP: 4956 case H2C_FUNC_MCC_SYNC: 4957 case H2C_FUNC_MCC_SET_DURATION: 4958 break; 4959 default: 4960 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4961 "invalid MCC C2H RCV ACK: func %d\n", func); 4962 return; 4963 } 4964 4965 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4966 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4967} 4968 4969static void 4970rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4971{ 4972 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4973 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4974 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4975 struct rtw89_completion_data data = {}; 4976 unsigned int cond; 4977 bool next = false; 4978 4979 switch (func) { 4980 case H2C_FUNC_MCC_REQ_TSF: 4981 next = true; 4982 break; 4983 case H2C_FUNC_MCC_MACID_BITMAP: 4984 case H2C_FUNC_MCC_SYNC: 4985 case H2C_FUNC_MCC_SET_DURATION: 4986 break; 4987 case H2C_FUNC_ADD_MCC: 4988 case H2C_FUNC_START_MCC: 4989 case H2C_FUNC_STOP_MCC: 4990 case H2C_FUNC_DEL_MCC_GROUP: 4991 case H2C_FUNC_RESET_MCC_GROUP: 4992 default: 4993 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4994 "invalid MCC C2H REQ ACK: func %d\n", func); 4995 return; 4996 } 4997 4998 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4999 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5000 group, func, retcode); 5001 5002 if (!retcode && next) 5003 return; 5004 5005 data.err = !!retcode; 5006 cond = RTW89_MCC_WAIT_COND(group, func); 5007 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5008} 5009 5010static void 5011rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5012{ 5013 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5014 struct rtw89_completion_data data = {}; 5015 struct rtw89_mac_mcc_tsf_rpt *rpt; 5016 unsigned int cond; 5017 5018 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5019 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5020 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5021 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5022 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5023 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5024 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5025 5026 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5027 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5028 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5029 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5030 5031 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5032 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5033} 5034 5035static void 5036rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5037{ 5038 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5039 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5040 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5041 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5042 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5043 struct rtw89_completion_data data = {}; 5044 unsigned int cond; 5045 bool rsp = true; 5046 bool err; 5047 u8 func; 5048 5049 switch (status) { 5050 case RTW89_MAC_MCC_ADD_ROLE_OK: 5051 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5052 func = H2C_FUNC_ADD_MCC; 5053 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5054 break; 5055 case RTW89_MAC_MCC_START_GROUP_OK: 5056 case RTW89_MAC_MCC_START_GROUP_FAIL: 5057 func = H2C_FUNC_START_MCC; 5058 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5059 break; 5060 case RTW89_MAC_MCC_STOP_GROUP_OK: 5061 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5062 func = H2C_FUNC_STOP_MCC; 5063 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5064 break; 5065 case RTW89_MAC_MCC_DEL_GROUP_OK: 5066 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5067 func = H2C_FUNC_DEL_MCC_GROUP; 5068 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5069 break; 5070 case RTW89_MAC_MCC_RESET_GROUP_OK: 5071 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5072 func = H2C_FUNC_RESET_MCC_GROUP; 5073 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5074 break; 5075 case RTW89_MAC_MCC_SWITCH_CH_OK: 5076 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5077 case RTW89_MAC_MCC_TXNULL0_OK: 5078 case RTW89_MAC_MCC_TXNULL0_FAIL: 5079 case RTW89_MAC_MCC_TXNULL1_OK: 5080 case RTW89_MAC_MCC_TXNULL1_FAIL: 5081 case RTW89_MAC_MCC_SWITCH_EARLY: 5082 case RTW89_MAC_MCC_TBTT: 5083 case RTW89_MAC_MCC_DURATION_START: 5084 case RTW89_MAC_MCC_DURATION_END: 5085 rsp = false; 5086 break; 5087 default: 5088 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5089 "invalid MCC C2H STS RPT: status %d\n", status); 5090 return; 5091 } 5092 5093 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5094 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5095 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5096 5097 if (!rsp) 5098 return; 5099 5100 data.err = err; 5101 cond = RTW89_MCC_WAIT_COND(group, func); 5102 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5103} 5104 5105static void 5106rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5107{ 5108 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5109 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5110 struct rtw89_completion_data data = {}; 5111 struct rtw89_mac_mrc_tsf_rpt *rpt; 5112 unsigned int i; 5113 5114 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5115 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5116 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5117 le32_get_bits(c2h_rpt->w2, 5118 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5119 5120 for (i = 0; i < rpt->num; i++) { 5121 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5122 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5123 5124 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5125 5126 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5127 "MRC C2H TSF RPT: index %u> %llu\n", 5128 i, rpt->tsfs[i]); 5129 } 5130 5131 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5132} 5133 5134static void 5135rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5136{ 5137 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5138 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5139 struct rtw89_completion_data data = {}; 5140 enum rtw89_mac_mrc_status status; 5141 unsigned int cond; 5142 bool next = false; 5143 u32 tsf_high; 5144 u32 tsf_low; 5145 u8 sch_idx; 5146 u8 func; 5147 5148 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5149 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5150 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5151 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5152 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5153 5154 switch (status) { 5155 case RTW89_MAC_MRC_START_SCH_OK: 5156 func = H2C_FUNC_START_MRC; 5157 break; 5158 case RTW89_MAC_MRC_STOP_SCH_OK: 5159 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5160 func = H2C_FUNC_DEL_MRC; 5161 next = true; 5162 break; 5163 case RTW89_MAC_MRC_DEL_SCH_OK: 5164 func = H2C_FUNC_DEL_MRC; 5165 break; 5166 default: 5167 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5168 "invalid MRC C2H STS RPT: status %d\n", status); 5169 return; 5170 } 5171 5172 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5173 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5174 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5175 5176 if (next) 5177 return; 5178 5179 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5180 rtw89_complete_cond(wait, cond, &data); 5181} 5182 5183static 5184void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5185 struct sk_buff *c2h, u32 len) = { 5186 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5187 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5188 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5189 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5190 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5191 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5192 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5193 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5194}; 5195 5196static 5197void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5198 struct sk_buff *c2h, u32 len) = { 5199 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5200 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5201 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5202 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5203}; 5204 5205static 5206void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5207 struct sk_buff *c2h, u32 len) = { 5208 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5209 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5210 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5211 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5212}; 5213 5214static 5215void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5216 struct sk_buff *c2h, u32 len) = { 5217 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5218 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5219}; 5220 5221static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5222 struct sk_buff *skb) 5223{ 5224 const struct rtw89_c2h_scanofld *c2h = 5225 (const struct rtw89_c2h_scanofld *)skb->data; 5226 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5227 struct rtw89_completion_data data = {}; 5228 unsigned int cond; 5229 u8 status, reason; 5230 5231 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5232 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5233 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5234 5235 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5236 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5237 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5238 else 5239 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5240 5241 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5242 } 5243} 5244 5245bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5246 u8 class, u8 func) 5247{ 5248 switch (class) { 5249 default: 5250 return false; 5251 case RTW89_MAC_C2H_CLASS_INFO: 5252 switch (func) { 5253 default: 5254 return false; 5255 case RTW89_MAC_C2H_FUNC_REC_ACK: 5256 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5257 return true; 5258 } 5259 case RTW89_MAC_C2H_CLASS_OFLD: 5260 switch (func) { 5261 default: 5262 return false; 5263 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5264 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5265 return false; 5266 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5267 return true; 5268 } 5269 case RTW89_MAC_C2H_CLASS_MCC: 5270 return true; 5271 case RTW89_MAC_C2H_CLASS_MRC: 5272 return true; 5273 } 5274} 5275 5276void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5277 u32 len, u8 class, u8 func) 5278{ 5279 void (*handler)(struct rtw89_dev *rtwdev, 5280 struct sk_buff *c2h, u32 len) = NULL; 5281 5282 switch (class) { 5283 case RTW89_MAC_C2H_CLASS_INFO: 5284 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5285 handler = rtw89_mac_c2h_info_handler[func]; 5286 break; 5287 case RTW89_MAC_C2H_CLASS_OFLD: 5288 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5289 handler = rtw89_mac_c2h_ofld_handler[func]; 5290 break; 5291 case RTW89_MAC_C2H_CLASS_MCC: 5292 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5293 handler = rtw89_mac_c2h_mcc_handler[func]; 5294 break; 5295 case RTW89_MAC_C2H_CLASS_MRC: 5296 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5297 handler = rtw89_mac_c2h_mrc_handler[func]; 5298 break; 5299 case RTW89_MAC_C2H_CLASS_FWDBG: 5300 return; 5301 default: 5302 rtw89_info(rtwdev, "c2h class %d not support\n", class); 5303 return; 5304 } 5305 if (!handler) { 5306 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5307 func); 5308 return; 5309 } 5310 handler(rtwdev, skb, len); 5311} 5312 5313static 5314bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5315 enum rtw89_phy_idx phy_idx, 5316 u32 reg_base, u32 *cr) 5317{ 5318 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5319 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5320 5321 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5322 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5323 addr); 5324 goto error; 5325 } 5326 5327 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5328 if (mode == RTW89_QTA_SCC) { 5329 rtw89_err(rtwdev, 5330 "[TXPWR] addr=0x%x but hw not enable\n", 5331 addr); 5332 goto error; 5333 } 5334 5335 *cr = addr; 5336 return true; 5337 5338error: 5339 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5340 addr, phy_idx); 5341 5342 return false; 5343} 5344 5345static 5346int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5347{ 5348 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5349 int ret; 5350 5351 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5352 if (ret) 5353 return ret; 5354 5355 if (!enable) { 5356 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5357 return 0; 5358 } 5359 5360 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5361 B_AX_APP_MAC_INFO_RPT | 5362 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5363 B_AX_PPDU_STAT_RPT_CRC32); 5364 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5365 RTW89_PRPT_DEST_HOST); 5366 5367 return 0; 5368} 5369 5370void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5371{ 5372#define MAC_AX_TIME_TH_SH 5 5373#define MAC_AX_LEN_TH_SH 4 5374#define MAC_AX_TIME_TH_MAX 255 5375#define MAC_AX_LEN_TH_MAX 255 5376#define MAC_AX_TIME_TH_DEF 88 5377#define MAC_AX_LEN_TH_DEF 4080 5378 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5379 struct ieee80211_hw *hw = rtwdev->hw; 5380 u32 rts_threshold = hw->wiphy->rts_threshold; 5381 u32 time_th, len_th; 5382 u32 reg; 5383 5384 if (rts_threshold == (u32)-1) { 5385 time_th = MAC_AX_TIME_TH_DEF; 5386 len_th = MAC_AX_LEN_TH_DEF; 5387 } else { 5388 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5389 len_th = rts_threshold; 5390 } 5391 5392 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5393 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5394 5395 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5396 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5397 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5398} 5399 5400void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5401{ 5402 bool empty; 5403 int ret; 5404 5405 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5406 return; 5407 5408 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5409 10000, 200000, false, rtwdev); 5410 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5411 rtw89_info(rtwdev, "timed out to flush queues\n"); 5412} 5413 5414int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5415{ 5416 u8 val; 5417 u16 val16; 5418 u32 val32; 5419 int ret; 5420 5421 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5422 if (rtwdev->chip->chip_id != RTL8851B) 5423 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5424 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5425 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5426 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5427 if (rtwdev->chip->chip_id != RTL8851B) 5428 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5429 5430 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5431 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5432 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5433 5434 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5435 if (ret) { 5436 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5437 return ret; 5438 } 5439 val32 = val32 & B_AX_WL_RX_CTRL; 5440 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5441 if (ret) { 5442 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5443 return ret; 5444 } 5445 5446 switch (coex->pta_mode) { 5447 case RTW89_MAC_AX_COEX_RTK_MODE: 5448 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5449 val &= ~B_AX_BTMODE_MASK; 5450 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5451 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5452 5453 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5454 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5455 5456 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5457 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5458 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5459 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5460 break; 5461 case RTW89_MAC_AX_COEX_CSR_MODE: 5462 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5463 val &= ~B_AX_BTMODE_MASK; 5464 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5465 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5466 5467 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5468 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5469 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5470 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5471 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5472 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5473 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5474 val16 |= B_AX_ENHANCED_BT; 5475 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5476 5477 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5478 break; 5479 default: 5480 return -EINVAL; 5481 } 5482 5483 switch (coex->direction) { 5484 case RTW89_MAC_AX_COEX_INNER: 5485 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5486 val = (val & ~BIT(2)) | BIT(1); 5487 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5488 break; 5489 case RTW89_MAC_AX_COEX_OUTPUT: 5490 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5491 val = val | BIT(1) | BIT(0); 5492 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5493 break; 5494 case RTW89_MAC_AX_COEX_INPUT: 5495 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5496 val = val & ~(BIT(2) | BIT(1)); 5497 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5498 break; 5499 default: 5500 return -EINVAL; 5501 } 5502 5503 return 0; 5504} 5505EXPORT_SYMBOL(rtw89_mac_coex_init); 5506 5507int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5508 const struct rtw89_mac_ax_coex *coex) 5509{ 5510 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5511 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5512 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5513 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5514 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5515 5516 switch (coex->pta_mode) { 5517 case RTW89_MAC_AX_COEX_RTK_MODE: 5518 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5519 MAC_AX_RTK_MODE); 5520 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5521 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5522 break; 5523 case RTW89_MAC_AX_COEX_CSR_MODE: 5524 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5525 MAC_AX_CSR_MODE); 5526 break; 5527 default: 5528 return -EINVAL; 5529 } 5530 5531 return 0; 5532} 5533EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5534 5535int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5536 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5537{ 5538 u32 val = 0, ret; 5539 5540 if (gnt_cfg->band[0].gnt_bt) 5541 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5542 5543 if (gnt_cfg->band[0].gnt_bt_sw_en) 5544 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5545 5546 if (gnt_cfg->band[0].gnt_wl) 5547 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5548 5549 if (gnt_cfg->band[0].gnt_wl_sw_en) 5550 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5551 5552 if (gnt_cfg->band[1].gnt_bt) 5553 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5554 5555 if (gnt_cfg->band[1].gnt_bt_sw_en) 5556 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5557 5558 if (gnt_cfg->band[1].gnt_wl) 5559 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5560 5561 if (gnt_cfg->band[1].gnt_wl_sw_en) 5562 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5563 5564 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5565 if (ret) { 5566 rtw89_err(rtwdev, "Write LTE fail!\n"); 5567 return ret; 5568 } 5569 5570 return 0; 5571} 5572EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5573 5574int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5575 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5576{ 5577 u32 val = 0; 5578 5579 if (gnt_cfg->band[0].gnt_bt) 5580 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5581 B_AX_GNT_BT_TX_VAL; 5582 else 5583 val |= B_AX_WL_ACT_VAL; 5584 5585 if (gnt_cfg->band[0].gnt_bt_sw_en) 5586 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5587 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5588 5589 if (gnt_cfg->band[0].gnt_wl) 5590 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5591 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5592 5593 if (gnt_cfg->band[0].gnt_wl_sw_en) 5594 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5595 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5596 5597 if (gnt_cfg->band[1].gnt_bt) 5598 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5599 B_AX_GNT_BT_TX_VAL; 5600 else 5601 val |= B_AX_WL_ACT_VAL; 5602 5603 if (gnt_cfg->band[1].gnt_bt_sw_en) 5604 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5605 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5606 5607 if (gnt_cfg->band[1].gnt_wl) 5608 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5609 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5610 5611 if (gnt_cfg->band[1].gnt_wl_sw_en) 5612 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5613 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5614 5615 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5616 5617 return 0; 5618} 5619EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5620 5621static 5622int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5623{ 5624 u32 reg; 5625 u16 val; 5626 int ret; 5627 5628 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5629 if (ret) 5630 return ret; 5631 5632 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5633 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5634 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5635 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5636 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5637 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5638 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5639 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5640 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5641 B_AX_PLT_EN; 5642 rtw89_write16(rtwdev, reg, val); 5643 5644 return 0; 5645} 5646 5647void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5648{ 5649 u32 fw_sb; 5650 5651 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5652 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5653 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5654 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5655 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5656 else 5657 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5658 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5659 val = B_AX_TOGGLE | 5660 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5661 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5662 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5663 fsleep(1000); /* avoid BT FW loss information */ 5664} 5665 5666u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5667{ 5668 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5669} 5670 5671int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5672{ 5673 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5674 5675 val = wl ? val | BIT(2) : val & ~BIT(2); 5676 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5677 5678 return 0; 5679} 5680EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5681 5682int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5683{ 5684 struct rtw89_btc *btc = &rtwdev->btc; 5685 struct rtw89_btc_dm *dm = &btc->dm; 5686 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5687 int i; 5688 5689 if (wl) 5690 return 0; 5691 5692 for (i = 0; i < RTW89_PHY_MAX; i++) { 5693 g[i].gnt_bt_sw_en = 1; 5694 g[i].gnt_bt = 1; 5695 g[i].gnt_wl_sw_en = 1; 5696 g[i].gnt_wl = 0; 5697 } 5698 5699 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5700} 5701EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5702 5703bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5704{ 5705 const struct rtw89_chip_info *chip = rtwdev->chip; 5706 u8 val = 0; 5707 5708 if (chip->chip_id == RTL8852C) 5709 return false; 5710 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 5711 chip->chip_id == RTL8851B) 5712 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5713 B_AX_LTE_MUX_CTRL_PATH >> 24); 5714 5715 return !!val; 5716} 5717 5718static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 5719{ 5720 u32 reg; 5721 u16 cnt; 5722 5723 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5724 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5725 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5726 5727 return cnt; 5728} 5729 5730static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5731 bool keep) 5732{ 5733 u32 reg; 5734 5735 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5736 return; 5737 5738 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5739 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5740 if (keep) { 5741 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5742 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5743 BFRP_RX_STANDBY_TIMER_KEEP); 5744 } else { 5745 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5746 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5747 BFRP_RX_STANDBY_TIMER_RELEASE); 5748 } 5749} 5750 5751void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5752{ 5753 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5754 u32 reg; 5755 u32 mask = mac->bfee_ctrl.mask; 5756 5757 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5758 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5759 if (en) { 5760 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5761 rtw89_write32_set(rtwdev, reg, mask); 5762 } else { 5763 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5764 rtw89_write32_clr(rtwdev, reg, mask); 5765 } 5766} 5767 5768static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5769{ 5770 u32 reg; 5771 u32 val32; 5772 int ret; 5773 5774 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5775 if (ret) 5776 return ret; 5777 5778 /* AP mode set tx gid to 63 */ 5779 /* STA mode set tx gid to 0(default) */ 5780 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5781 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5782 5783 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5784 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5785 5786 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5787 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5788 rtw89_write32(rtwdev, reg, val32); 5789 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5790 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5791 5792 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5793 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5794 B_AX_BFMEE_USE_NSTS | 5795 B_AX_BFMEE_CSI_GID_SEL | 5796 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5797 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5798 rtw89_write32(rtwdev, reg, 5799 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5800 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5801 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5802 5803 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5804 rtw89_write32_set(rtwdev, reg, 5805 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5806 5807 return 0; 5808} 5809 5810static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5811 struct ieee80211_vif *vif, 5812 struct ieee80211_sta *sta) 5813{ 5814 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5815 u8 mac_idx = rtwvif->mac_idx; 5816 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5817 u8 port_sel = rtwvif->port; 5818 u8 sound_dim = 3, t; 5819 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5820 u32 reg; 5821 u16 val; 5822 int ret; 5823 5824 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5825 if (ret) 5826 return ret; 5827 5828 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5829 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5830 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5831 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5832 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5833 phy_cap[5]); 5834 sound_dim = min(sound_dim, t); 5835 } 5836 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5837 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5838 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5839 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5840 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5841 sta->deflink.vht_cap.cap); 5842 sound_dim = min(sound_dim, t); 5843 } 5844 nc = min(nc, sound_dim); 5845 nr = min(nr, sound_dim); 5846 5847 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5848 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5849 5850 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5851 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5852 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5853 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5854 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5855 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5856 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5857 5858 if (port_sel == 0) 5859 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5860 else 5861 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5862 5863 rtw89_write16(rtwdev, reg, val); 5864 5865 return 0; 5866} 5867 5868static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5869 struct ieee80211_vif *vif, 5870 struct ieee80211_sta *sta) 5871{ 5872 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5873 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5874 u32 reg; 5875 u8 mac_idx = rtwvif->mac_idx; 5876 int ret; 5877 5878 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5879 if (ret) 5880 return ret; 5881 5882 if (sta->deflink.he_cap.has_he) { 5883 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5884 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5885 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5886 } 5887 if (sta->deflink.vht_cap.vht_supported) { 5888 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5889 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5890 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5891 } 5892 if (sta->deflink.ht_cap.ht_supported) { 5893 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5894 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5895 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5896 } 5897 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5898 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5899 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5900 rtw89_write32(rtwdev, 5901 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5902 rrsc); 5903 5904 return 0; 5905} 5906 5907static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 5908 struct ieee80211_vif *vif, 5909 struct ieee80211_sta *sta) 5910{ 5911 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5912 5913 if (rtw89_sta_has_beamformer_cap(sta)) { 5914 rtw89_debug(rtwdev, RTW89_DBG_BF, 5915 "initialize bfee for new association\n"); 5916 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 5917 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 5918 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 5919 } 5920} 5921 5922void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5923 struct ieee80211_sta *sta) 5924{ 5925 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5926 5927 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5928} 5929 5930void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5931 struct ieee80211_bss_conf *conf) 5932{ 5933 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5934 u8 mac_idx = rtwvif->mac_idx; 5935 __le32 *p; 5936 5937 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5938 5939 p = (__le32 *)conf->mu_group.membership; 5940 rtw89_write32(rtwdev, 5941 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 5942 le32_to_cpu(p[0])); 5943 rtw89_write32(rtwdev, 5944 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 5945 le32_to_cpu(p[1])); 5946 5947 p = (__le32 *)conf->mu_group.position; 5948 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 5949 le32_to_cpu(p[0])); 5950 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 5951 le32_to_cpu(p[1])); 5952 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 5953 le32_to_cpu(p[2])); 5954 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 5955 le32_to_cpu(p[3])); 5956} 5957 5958struct rtw89_mac_bf_monitor_iter_data { 5959 struct rtw89_dev *rtwdev; 5960 struct ieee80211_sta *down_sta; 5961 int count; 5962}; 5963 5964static 5965void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5966{ 5967 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5968 (struct rtw89_mac_bf_monitor_iter_data *)data; 5969 struct ieee80211_sta *down_sta = iter_data->down_sta; 5970 int *count = &iter_data->count; 5971 5972 if (down_sta == sta) 5973 return; 5974 5975 if (rtw89_sta_has_beamformer_cap(sta)) 5976 (*count)++; 5977} 5978 5979void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5980 struct ieee80211_sta *sta, bool disconnect) 5981{ 5982 struct rtw89_mac_bf_monitor_iter_data data; 5983 5984 data.rtwdev = rtwdev; 5985 data.down_sta = disconnect ? sta : NULL; 5986 data.count = 0; 5987 ieee80211_iterate_stations_atomic(rtwdev->hw, 5988 rtw89_mac_bf_monitor_calc_iter, 5989 &data); 5990 5991 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5992 if (data.count) 5993 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5994 else 5995 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5996} 5997 5998void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5999{ 6000 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6001 struct rtw89_vif *rtwvif; 6002 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6003 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6004 bool keep_timer = true; 6005 bool old_keep_timer; 6006 6007 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6008 6009 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6010 keep_timer = false; 6011 6012 if (keep_timer != old_keep_timer) { 6013 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6014 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 6015 keep_timer); 6016 } 6017 6018 if (en == old) 6019 return; 6020 6021 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6022 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 6023} 6024 6025static int 6026__rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6027 u32 tx_time) 6028{ 6029#define MAC_AX_DFLT_TX_TIME 5280 6030 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6031 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6032 u32 reg; 6033 int ret = 0; 6034 6035 if (rtwsta->cctl_tx_time) { 6036 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 6037 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6038 } else { 6039 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6040 if (ret) { 6041 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6042 return ret; 6043 } 6044 6045 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6046 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6047 max_tx_time >> 5); 6048 } 6049 6050 return ret; 6051} 6052 6053int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6054 bool resume, u32 tx_time) 6055{ 6056 int ret = 0; 6057 6058 if (!resume) { 6059 rtwsta->cctl_tx_time = true; 6060 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6061 } else { 6062 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6063 rtwsta->cctl_tx_time = false; 6064 } 6065 6066 return ret; 6067} 6068 6069int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6070 u32 *tx_time) 6071{ 6072 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6073 u32 reg; 6074 int ret = 0; 6075 6076 if (rtwsta->cctl_tx_time) { 6077 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 6078 } else { 6079 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6080 if (ret) { 6081 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6082 return ret; 6083 } 6084 6085 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6086 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6087 } 6088 6089 return ret; 6090} 6091 6092int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6093 struct rtw89_sta *rtwsta, 6094 bool resume, u8 tx_retry) 6095{ 6096 int ret = 0; 6097 6098 rtwsta->data_tx_cnt_lmt = tx_retry; 6099 6100 if (!resume) { 6101 rtwsta->cctl_tx_retry_limit = true; 6102 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6103 } else { 6104 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6105 rtwsta->cctl_tx_retry_limit = false; 6106 } 6107 6108 return ret; 6109} 6110 6111int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6112 struct rtw89_sta *rtwsta, u8 *tx_retry) 6113{ 6114 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6115 u32 reg; 6116 int ret = 0; 6117 6118 if (rtwsta->cctl_tx_retry_limit) { 6119 *tx_retry = rtwsta->data_tx_cnt_lmt; 6120 } else { 6121 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6122 if (ret) { 6123 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6124 return ret; 6125 } 6126 6127 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6128 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6129 } 6130 6131 return ret; 6132} 6133 6134int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6135 struct rtw89_vif *rtwvif, bool en) 6136{ 6137 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6138 u8 mac_idx = rtwvif->mac_idx; 6139 u16 set = mac->muedca_ctrl.mask; 6140 u32 reg; 6141 u32 ret; 6142 6143 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6144 if (ret) 6145 return ret; 6146 6147 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6148 if (en) 6149 rtw89_write16_set(rtwdev, reg, set); 6150 else 6151 rtw89_write16_clr(rtwdev, reg, set); 6152 6153 return 0; 6154} 6155 6156static 6157int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6158{ 6159 u32 val32; 6160 int ret; 6161 6162 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6163 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6164 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6165 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6166 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6167 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6168 6169 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6170 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6171 if (ret) { 6172 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6173 offset, val, mask); 6174 return ret; 6175 } 6176 6177 return 0; 6178} 6179 6180static 6181int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6182{ 6183 u32 val32; 6184 int ret; 6185 6186 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6187 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6188 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6189 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6190 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6191 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6192 6193 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6194 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6195 if (ret) { 6196 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6197 return ret; 6198 } 6199 6200 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6201 6202 return 0; 6203} 6204 6205static 6206void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 6207{ 6208 static const enum rtw89_pkt_drop_sel sels[] = { 6209 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6210 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6211 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6212 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6213 }; 6214 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6215 struct rtw89_pkt_drop_params params = {0}; 6216 int i; 6217 6218 params.mac_band = RTW89_MAC_0; 6219 params.macid = rtwsta->mac_id; 6220 params.port = rtwvif->port; 6221 params.mbssid = 0; 6222 params.tf_trs = rtwvif->trigger; 6223 6224 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6225 params.sel = sels[i]; 6226 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6227 } 6228} 6229 6230static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6231{ 6232 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 6233 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6234 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 6235 struct rtw89_vif *target = data; 6236 6237 if (rtwvif != target) 6238 return; 6239 6240 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 6241} 6242 6243void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6244{ 6245 ieee80211_iterate_stations_atomic(rtwdev->hw, 6246 rtw89_mac_pkt_drop_vif_iter, 6247 rtwvif); 6248} 6249 6250int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6251 enum rtw89_mac_idx band) 6252{ 6253 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6254 struct rtw89_pkt_drop_params params = {0}; 6255 bool empty; 6256 int i, ret = 0, try_cnt = 3; 6257 6258 params.mac_band = band; 6259 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6260 6261 for (i = 0; i < try_cnt; i++) { 6262 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6263 50000, false, rtwdev); 6264 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6265 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6266 else 6267 return 0; 6268 } 6269 return ret; 6270} 6271 6272static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6273{ 6274 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6275 int ret; 6276 6277 if (enable_wow) { 6278 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6279 if (ret) { 6280 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6281 return ret; 6282 } 6283 6284 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6285 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6286 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6287 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6288 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6289 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6290 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6291 } else { 6292 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6293 if (ret) { 6294 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6295 return ret; 6296 } 6297 6298 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6299 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6300 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6301 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6302 } 6303 6304 return 0; 6305} 6306 6307static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6308{ 6309 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6310 6311 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6312} 6313 6314static 6315int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6316 bool h2c_or_fwdl) 6317{ 6318 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6319 u8 val; 6320 6321 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6322 1, FWDL_WAIT_CNT, false, 6323 rtwdev, R_AX_WCPU_FW_CTRL); 6324} 6325 6326const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6327 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6328 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6329 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6330 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6331 .rx_fltr = R_AX_RX_FLTR_OPT, 6332 .port_base = &rtw89_port_base_ax, 6333 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6334 .ps_status = R_AX_PPWRBIT_SETTING, 6335 6336 .muedca_ctrl = { 6337 .addr = R_AX_MUEDCA_EN, 6338 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6339 }, 6340 .bfee_ctrl = { 6341 .addr = R_AX_BFMEE_RESP_OPTION, 6342 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6343 B_AX_BFMEE_HE_NDPA_EN, 6344 }, 6345 .narrow_bw_ru_dis = { 6346 .addr = R_AX_RXTRIG_TEST_USER_2, 6347 .mask = B_AX_RXTRIG_RU26_DIS, 6348 }, 6349 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6350 6351 .check_mac_en = rtw89_mac_check_mac_en_ax, 6352 .sys_init = sys_init_ax, 6353 .trx_init = trx_init_ax, 6354 .hci_func_en = rtw89_mac_hci_func_en_ax, 6355 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6356 .dle_func_en = dle_func_en_ax, 6357 .dle_clk_en = dle_clk_en_ax, 6358 .bf_assoc = rtw89_mac_bf_assoc_ax, 6359 6360 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6361 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6362 6363 .dle_mix_cfg = dle_mix_cfg_ax, 6364 .chk_dle_rdy = chk_dle_rdy_ax, 6365 .dle_buf_req = dle_buf_req_ax, 6366 .hfc_func_en = hfc_func_en_ax, 6367 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6368 .hfc_mix_cfg = hfc_mix_cfg_ax, 6369 .hfc_get_mix_info = hfc_get_mix_info_ax, 6370 .wde_quota_cfg = wde_quota_cfg_ax, 6371 .ple_quota_cfg = ple_quota_cfg_ax, 6372 .set_cpuio = set_cpuio_ax, 6373 .dle_quota_change = dle_quota_change_ax, 6374 6375 .disable_cpu = rtw89_mac_disable_cpu_ax, 6376 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6377 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6378 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6379 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6380 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6381 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6382 6383 .cfg_plt = rtw89_mac_cfg_plt_ax, 6384 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6385 6386 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6387 6388 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6389 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6390 6391 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6392 .dump_err_status = rtw89_mac_dump_err_status_ax, 6393 6394 .is_txq_empty = mac_is_txq_empty_ax, 6395 6396 .add_chan_list = rtw89_hw_scan_add_chan_list, 6397 .scan_offload = rtw89_fw_h2c_scan_offload, 6398 6399 .wow_config_mac = rtw89_wow_config_mac_ax, 6400}; 6401EXPORT_SYMBOL(rtw89_mac_gen_ax); 6402