1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright Fiona Klute <fiona.klute@gmx.de> */
3
4#ifndef __RTW8703B_H__
5#define __RTW8703B_H__
6
7#include "rtw8723x.h"
8
9extern const struct rtw_chip_info rtw8703b_hw_spec;
10
11/* phy status parsing */
12#define VGA_BITS GENMASK(4, 0)
13#define LNA_L_BITS GENMASK(7, 5)
14#define LNA_H_BIT BIT(7)
15/* masks for assembling LNA index from high and low bits */
16#define BIT_LNA_H_MASK BIT(3)
17#define BIT_LNA_L_MASK GENMASK(2, 0)
18
19struct phy_rx_agc_info {
20#ifdef __LITTLE_ENDIAN
21	u8 gain: 7;
22	u8 trsw: 1;
23#else
24	u8 trsw: 1;
25	u8 gain: 7;
26#endif
27} __packed;
28
29/* This struct is called phy_status_rpt_8192cd in the vendor driver,
30 * there might be potential to share it with drivers for other chips
31 * of the same generation.
32 */
33struct phy_status_8703b {
34	struct phy_rx_agc_info path_agc[2];
35	u8 ch_corr[2];
36	u8 cck_sig_qual_ofdm_pwdb_all;
37	/* for CCK: bits 0:4: VGA index, bits 5:7: LNA index (low) */
38	u8 cck_agc_rpt_ofdm_cfosho_a;
39	/* for CCK: bit 7 is high bit of LNA index if long report type */
40	u8 cck_rpt_b_ofdm_cfosho_b;
41	u8 reserved_1;
42	u8 noise_power_db_msb;
43	s8 path_cfotail[2];
44	u8 pcts_mask[2];
45	s8 stream_rxevm[2];
46	u8 path_rxsnr[2];
47	u8 noise_power_db_lsb;
48	u8 reserved_2[3];
49	u8 stream_csi[2];
50	u8 stream_target_csi[2];
51	s8 sig_evm;
52	u8 reserved_3;
53
54#ifdef __LITTLE_ENDIAN
55	u8 antsel_rx_keep_2: 1;
56	u8 sgi_en: 1;
57	u8 rxsc: 2;
58	u8 idle_long: 1;
59	u8 r_ant_train_en: 1;
60	u8 ant_sel_b: 1;
61	u8 ant_sel: 1;
62#else /* __BIG_ENDIAN */
63	u8 ant_sel: 1;
64	u8 ant_sel_b: 1;
65	u8 r_ant_train_en: 1;
66	u8 idle_long: 1;
67	u8 rxsc: 2;
68	u8 sgi_en: 1;
69	u8 antsel_rx_keep_2: 1;
70#endif
71} __packed;
72
73/* Baseband registers */
74#define REG_BB_PWR_SAV5_11N 0x0818
75/* BIT(11) should be 1 for 8703B *and* 8723D, which means LNA uses 4
76 * bit for CCK rates in report, not 3. Vendor driver logs a warning if
77 * it's 0, but handles the case.
78 *
79 * Purpose of other parts of this register is unknown, 8723cs driver
80 * code indicates some other chips use certain bits for antenna
81 * diversity.
82 */
83#define REG_BB_AMP 0x0950
84#define BIT_MASK_RX_LNA (BIT(11))
85
86/* 0xaXX: 40MHz channel settings */
87#define REG_CCK_TXSF2 0x0a24  /* CCK TX filter 2 */
88#define REG_CCK_DBG 0x0a28  /* debug port */
89#define REG_OFDM0_A_TX_AFE 0x0c84
90#define REG_TXIQK_MATRIXB_LSB2_11N 0x0c9c
91#define REG_OFDM0_TX_PSD_NOISE 0x0ce4  /* TX pseudo noise weighting */
92#define REG_IQK_RDY 0x0e90  /* is != 0 when IQK is done */
93
94/* RF registers */
95#define RF_RCK1 0x1E
96
97#define AGG_BURST_NUM 3
98#define AGG_BURST_SIZE 0 /* 1K */
99#define BIT_MASK_AGG_BURST_NUM (GENMASK(3, 2))
100#define BIT_MASK_AGG_BURST_SIZE (GENMASK(5, 4))
101
102#endif /* __RTW8703B_H__ */
103