1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2014 Realtek Corporation.*/ 3 4#include "../wifi.h" 5#include "../pci.h" 6#include "../ps.h" 7#include "reg.h" 8#include "def.h" 9#include "phy.h" 10#include "rf.h" 11#include "dm.h" 12#include "table.h" 13 14static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw, 15 enum radio_path rfpath, u32 offset); 16static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw, 17 enum radio_path rfpath, u32 offset, 18 u32 data); 19static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw); 20static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 21static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw, 22 u8 configtype); 23static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw, 24 u8 configtype); 25static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw); 26static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 27 u32 cmdtableidx, u32 cmdtablesz, 28 enum swchnlcmd_id cmdid, 29 u32 para1, u32 para2, 30 u32 msdelay); 31static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 32 u8 channel, u8 *stage, 33 u8 *step, u32 *delay); 34static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 35 enum wireless_mode wirelessmode, 36 u8 txpwridx); 37static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw); 38static void rtl92ee_phy_set_io(struct ieee80211_hw *hw); 39 40u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 41{ 42 struct rtl_priv *rtlpriv = rtl_priv(hw); 43 u32 returnvalue, originalvalue, bitshift; 44 45 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 46 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); 47 originalvalue = rtl_read_dword(rtlpriv, regaddr); 48 bitshift = calculate_bit_shift(bitmask); 49 returnvalue = (originalvalue & bitmask) >> bitshift; 50 51 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 53 bitmask, regaddr, originalvalue); 54 55 return returnvalue; 56} 57 58void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, 59 u32 bitmask, u32 data) 60{ 61 struct rtl_priv *rtlpriv = rtl_priv(hw); 62 u32 originalvalue, bitshift; 63 64 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 65 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 66 regaddr, bitmask, data); 67 68 if (bitmask != MASKDWORD) { 69 originalvalue = rtl_read_dword(rtlpriv, regaddr); 70 bitshift = calculate_bit_shift(bitmask); 71 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 72 } 73 74 rtl_write_dword(rtlpriv, regaddr, data); 75 76 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 77 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 78 regaddr, bitmask, data); 79} 80 81u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw, 82 enum radio_path rfpath, u32 regaddr, u32 bitmask) 83{ 84 struct rtl_priv *rtlpriv = rtl_priv(hw); 85 u32 original_value, readback_value, bitshift; 86 87 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 88 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 89 regaddr, rfpath, bitmask); 90 91 spin_lock(&rtlpriv->locks.rf_lock); 92 93 original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr); 94 bitshift = calculate_bit_shift(bitmask); 95 readback_value = (original_value & bitmask) >> bitshift; 96 97 spin_unlock(&rtlpriv->locks.rf_lock); 98 99 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 100 "regaddr(%#x),rfpath(%#x),bitmask(%#x),original_value(%#x)\n", 101 regaddr, rfpath, bitmask, original_value); 102 103 return readback_value; 104} 105 106void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw, 107 enum radio_path rfpath, 108 u32 addr, u32 bitmask, u32 data) 109{ 110 struct rtl_priv *rtlpriv = rtl_priv(hw); 111 u32 original_value, bitshift; 112 113 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 114 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 115 addr, bitmask, data, rfpath); 116 117 spin_lock(&rtlpriv->locks.rf_lock); 118 119 if (bitmask != RFREG_OFFSET_MASK) { 120 original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr); 121 bitshift = calculate_bit_shift(bitmask); 122 data = (original_value & (~bitmask)) | (data << bitshift); 123 } 124 125 _rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data); 126 127 spin_unlock(&rtlpriv->locks.rf_lock); 128 129 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 130 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 131 addr, bitmask, data, rfpath); 132} 133 134static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw, 135 enum radio_path rfpath, u32 offset) 136{ 137 struct rtl_priv *rtlpriv = rtl_priv(hw); 138 struct rtl_phy *rtlphy = &rtlpriv->phy; 139 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 140 u32 newoffset; 141 u32 tmplong, tmplong2; 142 u8 rfpi_enable = 0; 143 u32 retvalue; 144 145 offset &= 0xff; 146 newoffset = offset; 147 if (RT_CANNOT_IO(hw)) { 148 pr_err("return all one\n"); 149 return 0xFFFFFFFF; 150 } 151 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 152 if (rfpath == RF90_PATH_A) 153 tmplong2 = tmplong; 154 else 155 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 156 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 157 (newoffset << 23) | BLSSIREADEDGE; 158 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 159 tmplong & (~BLSSIREADEDGE)); 160 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 161 udelay(20); 162 if (rfpath == RF90_PATH_A) 163 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 164 BIT(8)); 165 else if (rfpath == RF90_PATH_B) 166 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 167 BIT(8)); 168 if (rfpi_enable) 169 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 170 BLSSIREADBACKDATA); 171 else 172 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 173 BLSSIREADBACKDATA); 174 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 175 "RFR-%d Addr[0x%x]=0x%x\n", 176 rfpath, pphyreg->rf_rb, retvalue); 177 return retvalue; 178} 179 180static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw, 181 enum radio_path rfpath, u32 offset, 182 u32 data) 183{ 184 u32 data_and_addr; 185 u32 newoffset; 186 struct rtl_priv *rtlpriv = rtl_priv(hw); 187 struct rtl_phy *rtlphy = &rtlpriv->phy; 188 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 189 190 if (RT_CANNOT_IO(hw)) { 191 pr_err("stop\n"); 192 return; 193 } 194 offset &= 0xff; 195 newoffset = offset; 196 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 197 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 198 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, 199 "RFW-%d Addr[0x%x]=0x%x\n", rfpath, 200 pphyreg->rf3wire_offset, data_and_addr); 201} 202 203bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw) 204{ 205 return _rtl92ee_phy_config_mac_with_headerfile(hw); 206} 207 208bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw) 209{ 210 struct rtl_priv *rtlpriv = rtl_priv(hw); 211 bool rtstatus = true; 212 u16 regval; 213 u32 tmp; 214 u8 crystal_cap; 215 216 phy_init_bb_rf_register_def(hw); 217 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 218 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 219 regval | BIT(13) | BIT(0) | BIT(1)); 220 221 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); 222 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 223 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | 224 FEN_BB_GLB_RSTN | FEN_BBRSTB); 225 226 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 227 228 tmp = rtl_read_dword(rtlpriv, 0x4c); 229 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); 230 231 rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw); 232 233 crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F; 234 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, 235 (crystal_cap | (crystal_cap << 6))); 236 return rtstatus; 237} 238 239bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw) 240{ 241 return rtl92ee_phy_rf6052_config(hw); 242} 243 244static bool _check_condition(struct ieee80211_hw *hw, 245 const u32 condition) 246{ 247 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 248 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 249 u32 _board = rtlefuse->board_type; /*need efuse define*/ 250 u32 _interface = rtlhal->interface; 251 u32 _platform = 0x08;/*SupportPlatform */ 252 u32 cond = condition; 253 254 if (condition == 0xCDCDCDCD) 255 return true; 256 257 cond = condition & 0xFF; 258 if ((_board != cond) && (cond != 0xFF)) 259 return false; 260 261 cond = condition & 0xFF00; 262 cond = cond >> 8; 263 if ((_interface & cond) == 0 && cond != 0x07) 264 return false; 265 266 cond = condition & 0xFF0000; 267 cond = cond >> 16; 268 if ((_platform & cond) == 0 && cond != 0x0F) 269 return false; 270 271 return true; 272} 273 274static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data, 275 enum radio_path rfpath, u32 regaddr) 276{ 277 if (addr == 0xfe || addr == 0xffe) { 278 mdelay(50); 279 } else { 280 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); 281 udelay(1); 282 283 if (addr == 0xb6) { 284 u32 getvalue; 285 u8 count = 0; 286 287 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); 288 udelay(1); 289 290 while ((getvalue >> 8) != (data >> 8)) { 291 count++; 292 rtl_set_rfreg(hw, rfpath, regaddr, 293 RFREG_OFFSET_MASK, data); 294 udelay(1); 295 getvalue = rtl_get_rfreg(hw, rfpath, addr, 296 MASKDWORD); 297 if (count > 5) 298 break; 299 } 300 } 301 302 if (addr == 0xb2) { 303 u32 getvalue; 304 u8 count = 0; 305 306 getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD); 307 udelay(1); 308 309 while (getvalue != data) { 310 count++; 311 rtl_set_rfreg(hw, rfpath, regaddr, 312 RFREG_OFFSET_MASK, data); 313 udelay(1); 314 rtl_set_rfreg(hw, rfpath, 0x18, 315 RFREG_OFFSET_MASK, 0x0fc07); 316 udelay(1); 317 getvalue = rtl_get_rfreg(hw, rfpath, addr, 318 MASKDWORD); 319 if (count > 5) 320 break; 321 } 322 } 323 } 324} 325 326static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw, 327 u32 addr, u32 data) 328{ 329 u32 content = 0x1000; /*RF Content: radio_a_txt*/ 330 u32 maskforphyset = (u32)(content & 0xE000); 331 332 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A, 333 addr | maskforphyset); 334} 335 336static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw, 337 u32 addr, u32 data) 338{ 339 u32 content = 0x1001; /*RF Content: radio_b_txt*/ 340 u32 maskforphyset = (u32)(content & 0xE000); 341 342 _rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B, 343 addr | maskforphyset); 344} 345 346static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw, 347 u32 addr, u32 data) 348{ 349 if (addr == 0xfe) 350 mdelay(50); 351 else if (addr == 0xfd) 352 mdelay(5); 353 else if (addr == 0xfc) 354 mdelay(1); 355 else if (addr == 0xfb) 356 udelay(50); 357 else if (addr == 0xfa) 358 udelay(5); 359 else if (addr == 0xf9) 360 udelay(1); 361 else 362 rtl_set_bbreg(hw, addr, MASKDWORD , data); 363 364 udelay(1); 365} 366 367static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw) 368{ 369 struct rtl_priv *rtlpriv = rtl_priv(hw); 370 struct rtl_phy *rtlphy = &rtlpriv->phy; 371 372 u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0; 373 374 for (; band <= BAND_ON_5G; ++band) 375 for (; rf < TX_PWR_BY_RATE_NUM_RF; ++rf) 376 for (; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum) 377 for (; sec < TX_PWR_BY_RATE_NUM_SECTION; ++sec) 378 rtlphy->tx_power_by_rate_offset 379 [band][rf][txnum][sec] = 0; 380} 381 382static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw, 383 u8 band, u8 path, 384 u8 rate_section, u8 txnum, 385 u8 value) 386{ 387 struct rtl_priv *rtlpriv = rtl_priv(hw); 388 struct rtl_phy *rtlphy = &rtlpriv->phy; 389 390 if (path > RF90_PATH_D) { 391 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 392 "Invalid Rf Path %d\n", path); 393 return; 394 } 395 396 if (band == BAND_ON_2_4G) { 397 switch (rate_section) { 398 case CCK: 399 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; 400 break; 401 case OFDM: 402 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value; 403 break; 404 case HT_MCS0_MCS7: 405 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value; 406 break; 407 case HT_MCS8_MCS15: 408 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value; 409 break; 410 default: 411 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 412 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n", 413 rate_section, path, txnum); 414 break; 415 } 416 } else { 417 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 418 "Invalid Band %d\n", band); 419 } 420} 421 422static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw, 423 u8 band, u8 path, u8 txnum, 424 u8 rate_section) 425{ 426 struct rtl_priv *rtlpriv = rtl_priv(hw); 427 struct rtl_phy *rtlphy = &rtlpriv->phy; 428 u8 value = 0; 429 430 if (path > RF90_PATH_D) { 431 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 432 "Invalid Rf Path %d\n", path); 433 return 0; 434 } 435 436 if (band == BAND_ON_2_4G) { 437 switch (rate_section) { 438 case CCK: 439 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; 440 break; 441 case OFDM: 442 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1]; 443 break; 444 case HT_MCS0_MCS7: 445 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2]; 446 break; 447 case HT_MCS8_MCS15: 448 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3]; 449 break; 450 default: 451 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 452 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n", 453 rate_section, path, txnum); 454 break; 455 } 456 } else { 457 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 458 "Invalid Band %d()\n", band); 459 } 460 return value; 461} 462 463static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw) 464{ 465 struct rtl_priv *rtlpriv = rtl_priv(hw); 466 struct rtl_phy *rtlphy = &rtlpriv->phy; 467 u16 raw = 0; 468 u8 base = 0, path = 0; 469 470 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) { 471 if (path == RF90_PATH_A) { 472 raw = (u16)(rtlphy->tx_power_by_rate_offset 473 [BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 474 0xFF; 475 base = (raw >> 4) * 10 + (raw & 0xF); 476 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, 477 path, CCK, RF_1TX, 478 base); 479 } else if (path == RF90_PATH_B) { 480 raw = (u16)(rtlphy->tx_power_by_rate_offset 481 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 482 0xFF; 483 base = (raw >> 4) * 10 + (raw & 0xF); 484 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, 485 path, CCK, RF_1TX, 486 base); 487 } 488 raw = (u16)(rtlphy->tx_power_by_rate_offset 489 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF; 490 base = (raw >> 4) * 10 + (raw & 0xF); 491 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, 492 OFDM, RF_1TX, base); 493 494 raw = (u16)(rtlphy->tx_power_by_rate_offset 495 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF; 496 base = (raw >> 4) * 10 + (raw & 0xF); 497 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, 498 HT_MCS0_MCS7, RF_1TX, 499 base); 500 501 raw = (u16)(rtlphy->tx_power_by_rate_offset 502 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF; 503 base = (raw >> 4) * 10 + (raw & 0xF); 504 _rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, 505 HT_MCS8_MCS15, RF_2TX, 506 base); 507 } 508} 509 510static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start, 511 u8 end, u8 base) 512{ 513 s8 i = 0; 514 u8 tmp = 0; 515 u32 temp_data = 0; 516 517 for (i = 3; i >= 0; --i) { 518 if (i >= start && i <= end) { 519 /* Get the exact value */ 520 tmp = (u8)(*data >> (i * 8)) & 0xF; 521 tmp += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10; 522 523 /* Change the value to a relative value */ 524 tmp = (tmp > base) ? tmp - base : base - tmp; 525 } else { 526 tmp = (u8)(*data >> (i * 8)) & 0xFF; 527 } 528 temp_data <<= 8; 529 temp_data |= tmp; 530 } 531 *data = temp_data; 532} 533 534static void phy_convert_txpwr_dbm_to_rel_val(struct ieee80211_hw *hw) 535{ 536 struct rtl_priv *rtlpriv = rtl_priv(hw); 537 struct rtl_phy *rtlphy = &rtlpriv->phy; 538 u8 base = 0, rf = 0, band = BAND_ON_2_4G; 539 540 for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) { 541 if (rf == RF90_PATH_A) { 542 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, 543 rf, RF_1TX, 544 CCK); 545 _phy_convert_txpower_dbm_to_relative_value( 546 &rtlphy->tx_power_by_rate_offset 547 [band][rf][RF_1TX][2], 548 1, 1, base); 549 _phy_convert_txpower_dbm_to_relative_value( 550 &rtlphy->tx_power_by_rate_offset 551 [band][rf][RF_1TX][3], 552 1, 3, base); 553 } else if (rf == RF90_PATH_B) { 554 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, 555 rf, RF_1TX, 556 CCK); 557 _phy_convert_txpower_dbm_to_relative_value( 558 &rtlphy->tx_power_by_rate_offset 559 [band][rf][RF_1TX][3], 560 0, 0, base); 561 _phy_convert_txpower_dbm_to_relative_value( 562 &rtlphy->tx_power_by_rate_offset 563 [band][rf][RF_1TX][2], 564 1, 3, base); 565 } 566 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, 567 RF_1TX, OFDM); 568 _phy_convert_txpower_dbm_to_relative_value( 569 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0], 570 0, 3, base); 571 _phy_convert_txpower_dbm_to_relative_value( 572 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][1], 573 0, 3, base); 574 575 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, 576 RF_1TX, 577 HT_MCS0_MCS7); 578 _phy_convert_txpower_dbm_to_relative_value( 579 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][4], 580 0, 3, base); 581 _phy_convert_txpower_dbm_to_relative_value( 582 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][5], 583 0, 3, base); 584 585 base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf, 586 RF_2TX, 587 HT_MCS8_MCS15); 588 _phy_convert_txpower_dbm_to_relative_value( 589 &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][6], 590 0, 3, base); 591 592 _phy_convert_txpower_dbm_to_relative_value( 593 &rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][7], 594 0, 3, base); 595 } 596 597 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 598 "<==%s\n", __func__); 599} 600 601static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw) 602{ 603 _rtl92ee_phy_store_txpower_by_rate_base(hw); 604 phy_convert_txpwr_dbm_to_rel_val(hw); 605} 606 607static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw) 608{ 609 struct rtl_priv *rtlpriv = rtl_priv(hw); 610 struct rtl_phy *rtlphy = &rtlpriv->phy; 611 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 612 bool rtstatus; 613 614 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_PHY_REG); 615 if (!rtstatus) { 616 pr_err("Write BB Reg Fail!!\n"); 617 return false; 618 } 619 620 _rtl92ee_phy_init_tx_power_by_rate(hw); 621 if (!rtlefuse->autoload_failflag) { 622 rtlphy->pwrgroup_cnt = 0; 623 rtstatus = 624 phy_config_bb_with_pghdrfile(hw, BASEBAND_CONFIG_PHY_REG); 625 } 626 _rtl92ee_phy_txpower_by_rate_configuration(hw); 627 if (!rtstatus) { 628 pr_err("BB_PG Reg Fail!!\n"); 629 return false; 630 } 631 rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_AGC_TAB); 632 if (!rtstatus) { 633 pr_err("AGC Table Fail\n"); 634 return false; 635 } 636 rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw, 637 RFPGA0_XA_HSSIPARAMETER2, 638 0x200)); 639 640 return true; 641} 642 643static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 644{ 645 struct rtl_priv *rtlpriv = rtl_priv(hw); 646 u32 i; 647 u32 arraylength; 648 u32 *ptrarray; 649 650 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8192EMACPHY_Array\n"); 651 arraylength = RTL8192EE_MAC_ARRAY_LEN; 652 ptrarray = RTL8192EE_MAC_ARRAY; 653 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 654 "Img:RTL8192EE_MAC_ARRAY LEN %d\n", arraylength); 655 for (i = 0; i < arraylength; i = i + 2) 656 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); 657 return true; 658} 659 660#define READ_NEXT_PAIR(v1, v2, i) \ 661 do { \ 662 i += 2; \ 663 v1 = array[i]; \ 664 v2 = array[i+1]; \ 665 } while (0) 666 667static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw, 668 u8 configtype) 669{ 670 int i; 671 u32 *array; 672 u16 len; 673 struct rtl_priv *rtlpriv = rtl_priv(hw); 674 u32 v1 = 0, v2 = 0; 675 676 if (configtype == BASEBAND_CONFIG_PHY_REG) { 677 len = RTL8192EE_PHY_REG_ARRAY_LEN; 678 array = RTL8192EE_PHY_REG_ARRAY; 679 680 for (i = 0; i < len; i = i + 2) { 681 v1 = array[i]; 682 v2 = array[i+1]; 683 if (v1 < 0xcdcdcdcd) { 684 _rtl92ee_config_bb_reg(hw, v1, v2); 685 } else {/*This line is the start line of branch.*/ 686 /* to protect READ_NEXT_PAIR not overrun */ 687 if (i >= len - 2) 688 break; 689 690 if (!_check_condition(hw , array[i])) { 691 /*Discard the following pairs*/ 692 READ_NEXT_PAIR(v1, v2, i); 693 while (v2 != 0xDEAD && 694 v2 != 0xCDEF && 695 v2 != 0xCDCD && i < len - 2) { 696 READ_NEXT_PAIR(v1, v2, i); 697 } 698 i -= 2; /* prevent from for-loop += 2*/ 699 } else { 700 /* Configure matched pairs and 701 * skip to end of if-else. 702 */ 703 READ_NEXT_PAIR(v1, v2, i); 704 while (v2 != 0xDEAD && 705 v2 != 0xCDEF && 706 v2 != 0xCDCD && i < len - 2) { 707 _rtl92ee_config_bb_reg(hw, v1, 708 v2); 709 READ_NEXT_PAIR(v1, v2, i); 710 } 711 712 while (v2 != 0xDEAD && i < len - 2) 713 READ_NEXT_PAIR(v1, v2, i); 714 } 715 } 716 } 717 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 718 len = RTL8192EE_AGC_TAB_ARRAY_LEN; 719 array = RTL8192EE_AGC_TAB_ARRAY; 720 721 for (i = 0; i < len; i = i + 2) { 722 v1 = array[i]; 723 v2 = array[i+1]; 724 if (v1 < 0xCDCDCDCD) { 725 rtl_set_bbreg(hw, array[i], MASKDWORD, 726 array[i + 1]); 727 udelay(1); 728 continue; 729 } else{/*This line is the start line of branch.*/ 730 /* to protect READ_NEXT_PAIR not overrun */ 731 if (i >= len - 2) 732 break; 733 734 if (!_check_condition(hw , array[i])) { 735 /*Discard the following pairs*/ 736 READ_NEXT_PAIR(v1, v2, i); 737 while (v2 != 0xDEAD && 738 v2 != 0xCDEF && 739 v2 != 0xCDCD && 740 i < len - 2) { 741 READ_NEXT_PAIR(v1, v2, i); 742 } 743 i -= 2; /* prevent from for-loop += 2*/ 744 } else { 745 /* Configure matched pairs and 746 * skip to end of if-else. 747 */ 748 READ_NEXT_PAIR(v1, v2, i); 749 while (v2 != 0xDEAD && 750 v2 != 0xCDEF && 751 v2 != 0xCDCD && 752 i < len - 2) { 753 rtl_set_bbreg(hw, 754 array[i], 755 MASKDWORD, 756 array[i + 1]); 757 udelay(1); 758 READ_NEXT_PAIR(v1 , v2 , i); 759 } 760 761 while (v2 != 0xDEAD && 762 i < len - 2) { 763 READ_NEXT_PAIR(v1 , v2 , i); 764 } 765 } 766 } 767 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 768 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", 769 array[i], 770 array[i + 1]); 771 } 772 } 773 return true; 774} 775 776static u8 _rtl92ee_get_rate_section_index(u32 regaddr) 777{ 778 u8 index = 0; 779 780 switch (regaddr) { 781 case RTXAGC_A_RATE18_06: 782 case RTXAGC_B_RATE18_06: 783 index = 0; 784 break; 785 case RTXAGC_A_RATE54_24: 786 case RTXAGC_B_RATE54_24: 787 index = 1; 788 break; 789 case RTXAGC_A_CCK1_MCS32: 790 case RTXAGC_B_CCK1_55_MCS32: 791 index = 2; 792 break; 793 case RTXAGC_B_CCK11_A_CCK2_11: 794 index = 3; 795 break; 796 case RTXAGC_A_MCS03_MCS00: 797 case RTXAGC_B_MCS03_MCS00: 798 index = 4; 799 break; 800 case RTXAGC_A_MCS07_MCS04: 801 case RTXAGC_B_MCS07_MCS04: 802 index = 5; 803 break; 804 case RTXAGC_A_MCS11_MCS08: 805 case RTXAGC_B_MCS11_MCS08: 806 index = 6; 807 break; 808 case RTXAGC_A_MCS15_MCS12: 809 case RTXAGC_B_MCS15_MCS12: 810 index = 7; 811 break; 812 default: 813 regaddr &= 0xFFF; 814 if (regaddr >= 0xC20 && regaddr <= 0xC4C) 815 index = (u8)((regaddr - 0xC20) / 4); 816 else if (regaddr >= 0xE20 && regaddr <= 0xE4C) 817 index = (u8)((regaddr - 0xE20) / 4); 818 break; 819 } 820 return index; 821} 822 823static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw, 824 enum band_type band, 825 enum radio_path rfpath, 826 u32 txnum, u32 regaddr, 827 u32 bitmask, u32 data) 828{ 829 struct rtl_priv *rtlpriv = rtl_priv(hw); 830 struct rtl_phy *rtlphy = &rtlpriv->phy; 831 u8 section = _rtl92ee_get_rate_section_index(regaddr); 832 833 if (band != BAND_ON_2_4G && band != BAND_ON_5G) { 834 rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band); 835 return; 836 } 837 838 if (rfpath > MAX_RF_PATH - 1) { 839 rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, 840 "Invalid RfPath %d\n", rfpath); 841 return; 842 } 843 if (txnum > MAX_RF_PATH - 1) { 844 rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum); 845 return; 846 } 847 848 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][section] = data; 849} 850 851static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw, 852 u8 configtype) 853{ 854 struct rtl_priv *rtlpriv = rtl_priv(hw); 855 int i; 856 u32 *phy_regarray_table_pg; 857 u16 phy_regarray_pg_len; 858 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; 859 860 phy_regarray_pg_len = RTL8192EE_PHY_REG_ARRAY_PG_LEN; 861 phy_regarray_table_pg = RTL8192EE_PHY_REG_ARRAY_PG; 862 863 if (configtype == BASEBAND_CONFIG_PHY_REG) { 864 for (i = 0; i < phy_regarray_pg_len; i = i + 6) { 865 v1 = phy_regarray_table_pg[i]; 866 v2 = phy_regarray_table_pg[i+1]; 867 v3 = phy_regarray_table_pg[i+2]; 868 v4 = phy_regarray_table_pg[i+3]; 869 v5 = phy_regarray_table_pg[i+4]; 870 v6 = phy_regarray_table_pg[i+5]; 871 872 if (v1 < 0xcdcdcdcd) { 873 _rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3, 874 v4, v5, v6); 875 continue; 876 } 877 } 878 } else { 879 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, 880 "configtype != BaseBand_Config_PHY_REG\n"); 881 } 882 return true; 883} 884 885#define READ_NEXT_RF_PAIR(v1, v2, i) \ 886 do { \ 887 i += 2; \ 888 v1 = array[i]; \ 889 v2 = array[i+1]; \ 890 } while (0) 891 892bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 893 enum radio_path rfpath) 894{ 895 struct rtl_priv *rtlpriv = rtl_priv(hw); 896 int i; 897 u32 *array; 898 u16 len; 899 u32 v1 = 0, v2 = 0; 900 901 switch (rfpath) { 902 case RF90_PATH_A: 903 len = RTL8192EE_RADIOA_ARRAY_LEN; 904 array = RTL8192EE_RADIOA_ARRAY; 905 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 906 "Radio_A:RTL8192EE_RADIOA_ARRAY %d\n", len); 907 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 908 for (i = 0; i < len; i = i + 2) { 909 v1 = array[i]; 910 v2 = array[i+1]; 911 if (v1 < 0xcdcdcdcd) { 912 _rtl92ee_config_rf_radio_a(hw, v1, v2); 913 continue; 914 } else {/*This line is the start line of branch.*/ 915 /* to protect READ_NEXT_PAIR not overrun */ 916 if (i >= len - 2) 917 break; 918 919 if (!_check_condition(hw , array[i])) { 920 /*Discard the following pairs*/ 921 READ_NEXT_RF_PAIR(v1, v2, i); 922 while (v2 != 0xDEAD && 923 v2 != 0xCDEF && 924 v2 != 0xCDCD && i < len - 2) { 925 READ_NEXT_RF_PAIR(v1, v2, i); 926 } 927 i -= 2; /* prevent from for-loop += 2*/ 928 } else { 929 /* Configure matched pairs and 930 * skip to end of if-else. 931 */ 932 READ_NEXT_RF_PAIR(v1, v2, i); 933 while (v2 != 0xDEAD && 934 v2 != 0xCDEF && 935 v2 != 0xCDCD && i < len - 2) { 936 _rtl92ee_config_rf_radio_a(hw, 937 v1, 938 v2); 939 READ_NEXT_RF_PAIR(v1, v2, i); 940 } 941 942 while (v2 != 0xDEAD && i < len - 2) 943 READ_NEXT_RF_PAIR(v1, v2, i); 944 } 945 } 946 } 947 break; 948 949 case RF90_PATH_B: 950 len = RTL8192EE_RADIOB_ARRAY_LEN; 951 array = RTL8192EE_RADIOB_ARRAY; 952 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 953 "Radio_A:RTL8192EE_RADIOB_ARRAY %d\n", len); 954 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 955 for (i = 0; i < len; i = i + 2) { 956 v1 = array[i]; 957 v2 = array[i+1]; 958 if (v1 < 0xcdcdcdcd) { 959 _rtl92ee_config_rf_radio_b(hw, v1, v2); 960 continue; 961 } else {/*This line is the start line of branch.*/ 962 /* to protect READ_NEXT_PAIR not overrun */ 963 if (i >= len - 2) 964 break; 965 966 if (!_check_condition(hw , array[i])) { 967 /*Discard the following pairs*/ 968 READ_NEXT_RF_PAIR(v1, v2, i); 969 while (v2 != 0xDEAD && 970 v2 != 0xCDEF && 971 v2 != 0xCDCD && i < len - 2) { 972 READ_NEXT_RF_PAIR(v1, v2, i); 973 } 974 i -= 2; /* prevent from for-loop += 2*/ 975 } else { 976 /* Configure matched pairs and 977 * skip to end of if-else. 978 */ 979 READ_NEXT_RF_PAIR(v1, v2, i); 980 while (v2 != 0xDEAD && 981 v2 != 0xCDEF && 982 v2 != 0xCDCD && i < len - 2) { 983 _rtl92ee_config_rf_radio_b(hw, 984 v1, 985 v2); 986 READ_NEXT_RF_PAIR(v1, v2, i); 987 } 988 989 while (v2 != 0xDEAD && i < len - 2) 990 READ_NEXT_RF_PAIR(v1, v2, i); 991 } 992 } 993 } 994 break; 995 case RF90_PATH_C: 996 case RF90_PATH_D: 997 break; 998 } 999 return true; 1000} 1001 1002void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 1003{ 1004 struct rtl_priv *rtlpriv = rtl_priv(hw); 1005 struct rtl_phy *rtlphy = &rtlpriv->phy; 1006 1007 rtlphy->default_initialgain[0] = 1008 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 1009 rtlphy->default_initialgain[1] = 1010 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 1011 rtlphy->default_initialgain[2] = 1012 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 1013 rtlphy->default_initialgain[3] = 1014 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 1015 1016 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1017 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 1018 rtlphy->default_initialgain[0], 1019 rtlphy->default_initialgain[1], 1020 rtlphy->default_initialgain[2], 1021 rtlphy->default_initialgain[3]); 1022 1023 rtlphy->framesync = (u8)rtl_get_bbreg(hw, 1024 ROFDM0_RXDETECTOR3, MASKBYTE0); 1025 rtlphy->framesync_c34 = rtl_get_bbreg(hw, 1026 ROFDM0_RXDETECTOR2, MASKDWORD); 1027 1028 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, 1029 "Default framesync (0x%x) = 0x%x\n", 1030 ROFDM0_RXDETECTOR3, rtlphy->framesync); 1031} 1032 1033static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw) 1034{ 1035 struct rtl_priv *rtlpriv = rtl_priv(hw); 1036 struct rtl_phy *rtlphy = &rtlpriv->phy; 1037 1038 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 1039 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 1040 1041 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 1042 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 1043 1044 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 1045 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 1046 1047 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 1048 RFPGA0_XA_LSSIPARAMETER; 1049 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 1050 RFPGA0_XB_LSSIPARAMETER; 1051 1052 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 1053 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 1054 1055 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 1056 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 1057 1058 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; 1059 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; 1060} 1061 1062void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 1063{ 1064 struct rtl_priv *rtlpriv = rtl_priv(hw); 1065 struct rtl_phy *rtlphy = &rtlpriv->phy; 1066 u8 txpwr_level; 1067 long txpwr_dbm; 1068 1069 txpwr_level = rtlphy->cur_cck_txpwridx; 1070 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, 1071 txpwr_level); 1072 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 1073 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > 1074 txpwr_dbm) 1075 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 1076 txpwr_level); 1077 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 1078 if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 1079 txpwr_level) > txpwr_dbm) 1080 txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, 1081 WIRELESS_MODE_N_24G, 1082 txpwr_level); 1083 *powerlevel = txpwr_dbm; 1084} 1085 1086static u8 _rtl92ee_phy_get_ratesection_intxpower_byrate(enum radio_path path, 1087 u8 rate) 1088{ 1089 u8 rate_section = 0; 1090 1091 switch (rate) { 1092 case DESC92C_RATE1M: 1093 rate_section = 2; 1094 break; 1095 case DESC92C_RATE2M: 1096 case DESC92C_RATE5_5M: 1097 if (path == RF90_PATH_A) 1098 rate_section = 3; 1099 else if (path == RF90_PATH_B) 1100 rate_section = 2; 1101 break; 1102 case DESC92C_RATE11M: 1103 rate_section = 3; 1104 break; 1105 case DESC92C_RATE6M: 1106 case DESC92C_RATE9M: 1107 case DESC92C_RATE12M: 1108 case DESC92C_RATE18M: 1109 rate_section = 0; 1110 break; 1111 case DESC92C_RATE24M: 1112 case DESC92C_RATE36M: 1113 case DESC92C_RATE48M: 1114 case DESC92C_RATE54M: 1115 rate_section = 1; 1116 break; 1117 case DESC92C_RATEMCS0: 1118 case DESC92C_RATEMCS1: 1119 case DESC92C_RATEMCS2: 1120 case DESC92C_RATEMCS3: 1121 rate_section = 4; 1122 break; 1123 case DESC92C_RATEMCS4: 1124 case DESC92C_RATEMCS5: 1125 case DESC92C_RATEMCS6: 1126 case DESC92C_RATEMCS7: 1127 rate_section = 5; 1128 break; 1129 case DESC92C_RATEMCS8: 1130 case DESC92C_RATEMCS9: 1131 case DESC92C_RATEMCS10: 1132 case DESC92C_RATEMCS11: 1133 rate_section = 6; 1134 break; 1135 case DESC92C_RATEMCS12: 1136 case DESC92C_RATEMCS13: 1137 case DESC92C_RATEMCS14: 1138 case DESC92C_RATEMCS15: 1139 rate_section = 7; 1140 break; 1141 default: 1142 WARN_ONCE(true, "rtl8192ee: Rate_Section is Illegal\n"); 1143 break; 1144 } 1145 return rate_section; 1146} 1147 1148static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw, 1149 enum band_type band, 1150 enum radio_path rf, u8 rate) 1151{ 1152 struct rtl_priv *rtlpriv = rtl_priv(hw); 1153 struct rtl_phy *rtlphy = &rtlpriv->phy; 1154 u8 shift = 0, sec, tx_num; 1155 s8 diff = 0; 1156 1157 sec = _rtl92ee_phy_get_ratesection_intxpower_byrate(rf, rate); 1158 tx_num = RF_TX_NUM_NONIMPLEMENT; 1159 1160 if (tx_num == RF_TX_NUM_NONIMPLEMENT) { 1161 if ((rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS15)) 1162 tx_num = RF_2TX; 1163 else 1164 tx_num = RF_1TX; 1165 } 1166 1167 switch (rate) { 1168 case DESC92C_RATE1M: 1169 case DESC92C_RATE6M: 1170 case DESC92C_RATE24M: 1171 case DESC92C_RATEMCS0: 1172 case DESC92C_RATEMCS4: 1173 case DESC92C_RATEMCS8: 1174 case DESC92C_RATEMCS12: 1175 shift = 0; 1176 break; 1177 case DESC92C_RATE2M: 1178 case DESC92C_RATE9M: 1179 case DESC92C_RATE36M: 1180 case DESC92C_RATEMCS1: 1181 case DESC92C_RATEMCS5: 1182 case DESC92C_RATEMCS9: 1183 case DESC92C_RATEMCS13: 1184 shift = 8; 1185 break; 1186 case DESC92C_RATE5_5M: 1187 case DESC92C_RATE12M: 1188 case DESC92C_RATE48M: 1189 case DESC92C_RATEMCS2: 1190 case DESC92C_RATEMCS6: 1191 case DESC92C_RATEMCS10: 1192 case DESC92C_RATEMCS14: 1193 shift = 16; 1194 break; 1195 case DESC92C_RATE11M: 1196 case DESC92C_RATE18M: 1197 case DESC92C_RATE54M: 1198 case DESC92C_RATEMCS3: 1199 case DESC92C_RATEMCS7: 1200 case DESC92C_RATEMCS11: 1201 case DESC92C_RATEMCS15: 1202 shift = 24; 1203 break; 1204 default: 1205 WARN_ONCE(true, "rtl8192ee: Rate_Section is Illegal\n"); 1206 break; 1207 } 1208 1209 diff = (u8)(rtlphy->tx_power_by_rate_offset[band][rf][tx_num][sec] >> 1210 shift) & 0xff; 1211 1212 return diff; 1213} 1214 1215static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw, 1216 enum radio_path rfpath, u8 rate, 1217 u8 bw, u8 channel) 1218{ 1219 struct rtl_priv *rtlpriv = rtl_priv(hw); 1220 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 1221 u8 index = (channel - 1); 1222 u8 tx_power = 0; 1223 u8 diff = 0; 1224 1225 if (channel < 1 || channel > 14) { 1226 index = 0; 1227 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_DMESG, 1228 "Illegal channel!!\n"); 1229 } 1230 1231 if (IS_CCK_RATE((s8)rate)) 1232 tx_power = rtlefuse->txpwrlevel_cck[rfpath][index]; 1233 else if (DESC92C_RATE6M <= rate) 1234 tx_power = rtlefuse->txpwrlevel_ht40_1s[rfpath][index]; 1235 1236 /* OFDM-1T*/ 1237 if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M && 1238 !IS_CCK_RATE((s8)rate)) 1239 tx_power += rtlefuse->txpwr_legacyhtdiff[rfpath][TX_1S]; 1240 1241 /* BW20-1S, BW20-2S */ 1242 if (bw == HT_CHANNEL_WIDTH_20) { 1243 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15) 1244 tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_1S]; 1245 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15) 1246 tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_2S]; 1247 } else if (bw == HT_CHANNEL_WIDTH_20_40) {/* BW40-1S, BW40-2S */ 1248 if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15) 1249 tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_1S]; 1250 if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15) 1251 tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_2S]; 1252 } 1253 1254 if (rtlefuse->eeprom_regulatory != 2) 1255 diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G, 1256 rfpath, rate); 1257 1258 tx_power += diff; 1259 1260 if (tx_power > MAX_POWER_INDEX) 1261 tx_power = MAX_POWER_INDEX; 1262 1263 return tx_power; 1264} 1265 1266static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx, 1267 enum radio_path rfpath, u8 rate) 1268{ 1269 struct rtl_priv *rtlpriv = rtl_priv(hw); 1270 1271 if (rfpath == RF90_PATH_A) { 1272 switch (rate) { 1273 case DESC92C_RATE1M: 1274 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, 1275 pwr_idx); 1276 break; 1277 case DESC92C_RATE2M: 1278 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1, 1279 pwr_idx); 1280 break; 1281 case DESC92C_RATE5_5M: 1282 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2, 1283 pwr_idx); 1284 break; 1285 case DESC92C_RATE11M: 1286 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3, 1287 pwr_idx); 1288 break; 1289 case DESC92C_RATE6M: 1290 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0, 1291 pwr_idx); 1292 break; 1293 case DESC92C_RATE9M: 1294 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1, 1295 pwr_idx); 1296 break; 1297 case DESC92C_RATE12M: 1298 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2, 1299 pwr_idx); 1300 break; 1301 case DESC92C_RATE18M: 1302 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3, 1303 pwr_idx); 1304 break; 1305 case DESC92C_RATE24M: 1306 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0, 1307 pwr_idx); 1308 break; 1309 case DESC92C_RATE36M: 1310 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1, 1311 pwr_idx); 1312 break; 1313 case DESC92C_RATE48M: 1314 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2, 1315 pwr_idx); 1316 break; 1317 case DESC92C_RATE54M: 1318 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3, 1319 pwr_idx); 1320 break; 1321 case DESC92C_RATEMCS0: 1322 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, 1323 pwr_idx); 1324 break; 1325 case DESC92C_RATEMCS1: 1326 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, 1327 pwr_idx); 1328 break; 1329 case DESC92C_RATEMCS2: 1330 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, 1331 pwr_idx); 1332 break; 1333 case DESC92C_RATEMCS3: 1334 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, 1335 pwr_idx); 1336 break; 1337 case DESC92C_RATEMCS4: 1338 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, 1339 pwr_idx); 1340 break; 1341 case DESC92C_RATEMCS5: 1342 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, 1343 pwr_idx); 1344 break; 1345 case DESC92C_RATEMCS6: 1346 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, 1347 pwr_idx); 1348 break; 1349 case DESC92C_RATEMCS7: 1350 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, 1351 pwr_idx); 1352 break; 1353 case DESC92C_RATEMCS8: 1354 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, 1355 pwr_idx); 1356 break; 1357 case DESC92C_RATEMCS9: 1358 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, 1359 pwr_idx); 1360 break; 1361 case DESC92C_RATEMCS10: 1362 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, 1363 pwr_idx); 1364 break; 1365 case DESC92C_RATEMCS11: 1366 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, 1367 pwr_idx); 1368 break; 1369 case DESC92C_RATEMCS12: 1370 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, 1371 pwr_idx); 1372 break; 1373 case DESC92C_RATEMCS13: 1374 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, 1375 pwr_idx); 1376 break; 1377 case DESC92C_RATEMCS14: 1378 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, 1379 pwr_idx); 1380 break; 1381 case DESC92C_RATEMCS15: 1382 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, 1383 pwr_idx); 1384 break; 1385 default: 1386 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1387 "Invalid Rate!!\n"); 1388 break; 1389 } 1390 } else if (rfpath == RF90_PATH_B) { 1391 switch (rate) { 1392 case DESC92C_RATE1M: 1393 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1, 1394 pwr_idx); 1395 break; 1396 case DESC92C_RATE2M: 1397 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2, 1398 pwr_idx); 1399 break; 1400 case DESC92C_RATE5_5M: 1401 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3, 1402 pwr_idx); 1403 break; 1404 case DESC92C_RATE11M: 1405 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, 1406 pwr_idx); 1407 break; 1408 case DESC92C_RATE6M: 1409 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0, 1410 pwr_idx); 1411 break; 1412 case DESC92C_RATE9M: 1413 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1, 1414 pwr_idx); 1415 break; 1416 case DESC92C_RATE12M: 1417 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2, 1418 pwr_idx); 1419 break; 1420 case DESC92C_RATE18M: 1421 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3, 1422 pwr_idx); 1423 break; 1424 case DESC92C_RATE24M: 1425 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0, 1426 pwr_idx); 1427 break; 1428 case DESC92C_RATE36M: 1429 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1, 1430 pwr_idx); 1431 break; 1432 case DESC92C_RATE48M: 1433 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2, 1434 pwr_idx); 1435 break; 1436 case DESC92C_RATE54M: 1437 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3, 1438 pwr_idx); 1439 break; 1440 case DESC92C_RATEMCS0: 1441 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, 1442 pwr_idx); 1443 break; 1444 case DESC92C_RATEMCS1: 1445 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, 1446 pwr_idx); 1447 break; 1448 case DESC92C_RATEMCS2: 1449 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, 1450 pwr_idx); 1451 break; 1452 case DESC92C_RATEMCS3: 1453 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, 1454 pwr_idx); 1455 break; 1456 case DESC92C_RATEMCS4: 1457 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, 1458 pwr_idx); 1459 break; 1460 case DESC92C_RATEMCS5: 1461 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, 1462 pwr_idx); 1463 break; 1464 case DESC92C_RATEMCS6: 1465 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, 1466 pwr_idx); 1467 break; 1468 case DESC92C_RATEMCS7: 1469 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, 1470 pwr_idx); 1471 break; 1472 case DESC92C_RATEMCS8: 1473 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, 1474 pwr_idx); 1475 break; 1476 case DESC92C_RATEMCS9: 1477 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, 1478 pwr_idx); 1479 break; 1480 case DESC92C_RATEMCS10: 1481 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, 1482 pwr_idx); 1483 break; 1484 case DESC92C_RATEMCS11: 1485 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, 1486 pwr_idx); 1487 break; 1488 case DESC92C_RATEMCS12: 1489 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, 1490 pwr_idx); 1491 break; 1492 case DESC92C_RATEMCS13: 1493 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, 1494 pwr_idx); 1495 break; 1496 case DESC92C_RATEMCS14: 1497 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, 1498 pwr_idx); 1499 break; 1500 case DESC92C_RATEMCS15: 1501 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, 1502 pwr_idx); 1503 break; 1504 default: 1505 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, 1506 "Invalid Rate!!\n"); 1507 break; 1508 } 1509 } else { 1510 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n"); 1511 } 1512} 1513 1514static void phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw, 1515 enum radio_path rfpath, u8 bw, 1516 u8 channel, u8 *rates, u8 size) 1517{ 1518 u8 i; 1519 u8 power_index; 1520 1521 for (i = 0; i < size; i++) { 1522 power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i], 1523 bw, channel); 1524 _rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]); 1525 } 1526} 1527 1528static void phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw, 1529 enum radio_path rfpath, 1530 u8 channel, 1531 enum rate_section section) 1532{ 1533 struct rtl_priv *rtlpriv = rtl_priv(hw); 1534 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1535 struct rtl_phy *rtlphy = &rtlpriv->phy; 1536 1537 if (section == CCK) { 1538 u8 cck_rates[] = {DESC92C_RATE1M, DESC92C_RATE2M, 1539 DESC92C_RATE5_5M, DESC92C_RATE11M}; 1540 if (rtlhal->current_bandtype == BAND_ON_2_4G) 1541 phy_set_txpower_index_by_rate_array(hw, rfpath, 1542 rtlphy->current_chan_bw, 1543 channel, cck_rates, 4); 1544 } else if (section == OFDM) { 1545 u8 ofdm_rates[] = {DESC92C_RATE6M, DESC92C_RATE9M, 1546 DESC92C_RATE12M, DESC92C_RATE18M, 1547 DESC92C_RATE24M, DESC92C_RATE36M, 1548 DESC92C_RATE48M, DESC92C_RATE54M}; 1549 phy_set_txpower_index_by_rate_array(hw, rfpath, 1550 rtlphy->current_chan_bw, 1551 channel, ofdm_rates, 8); 1552 } else if (section == HT_MCS0_MCS7) { 1553 u8 ht_rates1t[] = {DESC92C_RATEMCS0, DESC92C_RATEMCS1, 1554 DESC92C_RATEMCS2, DESC92C_RATEMCS3, 1555 DESC92C_RATEMCS4, DESC92C_RATEMCS5, 1556 DESC92C_RATEMCS6, DESC92C_RATEMCS7}; 1557 phy_set_txpower_index_by_rate_array(hw, rfpath, 1558 rtlphy->current_chan_bw, 1559 channel, ht_rates1t, 8); 1560 } else if (section == HT_MCS8_MCS15) { 1561 u8 ht_rates2t[] = {DESC92C_RATEMCS8, DESC92C_RATEMCS9, 1562 DESC92C_RATEMCS10, DESC92C_RATEMCS11, 1563 DESC92C_RATEMCS12, DESC92C_RATEMCS13, 1564 DESC92C_RATEMCS14, DESC92C_RATEMCS15}; 1565 phy_set_txpower_index_by_rate_array(hw, rfpath, 1566 rtlphy->current_chan_bw, 1567 channel, ht_rates2t, 8); 1568 } else 1569 rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, 1570 "Invalid RateSection %d\n", section); 1571} 1572 1573void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 1574{ 1575 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1576 struct rtl_phy *rtlphy = &rtl_priv(hw)->phy; 1577 enum radio_path rfpath; 1578 1579 if (!rtlefuse->txpwr_fromeprom) 1580 return; 1581 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 1582 rfpath++) { 1583 phy_set_txpower_index_by_rate_section(hw, rfpath, 1584 channel, CCK); 1585 phy_set_txpower_index_by_rate_section(hw, rfpath, 1586 channel, OFDM); 1587 phy_set_txpower_index_by_rate_section(hw, rfpath, 1588 channel, 1589 HT_MCS0_MCS7); 1590 1591 if (rtlphy->num_total_rfpath >= 2) 1592 phy_set_txpower_index_by_rate_section(hw, 1593 rfpath, channel, 1594 HT_MCS8_MCS15); 1595 } 1596} 1597 1598static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, 1599 enum wireless_mode wirelessmode, 1600 u8 txpwridx) 1601{ 1602 long offset; 1603 long pwrout_dbm; 1604 1605 switch (wirelessmode) { 1606 case WIRELESS_MODE_B: 1607 offset = -7; 1608 break; 1609 case WIRELESS_MODE_G: 1610 case WIRELESS_MODE_N_24G: 1611 offset = -8; 1612 break; 1613 default: 1614 offset = -8; 1615 break; 1616 } 1617 pwrout_dbm = txpwridx / 2 + offset; 1618 return pwrout_dbm; 1619} 1620 1621void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation) 1622{ 1623 struct rtl_priv *rtlpriv = rtl_priv(hw); 1624 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1625 enum io_type iotype; 1626 1627 if (!is_hal_stop(rtlhal)) { 1628 switch (operation) { 1629 case SCAN_OPT_BACKUP_BAND0: 1630 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN; 1631 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, 1632 (u8 *)&iotype); 1633 1634 break; 1635 case SCAN_OPT_RESTORE: 1636 iotype = IO_CMD_RESUME_DM_BY_SCAN; 1637 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD, 1638 (u8 *)&iotype); 1639 break; 1640 default: 1641 pr_err("Unknown Scan Backup operation.\n"); 1642 break; 1643 } 1644 } 1645} 1646 1647void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 1648{ 1649 struct rtl_priv *rtlpriv = rtl_priv(hw); 1650 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1651 struct rtl_phy *rtlphy = &rtlpriv->phy; 1652 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1653 u8 reg_bw_opmode; 1654 u8 reg_prsr_rsc; 1655 1656 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 1657 "Switch to %s bandwidth\n", 1658 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 1659 "20MHz" : "40MHz"); 1660 1661 if (is_hal_stop(rtlhal)) { 1662 rtlphy->set_bwmode_inprogress = false; 1663 return; 1664 } 1665 1666 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 1667 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 1668 1669 switch (rtlphy->current_chan_bw) { 1670 case HT_CHANNEL_WIDTH_20: 1671 reg_bw_opmode |= BW_OPMODE_20MHZ; 1672 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1673 break; 1674 case HT_CHANNEL_WIDTH_20_40: 1675 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 1676 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 1677 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | 1678 (mac->cur_40_prime_sc << 5); 1679 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 1680 break; 1681 default: 1682 pr_err("unknown bandwidth: %#X\n", 1683 rtlphy->current_chan_bw); 1684 break; 1685 } 1686 1687 switch (rtlphy->current_chan_bw) { 1688 case HT_CHANNEL_WIDTH_20: 1689 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1690 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1691 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT, 1692 (BIT(31) | BIT(30)), 0); 1693 break; 1694 case HT_CHANNEL_WIDTH_20_40: 1695 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1696 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1697 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 1698 (mac->cur_40_prime_sc >> 1)); 1699 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, 1700 mac->cur_40_prime_sc); 1701 1702 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1703 (mac->cur_40_prime_sc == 1704 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1705 break; 1706 default: 1707 pr_err("unknown bandwidth: %#X\n", 1708 rtlphy->current_chan_bw); 1709 break; 1710 } 1711 rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1712 rtlphy->set_bwmode_inprogress = false; 1713 rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n"); 1714} 1715 1716void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw, 1717 enum nl80211_channel_type ch_type) 1718{ 1719 struct rtl_priv *rtlpriv = rtl_priv(hw); 1720 struct rtl_phy *rtlphy = &rtlpriv->phy; 1721 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1722 u8 tmp_bw = rtlphy->current_chan_bw; 1723 1724 if (rtlphy->set_bwmode_inprogress) 1725 return; 1726 rtlphy->set_bwmode_inprogress = true; 1727 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1728 rtl92ee_phy_set_bw_mode_callback(hw); 1729 } else { 1730 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1731 "false driver sleep or unload\n"); 1732 rtlphy->set_bwmode_inprogress = false; 1733 rtlphy->current_chan_bw = tmp_bw; 1734 } 1735} 1736 1737void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw) 1738{ 1739 struct rtl_priv *rtlpriv = rtl_priv(hw); 1740 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1741 struct rtl_phy *rtlphy = &rtlpriv->phy; 1742 u32 delay; 1743 1744 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, 1745 "switch to channel%d\n", rtlphy->current_channel); 1746 if (is_hal_stop(rtlhal)) 1747 return; 1748 do { 1749 if (!rtlphy->sw_chnl_inprogress) 1750 break; 1751 if (!_rtl92ee_phy_sw_chnl_step_by_step 1752 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, 1753 &rtlphy->sw_chnl_step, &delay)) { 1754 if (delay > 0) 1755 mdelay(delay); 1756 else 1757 continue; 1758 } else { 1759 rtlphy->sw_chnl_inprogress = false; 1760 } 1761 break; 1762 } while (true); 1763 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n"); 1764} 1765 1766u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw) 1767{ 1768 struct rtl_priv *rtlpriv = rtl_priv(hw); 1769 struct rtl_phy *rtlphy = &rtlpriv->phy; 1770 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1771 1772 if (rtlphy->sw_chnl_inprogress) 1773 return 0; 1774 if (rtlphy->set_bwmode_inprogress) 1775 return 0; 1776 WARN_ONCE((rtlphy->current_channel > 14), 1777 "rtl8192ee: WIRELESS_MODE_G but channel>14"); 1778 rtlphy->sw_chnl_inprogress = true; 1779 rtlphy->sw_chnl_stage = 0; 1780 rtlphy->sw_chnl_step = 0; 1781 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) { 1782 rtl92ee_phy_sw_chnl_callback(hw); 1783 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 1784 "sw_chnl_inprogress false schedule workitem current channel %d\n", 1785 rtlphy->current_channel); 1786 rtlphy->sw_chnl_inprogress = false; 1787 } else { 1788 rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, 1789 "sw_chnl_inprogress false driver sleep or unload\n"); 1790 rtlphy->sw_chnl_inprogress = false; 1791 } 1792 return 1; 1793} 1794 1795static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 1796 u8 channel, u8 *stage, u8 *step, 1797 u32 *delay) 1798{ 1799 struct rtl_priv *rtlpriv = rtl_priv(hw); 1800 struct rtl_phy *rtlphy = &rtlpriv->phy; 1801 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 1802 u32 precommoncmdcnt; 1803 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 1804 u32 postcommoncmdcnt; 1805 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 1806 u32 rfdependcmdcnt; 1807 struct swchnlcmd *currentcmd = NULL; 1808 u8 rfpath; 1809 u8 num_total_rfpath = rtlphy->num_total_rfpath; 1810 1811 precommoncmdcnt = 0; 1812 _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1813 MAX_PRECMD_CNT, 1814 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 1815 _rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 1816 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 1817 1818 postcommoncmdcnt = 0; 1819 1820 _rtl92ee_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 1821 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 1822 1823 rfdependcmdcnt = 0; 1824 1825 WARN_ONCE((channel < 1 || channel > 14), 1826 "rtl8192ee: illegal channel for Zebra: %d\n", channel); 1827 1828 _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1829 MAX_RFDEPENDCMD_CNT, 1830 CMDID_RF_WRITEREG, 1831 RF_CHNLBW, channel, 10); 1832 1833 _rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 1834 MAX_RFDEPENDCMD_CNT, CMDID_END, 1835 0, 0, 0); 1836 1837 do { 1838 switch (*stage) { 1839 case 0: 1840 currentcmd = &precommoncmd[*step]; 1841 break; 1842 case 1: 1843 currentcmd = &rfdependcmd[*step]; 1844 break; 1845 case 2: 1846 currentcmd = &postcommoncmd[*step]; 1847 break; 1848 default: 1849 pr_err("Invalid 'stage' = %d, Check it!\n", 1850 *stage); 1851 return true; 1852 } 1853 1854 if (currentcmd->cmdid == CMDID_END) { 1855 if ((*stage) == 2) 1856 return true; 1857 (*stage)++; 1858 (*step) = 0; 1859 continue; 1860 } 1861 1862 switch (currentcmd->cmdid) { 1863 case CMDID_SET_TXPOWEROWER_LEVEL: 1864 rtl92ee_phy_set_txpower_level(hw, channel); 1865 break; 1866 case CMDID_WRITEPORT_ULONG: 1867 rtl_write_dword(rtlpriv, currentcmd->para1, 1868 currentcmd->para2); 1869 break; 1870 case CMDID_WRITEPORT_USHORT: 1871 rtl_write_word(rtlpriv, currentcmd->para1, 1872 (u16)currentcmd->para2); 1873 break; 1874 case CMDID_WRITEPORT_UCHAR: 1875 rtl_write_byte(rtlpriv, currentcmd->para1, 1876 (u8)currentcmd->para2); 1877 break; 1878 case CMDID_RF_WRITEREG: 1879 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 1880 rtlphy->rfreg_chnlval[rfpath] = 1881 ((rtlphy->rfreg_chnlval[rfpath] & 1882 0xfffff00) | currentcmd->para2); 1883 1884 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1885 currentcmd->para1, 1886 0x3ff, 1887 rtlphy->rfreg_chnlval[rfpath]); 1888 } 1889 break; 1890 default: 1891 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1892 "switch case %#x not processed\n", 1893 currentcmd->cmdid); 1894 break; 1895 } 1896 1897 break; 1898 } while (true); 1899 1900 (*delay) = currentcmd->msdelay; 1901 (*step)++; 1902 return false; 1903} 1904 1905static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 1906 u32 cmdtableidx, u32 cmdtablesz, 1907 enum swchnlcmd_id cmdid, 1908 u32 para1, u32 para2, u32 msdelay) 1909{ 1910 struct swchnlcmd *pcmd; 1911 1912 if (cmdtable == NULL) { 1913 WARN_ONCE(true, "rtl8192ee: cmdtable cannot be NULL.\n"); 1914 return false; 1915 } 1916 1917 if (cmdtableidx >= cmdtablesz) 1918 return false; 1919 1920 pcmd = cmdtable + cmdtableidx; 1921 pcmd->cmdid = cmdid; 1922 pcmd->para1 = para1; 1923 pcmd->para2 = para2; 1924 pcmd->msdelay = msdelay; 1925 return true; 1926} 1927 1928static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 1929{ 1930 u32 reg_eac, reg_e94, reg_e9c; 1931 u8 result = 0x00; 1932 /* path-A IQK setting */ 1933 /* PA/PAD controlled by 0x0 */ 1934 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1935 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); 1936 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1937 1938 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); 1939 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 1940 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 1941 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 1942 1943 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); 1944 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); 1945 1946 /*LO calibration setting*/ 1947 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); 1948 1949 /*One shot, path A LOK & IQK*/ 1950 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); 1951 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1952 1953 mdelay(IQK_DELAY_TIME); 1954 1955 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1956 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1957 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1958 1959 if (!(reg_eac & BIT(28)) && 1960 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 1961 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) 1962 result |= 0x01; 1963 else 1964 return result; 1965 1966 return result; 1967} 1968 1969static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw) 1970{ 1971 u32 reg_eac, reg_eb4, reg_ebc; 1972 u8 result = 0x00; 1973 1974 /* PA/PAD controlled by 0x0 */ 1975 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 1976 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); 1977 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 1978 1979 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); 1980 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1981 1982 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 1983 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 1984 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); 1985 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 1986 1987 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); 1988 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); 1989 1990 /* LO calibration setting */ 1991 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); 1992 1993 /*One shot, path B LOK & IQK*/ 1994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); 1995 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 1996 1997 mdelay(IQK_DELAY_TIME); 1998 1999 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 2000 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 2001 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 2002 2003 if (!(reg_eac & BIT(31)) && 2004 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && 2005 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) 2006 result |= 0x01; 2007 else 2008 return result; 2009 2010 return result; 2011} 2012 2013static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) 2014{ 2015 u32 reg_eac, reg_e94, reg_e9c, reg_ea4 , u32temp; 2016 u8 result = 0x00; 2017 2018 /*Get TXIMR Setting*/ 2019 /*Modify RX IQK mode table*/ 2020 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2021 2022 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 2023 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 2024 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 2025 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); 2026 2027 /*PA/PAD control by 0x56, and set = 0x0*/ 2028 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); 2029 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); 2030 2031 /*enter IQK mode*/ 2032 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 2033 2034 /*IQK Setting*/ 2035 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 2036 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 2037 2038 /*path a IQK setting*/ 2039 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); 2040 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 2041 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 2042 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 2043 2044 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); 2045 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); 2046 2047 /*LO calibration Setting*/ 2048 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 2049 2050 /*one shot,path A LOK & iqk*/ 2051 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); 2052 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 2053 2054 mdelay(IQK_DELAY_TIME); 2055 2056 /* Check failed */ 2057 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 2058 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); 2059 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); 2060 2061 if (!(reg_eac & BIT(28)) && 2062 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && 2063 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) { 2064 result |= 0x01; 2065 } else { 2066 /* PA/PAD controlled by 0x0 */ 2067 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2068 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); 2069 return result; 2070 } 2071 2072 u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000) | 2073 ((reg_e9c & 0x3FF0000) >> 16); 2074 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); 2075 /*RX IQK*/ 2076 /*Modify RX IQK mode table*/ 2077 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2078 2079 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 2080 2081 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 2082 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 2083 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); 2084 2085 /*PA/PAD control by 0x56, and set = 0x0*/ 2086 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); 2087 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); 2088 2089 /*enter IQK mode*/ 2090 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 2091 2092 /*IQK Setting*/ 2093 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 2094 2095 /*path a IQK setting*/ 2096 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 2097 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); 2098 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 2099 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 2100 2101 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); 2102 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); 2103 2104 /*LO calibration Setting*/ 2105 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); 2106 /*one shot,path A LOK & iqk*/ 2107 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); 2108 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 2109 2110 mdelay(IQK_DELAY_TIME); 2111 /*Check failed*/ 2112 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 2113 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); 2114 2115 /*PA/PAD controlled by 0x0*/ 2116 /*leave IQK mode*/ 2117 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2118 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); 2119 /*if Tx is OK, check whether Rx is OK*/ 2120 if (!(reg_eac & BIT(27)) && 2121 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && 2122 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) 2123 result |= 0x02; 2124 2125 return result; 2126} 2127 2128static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb) 2129{ 2130 struct rtl_priv *rtlpriv = rtl_priv(hw); 2131 u32 reg_eac, reg_eb4, reg_ebc, reg_ecc, reg_ec4, u32temp; 2132 u8 result = 0x00; 2133 2134 /*Get TXIMR Setting*/ 2135 /*Modify RX IQK mode table*/ 2136 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2137 2138 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 2139 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 2140 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 2141 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); 2142 2143 /*PA/PAD all off*/ 2144 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); 2145 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); 2146 2147 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 2148 2149 /*IQK Setting*/ 2150 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 2151 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 2152 2153 /*path a IQK setting*/ 2154 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 2155 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 2156 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); 2157 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 2158 2159 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); 2160 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); 2161 2162 /*LO calibration Setting*/ 2163 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); 2164 2165 /*one shot,path A LOK & iqk*/ 2166 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); 2167 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 2168 2169 mdelay(IQK_DELAY_TIME); 2170 2171 /* Check failed */ 2172 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 2173 reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); 2174 reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); 2175 2176 if (!(reg_eac & BIT(31)) && 2177 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && 2178 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) { 2179 result |= 0x01; 2180 } else { 2181 /* PA/PAD controlled by 0x0 */ 2182 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2183 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); 2184 return result; 2185 } 2186 2187 u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) | 2188 ((reg_ebc & 0x3FF0000) >> 16); 2189 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); 2190 /*RX IQK*/ 2191 /*Modify RX IQK mode table*/ 2192 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2193 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); 2194 2195 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); 2196 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); 2197 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); 2198 2199 /*PA/PAD all off*/ 2200 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); 2201 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); 2202 2203 /*enter IQK mode*/ 2204 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 2205 2206 /*IQK Setting*/ 2207 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 2208 2209 /*path b IQK setting*/ 2210 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 2211 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); 2212 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); 2213 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); 2214 2215 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); 2216 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); 2217 2218 /*LO calibration Setting*/ 2219 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); 2220 /*one shot,path A LOK & iqk*/ 2221 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); 2222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); 2223 2224 mdelay(IQK_DELAY_TIME); 2225 /*Check failed*/ 2226 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); 2227 reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); 2228 reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); 2229 /*PA/PAD controlled by 0x0*/ 2230 /*leave IQK mode*/ 2231 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); 2232 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); 2233 /*if Tx is OK, check whether Rx is OK*/ 2234 if (!(reg_eac & BIT(30)) && 2235 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && 2236 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) 2237 result |= 0x02; 2238 else 2239 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "Path B Rx IQK fail!!\n"); 2240 2241 return result; 2242} 2243 2244static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, 2245 bool b_iqk_ok, long result[][8], 2246 u8 final_candidate, 2247 bool btxonly) 2248{ 2249 u32 oldval_0, x, tx0_a, reg; 2250 long y, tx0_c; 2251 2252 if (final_candidate == 0xFF) { 2253 return; 2254 } else if (b_iqk_ok) { 2255 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 2256 MASKDWORD) >> 22) & 0x3FF; 2257 x = result[final_candidate][0]; 2258 if ((x & 0x00000200) != 0) 2259 x = x | 0xFFFFFC00; 2260 tx0_a = (x * oldval_0) >> 8; 2261 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); 2262 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), 2263 ((x * oldval_0 >> 7) & 0x1)); 2264 y = result[final_candidate][1]; 2265 if ((y & 0x00000200) != 0) 2266 y = y | 0xFFFFFC00; 2267 tx0_c = (y * oldval_0) >> 8; 2268 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 2269 ((tx0_c & 0x3C0) >> 6)); 2270 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, 2271 (tx0_c & 0x3F)); 2272 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), 2273 ((y * oldval_0 >> 7) & 0x1)); 2274 2275 if (btxonly) 2276 return; 2277 2278 reg = result[final_candidate][2]; 2279 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 2280 2281 reg = result[final_candidate][3] & 0x3F; 2282 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 2283 2284 reg = (result[final_candidate][3] >> 6) & 0xF; 2285 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); 2286 } 2287} 2288 2289static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw, 2290 bool b_iqk_ok, long result[][8], 2291 u8 final_candidate, 2292 bool btxonly) 2293{ 2294 u32 oldval_1, x, tx1_a, reg; 2295 long y, tx1_c; 2296 2297 if (final_candidate == 0xFF) { 2298 return; 2299 } else if (b_iqk_ok) { 2300 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 2301 MASKDWORD) >> 22) & 0x3FF; 2302 x = result[final_candidate][4]; 2303 if ((x & 0x00000200) != 0) 2304 x = x | 0xFFFFFC00; 2305 tx1_a = (x * oldval_1) >> 8; 2306 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); 2307 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), 2308 ((x * oldval_1 >> 7) & 0x1)); 2309 y = result[final_candidate][5]; 2310 if ((y & 0x00000200) != 0) 2311 y = y | 0xFFFFFC00; 2312 tx1_c = (y * oldval_1) >> 8; 2313 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 2314 ((tx1_c & 0x3C0) >> 6)); 2315 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, 2316 (tx1_c & 0x3F)); 2317 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), 2318 ((y * oldval_1 >> 7) & 0x1)); 2319 2320 if (btxonly) 2321 return; 2322 2323 reg = result[final_candidate][6]; 2324 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 2325 2326 reg = result[final_candidate][7] & 0x3F; 2327 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 2328 2329 reg = (result[final_candidate][7] >> 6) & 0xF; 2330 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); 2331 } 2332} 2333 2334static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw, 2335 u32 *addareg, u32 *addabackup, 2336 u32 registernum) 2337{ 2338 u32 i; 2339 2340 for (i = 0; i < registernum; i++) 2341 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD); 2342} 2343 2344static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw, 2345 u32 *macreg, u32 *macbackup) 2346{ 2347 struct rtl_priv *rtlpriv = rtl_priv(hw); 2348 u32 i; 2349 2350 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 2351 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 2352 2353 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 2354} 2355 2356static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw, 2357 u32 *addareg, u32 *addabackup, 2358 u32 regiesternum) 2359{ 2360 u32 i; 2361 2362 for (i = 0; i < regiesternum; i++) 2363 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); 2364} 2365 2366static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw, 2367 u32 *macreg, u32 *macbackup) 2368{ 2369 struct rtl_priv *rtlpriv = rtl_priv(hw); 2370 u32 i; 2371 2372 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 2373 rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]); 2374 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); 2375} 2376 2377static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg, 2378 bool is_patha_on, bool is2t) 2379{ 2380 u32 i; 2381 2382 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 2383 rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616); 2384} 2385 2386static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw, 2387 u32 *macreg, u32 *macbackup) 2388{ 2389 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); 2390} 2391 2392static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw) 2393{ 2394 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 2395 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); 2396 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 2397} 2398 2399static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw, 2400 long result[][8], u8 c1, u8 c2) 2401{ 2402 u32 i, j, diff, simularity_bitmap, bound; 2403 2404 u8 final_candidate[2] = { 0xFF, 0xFF }; 2405 bool bresult = true/*, is2t = true*/; 2406 s32 tmp1, tmp2; 2407 2408 bound = 8; 2409 2410 simularity_bitmap = 0; 2411 2412 for (i = 0; i < bound; i++) { 2413 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { 2414 if ((result[c1][i] & 0x00000200) != 0) 2415 tmp1 = result[c1][i] | 0xFFFFFC00; 2416 else 2417 tmp1 = result[c1][i]; 2418 2419 if ((result[c2][i] & 0x00000200) != 0) 2420 tmp2 = result[c2][i] | 0xFFFFFC00; 2421 else 2422 tmp2 = result[c2][i]; 2423 } else { 2424 tmp1 = result[c1][i]; 2425 tmp2 = result[c2][i]; 2426 } 2427 2428 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 2429 2430 if (diff > MAX_TOLERANCE) { 2431 if ((i == 2 || i == 6) && !simularity_bitmap) { 2432 if (result[c1][i] + result[c1][i + 1] == 0) 2433 final_candidate[(i / 4)] = c2; 2434 else if (result[c2][i] + result[c2][i + 1] == 0) 2435 final_candidate[(i / 4)] = c1; 2436 else 2437 simularity_bitmap |= (1 << i); 2438 } else { 2439 simularity_bitmap |= (1 << i); 2440 } 2441 } 2442 } 2443 2444 if (simularity_bitmap == 0) { 2445 for (i = 0; i < (bound / 4); i++) { 2446 if (final_candidate[i] != 0xFF) { 2447 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2448 result[3][j] = 2449 result[final_candidate[i]][j]; 2450 bresult = false; 2451 } 2452 } 2453 return bresult; 2454 } 2455 if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/ 2456 for (i = 0; i < 2; i++) 2457 result[3][i] = result[c1][i]; 2458 } 2459 if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/ 2460 for (i = 2; i < 4; i++) 2461 result[3][i] = result[c1][i]; 2462 } 2463 if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/ 2464 for (i = 4; i < 6; i++) 2465 result[3][i] = result[c1][i]; 2466 } 2467 if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/ 2468 for (i = 6; i < 8; i++) 2469 result[3][i] = result[c1][i]; 2470 } 2471 return false; 2472} 2473 2474static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, 2475 long result[][8], u8 t, bool is2t) 2476{ 2477 struct rtl_priv *rtlpriv = rtl_priv(hw); 2478 struct rtl_phy *rtlphy = &rtlpriv->phy; 2479 u32 i; 2480 u8 patha_ok, pathb_ok; 2481 u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0); 2482 u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0); 2483 u32 adda_reg[IQK_ADDA_REG_NUM] = { 2484 0x85c, 0xe6c, 0xe70, 0xe74, 2485 0xe78, 0xe7c, 0xe80, 0xe84, 2486 0xe88, 0xe8c, 0xed0, 0xed4, 2487 0xed8, 0xedc, 0xee0, 0xeec 2488 }; 2489 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 2490 0x522, 0x550, 0x551, 0x040 2491 }; 2492 u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 2493 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, 2494 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, 2495 0x870, 0x860, 2496 0x864, 0x800 2497 }; 2498 const u32 retrycount = 2; 2499 2500 if (t == 0) { 2501 _rtl92ee_phy_save_adda_registers(hw, adda_reg, 2502 rtlphy->adda_backup, 2503 IQK_ADDA_REG_NUM); 2504 _rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg, 2505 rtlphy->iqk_mac_backup); 2506 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg, 2507 rtlphy->iqk_bb_backup, 2508 IQK_BB_REG_NUM); 2509 } 2510 2511 _rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t); 2512 2513 /*BB setting*/ 2514 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 2515 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 2516 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 2517 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); 2518 2519 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); 2520 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); 2521 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); 2522 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); 2523 2524 _rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg, 2525 rtlphy->iqk_mac_backup); 2526 /* Page B init*/ 2527 /* IQ calibration setting*/ 2528 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 2529 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 2530 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 2531 2532 for (i = 0 ; i < retrycount ; i++) { 2533 patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t); 2534 2535 if (patha_ok == 0x01) { 2536 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2537 "Path A Tx IQK Success!!\n"); 2538 result[t][0] = (rtl_get_bbreg(hw, 2539 RTX_POWER_BEFORE_IQK_A, 2540 MASKDWORD) & 0x3FF0000) 2541 >> 16; 2542 result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, 2543 MASKDWORD) & 0x3FF0000) 2544 >> 16; 2545 break; 2546 } 2547 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2548 "Path A Tx IQK Fail!!, ret = 0x%x\n", 2549 patha_ok); 2550 } 2551 2552 for (i = 0 ; i < retrycount ; i++) { 2553 patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t); 2554 2555 if (patha_ok == 0x03) { 2556 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2557 "Path A Rx IQK Success!!\n"); 2558 result[t][2] = (rtl_get_bbreg(hw, 2559 RRX_POWER_BEFORE_IQK_A_2, 2560 MASKDWORD) & 0x3FF0000) 2561 >> 16; 2562 result[t][3] = (rtl_get_bbreg(hw, 2563 RRX_POWER_AFTER_IQK_A_2, 2564 MASKDWORD) & 0x3FF0000) 2565 >> 16; 2566 break; 2567 } 2568 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2569 "Path A Rx IQK Fail!!, ret = 0x%x\n", 2570 patha_ok); 2571 } 2572 2573 if (0x00 == patha_ok) 2574 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2575 "Path A IQK failed!!, ret = 0\n"); 2576 if (is2t) { 2577 _rtl92ee_phy_path_a_standby(hw); 2578 /* Turn Path B ADDA on */ 2579 _rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t); 2580 2581 /* IQ calibration setting */ 2582 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); 2583 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); 2584 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); 2585 2586 for (i = 0 ; i < retrycount ; i++) { 2587 pathb_ok = _rtl92ee_phy_path_b_iqk(hw); 2588 if (pathb_ok == 0x01) { 2589 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2590 "Path B Tx IQK Success!!\n"); 2591 result[t][4] = (rtl_get_bbreg(hw, 2592 RTX_POWER_BEFORE_IQK_B, 2593 MASKDWORD) & 0x3FF0000) 2594 >> 16; 2595 result[t][5] = (rtl_get_bbreg(hw, 2596 RTX_POWER_AFTER_IQK_B, 2597 MASKDWORD) & 0x3FF0000) 2598 >> 16; 2599 break; 2600 } 2601 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2602 "Path B Tx IQK Fail!!, ret = 0x%x\n", 2603 pathb_ok); 2604 } 2605 2606 for (i = 0 ; i < retrycount ; i++) { 2607 pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t); 2608 if (pathb_ok == 0x03) { 2609 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2610 "Path B Rx IQK Success!!\n"); 2611 result[t][6] = (rtl_get_bbreg(hw, 2612 RRX_POWER_BEFORE_IQK_B_2, 2613 MASKDWORD) & 0x3FF0000) 2614 >> 16; 2615 result[t][7] = (rtl_get_bbreg(hw, 2616 RRX_POWER_AFTER_IQK_B_2, 2617 MASKDWORD) & 0x3FF0000) 2618 >> 16; 2619 break; 2620 } 2621 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2622 "Path B Rx IQK Fail!!, ret = 0x%x\n", 2623 pathb_ok); 2624 } 2625 2626 if (0x00 == pathb_ok) 2627 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2628 "Path B IQK failed!!, ret = 0\n"); 2629 } 2630 /* Back to BB mode, load original value */ 2631 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, 2632 "IQK:Back to BB mode, load original value!\n"); 2633 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); 2634 2635 if (t != 0) { 2636 /* Reload ADDA power saving parameters */ 2637 _rtl92ee_phy_reload_adda_registers(hw, adda_reg, 2638 rtlphy->adda_backup, 2639 IQK_ADDA_REG_NUM); 2640 2641 /* Reload MAC parameters */ 2642 _rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg, 2643 rtlphy->iqk_mac_backup); 2644 2645 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg, 2646 rtlphy->iqk_bb_backup, 2647 IQK_BB_REG_NUM); 2648 2649 /* Restore RX initial gain */ 2650 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); 2651 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); 2652 if (is2t) { 2653 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); 2654 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); 2655 } 2656 2657 /* load 0xe30 IQC default value */ 2658 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); 2659 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); 2660 } 2661} 2662 2663static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2664{ 2665 u8 tmpreg; 2666 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 2667 struct rtl_priv *rtlpriv = rtl_priv(hw); 2668 2669 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 2670 2671 if ((tmpreg & 0x70) != 0) 2672 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 2673 else 2674 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2675 2676 if ((tmpreg & 0x70) != 0) { 2677 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); 2678 2679 if (is2t) 2680 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, 2681 MASK12BITS); 2682 2683 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, 2684 (rf_a_mode & 0x8FFFF) | 0x10000); 2685 2686 if (is2t) 2687 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 2688 (rf_b_mode & 0x8FFFF) | 0x10000); 2689 } 2690 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); 2691 2692 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); 2693 2694 mdelay(100); 2695 2696 if ((tmpreg & 0x70) != 0) { 2697 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 2698 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); 2699 2700 if (is2t) 2701 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 2702 rf_b_mode); 2703 } else { 2704 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2705 } 2706} 2707 2708static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, 2709 bool bmain, bool is2t) 2710{ 2711 struct rtl_priv *rtlpriv = rtl_priv(hw); 2712 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2713 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2714 2715 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n"); 2716 2717 if (is_hal_stop(rtlhal)) { 2718 u8 u1btmp; 2719 2720 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0); 2721 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7)); 2722 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); 2723 } 2724 if (is2t) { 2725 if (bmain) 2726 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 2727 BIT(5) | BIT(6), 0x1); 2728 else 2729 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 2730 BIT(5) | BIT(6), 0x2); 2731 } else { 2732 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); 2733 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); 2734 2735 /* We use the RF definition of MAIN and AUX, 2736 * left antenna and right antenna repectively. 2737 * Default output at AUX. 2738 */ 2739 if (bmain) { 2740 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 2741 BIT(14) | BIT(13) | BIT(12), 0); 2742 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 2743 BIT(5) | BIT(4) | BIT(3), 0); 2744 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 2745 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); 2746 } else { 2747 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 2748 BIT(14) | BIT(13) | BIT(12), 1); 2749 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 2750 BIT(5) | BIT(4) | BIT(3), 1); 2751 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) 2752 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); 2753 } 2754 } 2755} 2756 2757#undef IQK_ADDA_REG_NUM 2758#undef IQK_DELAY_TIME 2759 2760static u8 rtl92ee_get_rightchnlplace_for_iqk(u8 chnl) 2761{ 2762 u8 channel_all[59] = { 2763 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 2764 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 2765 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 2766 114, 116, 118, 120, 122, 124, 126, 128, 130, 2767 132, 134, 136, 138, 140, 149, 151, 153, 155, 2768 157, 159, 161, 163, 165 2769 }; 2770 u8 place = chnl; 2771 2772 if (chnl > 14) { 2773 for (place = 14; place < sizeof(channel_all); place++) { 2774 if (channel_all[place] == chnl) 2775 return place - 13; 2776 } 2777 } 2778 2779 return 0; 2780} 2781 2782void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery) 2783{ 2784 struct rtl_priv *rtlpriv = rtl_priv(hw); 2785 struct rtl_phy *rtlphy = &rtlpriv->phy; 2786 long result[4][8]; 2787 u8 i, final_candidate; 2788 bool b_patha_ok, b_pathb_ok; 2789 long reg_e94, reg_e9c, reg_ea4; 2790 long reg_eb4, reg_ebc, reg_ec4; 2791 bool is12simular, is13simular, is23simular; 2792 u8 idx; 2793 u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 2794 ROFDM0_XARXIQIMBALANCE, 2795 ROFDM0_XBRXIQIMBALANCE, 2796 ROFDM0_ECCATHRESHOLD, 2797 ROFDM0_AGCRSSITABLE, 2798 ROFDM0_XATXIQIMBALANCE, 2799 ROFDM0_XBTXIQIMBALANCE, 2800 ROFDM0_XCTXAFE, 2801 ROFDM0_XDTXAFE, 2802 ROFDM0_RXIQEXTANTA 2803 }; 2804 2805 if (b_recovery) { 2806 _rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg, 2807 rtlphy->iqk_bb_backup, 9); 2808 return; 2809 } 2810 2811 for (i = 0; i < 8; i++) { 2812 result[0][i] = 0; 2813 result[1][i] = 0; 2814 result[2][i] = 0; 2815 2816 if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) 2817 result[3][i] = 0x100; 2818 else 2819 result[3][i] = 0; 2820 } 2821 final_candidate = 0xff; 2822 b_patha_ok = false; 2823 b_pathb_ok = false; 2824 is12simular = false; 2825 is23simular = false; 2826 is13simular = false; 2827 for (i = 0; i < 3; i++) { 2828 _rtl92ee_phy_iq_calibrate(hw, result, i, true); 2829 if (i == 1) { 2830 is12simular = _rtl92ee_phy_simularity_compare(hw, 2831 result, 2832 0, 1); 2833 if (is12simular) { 2834 final_candidate = 0; 2835 break; 2836 } 2837 } 2838 2839 if (i == 2) { 2840 is13simular = _rtl92ee_phy_simularity_compare(hw, 2841 result, 2842 0, 2); 2843 if (is13simular) { 2844 final_candidate = 0; 2845 break; 2846 } 2847 is23simular = _rtl92ee_phy_simularity_compare(hw, 2848 result, 2849 1, 2); 2850 if (is23simular) 2851 final_candidate = 1; 2852 else 2853 final_candidate = 3; 2854 } 2855 } 2856 2857 reg_e94 = result[3][0]; 2858 reg_e9c = result[3][1]; 2859 reg_ea4 = result[3][2]; 2860 reg_eb4 = result[3][4]; 2861 reg_ebc = result[3][5]; 2862 reg_ec4 = result[3][6]; 2863 2864 if (final_candidate != 0xff) { 2865 reg_e94 = result[final_candidate][0]; 2866 rtlphy->reg_e94 = reg_e94; 2867 reg_e9c = result[final_candidate][1]; 2868 rtlphy->reg_e9c = reg_e9c; 2869 reg_ea4 = result[final_candidate][2]; 2870 reg_eb4 = result[final_candidate][4]; 2871 rtlphy->reg_eb4 = reg_eb4; 2872 reg_ebc = result[final_candidate][5]; 2873 rtlphy->reg_ebc = reg_ebc; 2874 reg_ec4 = result[final_candidate][6]; 2875 b_patha_ok = true; 2876 b_pathb_ok = true; 2877 } else { 2878 rtlphy->reg_e94 = 0x100; 2879 rtlphy->reg_eb4 = 0x100; 2880 rtlphy->reg_e9c = 0x0; 2881 rtlphy->reg_ebc = 0x0; 2882 } 2883 2884 if (reg_e94 != 0) 2885 _rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result, 2886 final_candidate, 2887 (reg_ea4 == 0)); 2888 2889 _rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result, 2890 final_candidate, 2891 (reg_ec4 == 0)); 2892 2893 idx = rtl92ee_get_rightchnlplace_for_iqk(rtlphy->current_channel); 2894 2895 /* To Fix BSOD when final_candidate is 0xff */ 2896 if (final_candidate < 4) { 2897 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2898 rtlphy->iqk_matrix[idx].value[0][i] = 2899 result[final_candidate][i]; 2900 2901 rtlphy->iqk_matrix[idx].iqk_done = true; 2902 } 2903 _rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg, 2904 rtlphy->iqk_bb_backup, 9); 2905} 2906 2907void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw) 2908{ 2909 struct rtl_priv *rtlpriv = rtl_priv(hw); 2910 struct rtl_phy *rtlphy = &rtlpriv->phy; 2911 struct rtl_hal *rtlhal = &rtlpriv->rtlhal; 2912 u32 timeout = 2000, timecount = 0; 2913 2914 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2915 udelay(50); 2916 timecount += 50; 2917 } 2918 2919 rtlphy->lck_inprogress = true; 2920 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2921 "LCK:Start!!! currentband %x delay %d ms\n", 2922 rtlhal->current_bandtype, timecount); 2923 2924 _rtl92ee_phy_lc_calibrate(hw, false); 2925 2926 rtlphy->lck_inprogress = false; 2927} 2928 2929void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) 2930{ 2931} 2932 2933void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain) 2934{ 2935 _rtl92ee_phy_set_rfpath_switch(hw, bmain, false); 2936} 2937 2938bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2939{ 2940 struct rtl_priv *rtlpriv = rtl_priv(hw); 2941 struct rtl_phy *rtlphy = &rtlpriv->phy; 2942 bool postprocessing = false; 2943 2944 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2945 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2946 iotype, rtlphy->set_io_inprogress); 2947 do { 2948 switch (iotype) { 2949 case IO_CMD_RESUME_DM_BY_SCAN: 2950 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2951 "[IO CMD] Resume DM after scan.\n"); 2952 postprocessing = true; 2953 break; 2954 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 2955 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2956 "[IO CMD] Pause DM before scan.\n"); 2957 postprocessing = true; 2958 break; 2959 default: 2960 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 2961 "switch case %#x not processed\n", iotype); 2962 break; 2963 } 2964 } while (false); 2965 if (postprocessing && !rtlphy->set_io_inprogress) { 2966 rtlphy->set_io_inprogress = true; 2967 rtlphy->current_io_type = iotype; 2968 } else { 2969 return false; 2970 } 2971 rtl92ee_phy_set_io(hw); 2972 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype); 2973 return true; 2974} 2975 2976static void rtl92ee_phy_set_io(struct ieee80211_hw *hw) 2977{ 2978 struct rtl_priv *rtlpriv = rtl_priv(hw); 2979 struct rtl_phy *rtlphy = &rtlpriv->phy; 2980 struct dig_t *dm_dig = &rtlpriv->dm_digtable; 2981 2982 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 2983 "--->Cmd(%#x), set_io_inprogress(%d)\n", 2984 rtlphy->current_io_type, rtlphy->set_io_inprogress); 2985 switch (rtlphy->current_io_type) { 2986 case IO_CMD_RESUME_DM_BY_SCAN: 2987 rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1); 2988 rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca); 2989 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "no set txpower\n"); 2990 rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel); 2991 break; 2992 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN: 2993 /* 8192eebt */ 2994 rtlphy->initgain_backup.xaagccore1 = dm_dig->cur_igvalue; 2995 rtl92ee_dm_write_dig(hw, 0x17); 2996 rtlphy->initgain_backup.cca = dm_dig->cur_cck_cca_thres; 2997 rtl92ee_dm_write_cck_cca_thres(hw, 0x40); 2998 break; 2999 default: 3000 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 3001 "switch case %#x not processed\n", 3002 rtlphy->current_io_type); 3003 break; 3004 } 3005 rtlphy->set_io_inprogress = false; 3006 rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, 3007 "(%#x)\n", rtlphy->current_io_type); 3008} 3009 3010static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw) 3011{ 3012 struct rtl_priv *rtlpriv = rtl_priv(hw); 3013 3014 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 3015 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3016 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ 3017 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3018 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3019 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3020} 3021 3022static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw) 3023{ 3024 struct rtl_priv *rtlpriv = rtl_priv(hw); 3025 3026 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 3027 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3028 3029 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3030 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 3031} 3032 3033static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, 3034 enum rf_pwrstate rfpwr_state) 3035{ 3036 struct rtl_priv *rtlpriv = rtl_priv(hw); 3037 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3038 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3039 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3040 bool bresult = true; 3041 u8 i, queue_id; 3042 struct rtl8192_tx_ring *ring = NULL; 3043 3044 switch (rfpwr_state) { 3045 case ERFON: 3046 if ((ppsc->rfpwr_state == ERFOFF) && 3047 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 3048 bool rtstatus; 3049 u32 initializecount = 0; 3050 3051 do { 3052 initializecount++; 3053 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 3054 "IPS Set eRf nic enable\n"); 3055 rtstatus = rtl_ps_enable_nic(hw); 3056 } while (!rtstatus && (initializecount < 10)); 3057 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3058 } else { 3059 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 3060 "Set ERFON sleeping:%d ms\n", 3061 jiffies_to_msecs(jiffies - 3062 ppsc->last_sleep_jiffies)); 3063 ppsc->last_awake_jiffies = jiffies; 3064 rtl92ee_phy_set_rf_on(hw); 3065 } 3066 if (mac->link_state == MAC80211_LINKED) 3067 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); 3068 else 3069 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); 3070 break; 3071 case ERFOFF: 3072 for (queue_id = 0, i = 0; 3073 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 3074 ring = &pcipriv->dev.tx_ring[queue_id]; 3075 if (queue_id == BEACON_QUEUE || 3076 skb_queue_len(&ring->queue) == 0) { 3077 queue_id++; 3078 continue; 3079 } else { 3080 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 3081 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 3082 (i + 1), queue_id, 3083 skb_queue_len(&ring->queue)); 3084 3085 udelay(10); 3086 i++; 3087 } 3088 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 3089 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 3090 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 3091 MAX_DOZE_WAITING_TIMES_9x, 3092 queue_id, 3093 skb_queue_len(&ring->queue)); 3094 break; 3095 } 3096 } 3097 3098 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 3099 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 3100 "IPS Set eRf nic disable\n"); 3101 rtl_ps_disable_nic(hw); 3102 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3103 } else { 3104 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 3105 rtlpriv->cfg->ops->led_control(hw, 3106 LED_CTL_NO_LINK); 3107 } else { 3108 rtlpriv->cfg->ops->led_control(hw, 3109 LED_CTL_POWER_OFF); 3110 } 3111 } 3112 break; 3113 case ERFSLEEP: 3114 if (ppsc->rfpwr_state == ERFOFF) 3115 break; 3116 for (queue_id = 0, i = 0; 3117 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 3118 ring = &pcipriv->dev.tx_ring[queue_id]; 3119 if (skb_queue_len(&ring->queue) == 0) { 3120 queue_id++; 3121 continue; 3122 } else { 3123 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 3124 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 3125 (i + 1), queue_id, 3126 skb_queue_len(&ring->queue)); 3127 udelay(10); 3128 i++; 3129 } 3130 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 3131 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 3132 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 3133 MAX_DOZE_WAITING_TIMES_9x, 3134 queue_id, 3135 skb_queue_len(&ring->queue)); 3136 break; 3137 } 3138 } 3139 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, 3140 "Set ERFSLEEP awaked:%d ms\n", 3141 jiffies_to_msecs(jiffies - 3142 ppsc->last_awake_jiffies)); 3143 ppsc->last_sleep_jiffies = jiffies; 3144 _rtl92ee_phy_set_rf_sleep(hw); 3145 break; 3146 default: 3147 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 3148 "switch case %#x not processed\n", rfpwr_state); 3149 bresult = false; 3150 break; 3151 } 3152 if (bresult) 3153 ppsc->rfpwr_state = rfpwr_state; 3154 return bresult; 3155} 3156 3157bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw, 3158 enum rf_pwrstate rfpwr_state) 3159{ 3160 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3161 3162 bool bresult = false; 3163 3164 if (rfpwr_state == ppsc->rfpwr_state) 3165 return bresult; 3166 bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state); 3167 return bresult; 3168} 3169