1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#include "wifi.h" 5#include "core.h" 6#include "pci.h" 7#include "base.h" 8#include "ps.h" 9#include "efuse.h" 10#include <linux/interrupt.h> 11#include <linux/export.h> 12#include <linux/module.h> 13 14MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 15MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 16MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); 17MODULE_LICENSE("GPL"); 18MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); 19 20static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 21 INTEL_VENDOR_ID, 22 ATI_VENDOR_ID, 23 AMD_VENDOR_ID, 24 SIS_VENDOR_ID 25}; 26 27static const u8 ac_to_hwq[] = { 28 VO_QUEUE, 29 VI_QUEUE, 30 BE_QUEUE, 31 BK_QUEUE 32}; 33 34static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb) 35{ 36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 37 __le16 fc = rtl_get_fc(skb); 38 u8 queue_index = skb_get_queue_mapping(skb); 39 struct ieee80211_hdr *hdr; 40 41 if (unlikely(ieee80211_is_beacon(fc))) 42 return BEACON_QUEUE; 43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 44 return MGNT_QUEUE; 45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 46 if (ieee80211_is_nullfunc(fc)) 47 return HIGH_QUEUE; 48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 49 hdr = rtl_get_hdr(skb); 50 51 if (is_multicast_ether_addr(hdr->addr1) || 52 is_broadcast_ether_addr(hdr->addr1)) 53 return HIGH_QUEUE; 54 } 55 56 return ac_to_hwq[queue_index]; 57} 58 59/* Update PCI dependent default settings*/ 60static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) 61{ 62 struct rtl_priv *rtlpriv = rtl_priv(hw); 63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 67 u16 init_aspm; 68 69 ppsc->reg_rfps_level = 0; 70 ppsc->support_aspm = false; 71 72 /*Update PCI ASPM setting */ 73 switch (rtlpci->const_pci_aspm) { 74 case 0: 75 /*No ASPM */ 76 break; 77 78 case 1: 79 /*ASPM dynamically enabled/disable. */ 80 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; 81 break; 82 83 case 2: 84 /*ASPM with Clock Req dynamically enabled/disable. */ 85 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | 86 RT_RF_OFF_LEVL_CLK_REQ); 87 break; 88 89 case 3: 90 /* Always enable ASPM and Clock Req 91 * from initialization to halt. 92 */ 93 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); 94 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | 95 RT_RF_OFF_LEVL_CLK_REQ); 96 break; 97 98 case 4: 99 /* Always enable ASPM without Clock Req 100 * from initialization to halt. 101 */ 102 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | 103 RT_RF_OFF_LEVL_CLK_REQ); 104 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; 105 break; 106 } 107 108 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 109 110 /*Update Radio OFF setting */ 111 switch (rtlpci->const_hwsw_rfoff_d3) { 112 case 1: 113 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 114 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 115 break; 116 117 case 2: 118 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) 119 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; 120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; 121 break; 122 123 case 3: 124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; 125 break; 126 } 127 128 /*Set HW definition to determine if it supports ASPM. */ 129 switch (rtlpci->const_support_pciaspm) { 130 case 0: 131 /*Not support ASPM. */ 132 ppsc->support_aspm = false; 133 break; 134 case 1: 135 /*Support ASPM. */ 136 ppsc->support_aspm = true; 137 ppsc->support_backdoor = true; 138 break; 139 case 2: 140 /*ASPM value set by chipset. */ 141 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) 142 ppsc->support_aspm = true; 143 break; 144 default: 145 pr_err("switch case %#x not processed\n", 146 rtlpci->const_support_pciaspm); 147 break; 148 } 149 150 /* toshiba aspm issue, toshiba will set aspm selfly 151 * so we should not set aspm in driver 152 */ 153 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &init_aspm); 154 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && 155 ((u8)init_aspm) == (PCI_EXP_LNKCTL_ASPM_L0S | 156 PCI_EXP_LNKCTL_ASPM_L1 | PCI_EXP_LNKCTL_CCC)) 157 ppsc->support_aspm = false; 158} 159 160static bool _rtl_pci_platform_switch_device_pci_aspm( 161 struct ieee80211_hw *hw, 162 u8 value) 163{ 164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 166 167 value &= PCI_EXP_LNKCTL_ASPMC; 168 169 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) 170 value |= PCI_EXP_LNKCTL_CCC; 171 172 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 173 PCI_EXP_LNKCTL_ASPMC | value, 174 value); 175 176 return false; 177} 178 179/* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */ 180static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value) 181{ 182 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 184 185 value &= PCI_EXP_LNKCTL_CLKREQ_EN; 186 187 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL, 188 PCI_EXP_LNKCTL_CLKREQ_EN, 189 value); 190 191 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) 192 udelay(100); 193} 194 195/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ 196static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) 197{ 198 struct rtl_priv *rtlpriv = rtl_priv(hw); 199 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 200 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 202 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 203 /*Retrieve original configuration settings. */ 204 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; 205 u16 aspmlevel = 0; 206 u16 tmp_u1b = 0; 207 208 if (!ppsc->support_aspm) 209 return; 210 211 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 212 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 213 "PCI(Bridge) UNKNOWN\n"); 214 215 return; 216 } 217 218 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 219 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 220 _rtl_pci_switch_clk_req(hw, 0x0); 221 } 222 223 /*for promising device will in L0 state after an I/O. */ 224 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &tmp_u1b); 225 226 /*Set corresponding value. */ 227 aspmlevel |= PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1; 228 linkctrl_reg &= ~aspmlevel; 229 230 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); 231} 232 233/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for 234 *power saving We should follow the sequence to enable 235 *RTL8192SE first then enable Pci Bridge ASPM 236 *or the system will show bluescreen. 237 */ 238static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) 239{ 240 struct rtl_priv *rtlpriv = rtl_priv(hw); 241 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 242 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 244 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 245 u16 aspmlevel; 246 u8 u_device_aspmsetting; 247 248 if (!ppsc->support_aspm) 249 return; 250 251 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { 252 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, 253 "PCI(Bridge) UNKNOWN\n"); 254 return; 255 } 256 257 /*Get ASPM level (with/without Clock Req) */ 258 aspmlevel = rtlpci->const_devicepci_aspm_setting; 259 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; 260 261 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ 262 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ 263 264 u_device_aspmsetting |= aspmlevel; 265 266 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); 267 268 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { 269 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & 270 RT_RF_OFF_LEVL_CLK_REQ) ? 271 PCI_EXP_LNKCTL_CLKREQ_EN : 0); 272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); 273 } 274 udelay(100); 275} 276 277static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) 278{ 279 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 280 281 bool status = false; 282 u8 offset_e0; 283 unsigned int offset_e4; 284 285 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); 286 287 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); 288 289 if (offset_e0 == 0xA0) { 290 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); 291 if (offset_e4 & BIT(23)) 292 status = true; 293 } 294 295 return status; 296} 297 298static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, 299 struct rtl_priv **buddy_priv) 300{ 301 struct rtl_priv *rtlpriv = rtl_priv(hw); 302 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 303 struct rtl_priv *tpriv = NULL, *iter; 304 struct rtl_pci_priv *tpcipriv = NULL; 305 306 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { 307 list_for_each_entry(iter, &rtlpriv->glb_var->glb_priv_list, 308 list) { 309 tpcipriv = (struct rtl_pci_priv *)iter->priv; 310 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 311 "pcipriv->ndis_adapter.funcnumber %x\n", 312 pcipriv->ndis_adapter.funcnumber); 313 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 314 "tpcipriv->ndis_adapter.funcnumber %x\n", 315 tpcipriv->ndis_adapter.funcnumber); 316 317 if (pcipriv->ndis_adapter.busnumber == 318 tpcipriv->ndis_adapter.busnumber && 319 pcipriv->ndis_adapter.devnumber == 320 tpcipriv->ndis_adapter.devnumber && 321 pcipriv->ndis_adapter.funcnumber != 322 tpcipriv->ndis_adapter.funcnumber) { 323 tpriv = iter; 324 break; 325 } 326 } 327 } 328 329 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 330 "find_buddy_priv %d\n", tpriv != NULL); 331 332 if (tpriv) 333 *buddy_priv = tpriv; 334 335 return tpriv != NULL; 336} 337 338static void rtl_pci_parse_configuration(struct pci_dev *pdev, 339 struct ieee80211_hw *hw) 340{ 341 struct rtl_priv *rtlpriv = rtl_priv(hw); 342 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 343 344 u8 tmp; 345 u16 linkctrl_reg; 346 347 /*Link Control Register */ 348 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); 349 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; 350 351 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", 352 pcipriv->ndis_adapter.linkctrl_reg); 353 354 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, 355 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS); 356 357 tmp = 0x17; 358 pci_write_config_byte(pdev, 0x70f, tmp); 359} 360 361static void rtl_pci_init_aspm(struct ieee80211_hw *hw) 362{ 363 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 364 365 _rtl_pci_update_default_setting(hw); 366 367 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { 368 /*Always enable ASPM & Clock Req. */ 369 rtl_pci_enable_aspm(hw); 370 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); 371 } 372} 373 374static void _rtl_pci_io_handler_init(struct device *dev, 375 struct ieee80211_hw *hw) 376{ 377 struct rtl_priv *rtlpriv = rtl_priv(hw); 378 379 rtlpriv->io.dev = dev; 380 381 rtlpriv->io.write8 = pci_write8_async; 382 rtlpriv->io.write16 = pci_write16_async; 383 rtlpriv->io.write32 = pci_write32_async; 384 385 rtlpriv->io.read8 = pci_read8_sync; 386 rtlpriv->io.read16 = pci_read16_sync; 387 rtlpriv->io.read32 = pci_read32_sync; 388} 389 390static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, 391 struct sk_buff *skb, 392 struct rtl_tcb_desc *tcb_desc, u8 tid) 393{ 394 struct rtl_priv *rtlpriv = rtl_priv(hw); 395 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 396 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 397 struct sk_buff *next_skb; 398 u8 additionlen = FCS_LEN; 399 400 /* here open is 4, wep/tkip is 8, aes is 12*/ 401 if (info->control.hw_key) 402 additionlen += info->control.hw_key->icv_len; 403 404 /* The most skb num is 6 */ 405 tcb_desc->empkt_num = 0; 406 spin_lock_bh(&rtlpriv->locks.waitq_lock); 407 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { 408 struct ieee80211_tx_info *next_info; 409 410 next_info = IEEE80211_SKB_CB(next_skb); 411 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { 412 tcb_desc->empkt_len[tcb_desc->empkt_num] = 413 next_skb->len + additionlen; 414 tcb_desc->empkt_num++; 415 } else { 416 break; 417 } 418 419 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], 420 next_skb)) 421 break; 422 423 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) 424 break; 425 } 426 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 427 428 return true; 429} 430 431/* just for early mode now */ 432static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) 433{ 434 struct rtl_priv *rtlpriv = rtl_priv(hw); 435 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 436 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 437 struct sk_buff *skb = NULL; 438 struct ieee80211_tx_info *info = NULL; 439 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 440 int tid; 441 442 if (!rtlpriv->rtlhal.earlymode_enable) 443 return; 444 445 /* we just use em for BE/BK/VI/VO */ 446 for (tid = 7; tid >= 0; tid--) { 447 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; 448 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 449 450 while (!mac->act_scanning && 451 rtlpriv->psc.rfpwr_state == ERFON) { 452 struct rtl_tcb_desc tcb_desc; 453 454 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 455 456 spin_lock(&rtlpriv->locks.waitq_lock); 457 if (!skb_queue_empty(&mac->skb_waitq[tid]) && 458 (ring->entries - skb_queue_len(&ring->queue) > 459 rtlhal->max_earlymode_num)) { 460 skb = skb_dequeue(&mac->skb_waitq[tid]); 461 } else { 462 spin_unlock(&rtlpriv->locks.waitq_lock); 463 break; 464 } 465 spin_unlock(&rtlpriv->locks.waitq_lock); 466 467 /* Some macaddr can't do early mode. like 468 * multicast/broadcast/no_qos data 469 */ 470 info = IEEE80211_SKB_CB(skb); 471 if (info->flags & IEEE80211_TX_CTL_AMPDU) 472 _rtl_update_earlymode_info(hw, skb, 473 &tcb_desc, tid); 474 475 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); 476 } 477 } 478} 479 480static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) 481{ 482 struct rtl_priv *rtlpriv = rtl_priv(hw); 483 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 484 485 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 486 487 while (skb_queue_len(&ring->queue)) { 488 struct sk_buff *skb; 489 struct ieee80211_tx_info *info; 490 __le16 fc; 491 u8 tid; 492 u8 *entry; 493 494 if (rtlpriv->use_new_trx_flow) 495 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 496 else 497 entry = (u8 *)(&ring->desc[ring->idx]); 498 499 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) 500 return; 501 ring->idx = (ring->idx + 1) % ring->entries; 502 503 skb = __skb_dequeue(&ring->queue); 504 dma_unmap_single(&rtlpci->pdev->dev, 505 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 506 true, HW_DESC_TXBUFF_ADDR), 507 skb->len, DMA_TO_DEVICE); 508 509 /* remove early mode header */ 510 if (rtlpriv->rtlhal.earlymode_enable) 511 skb_pull(skb, EM_HDR_LEN); 512 513 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 514 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", 515 ring->idx, 516 skb_queue_len(&ring->queue), 517 *(u16 *)(skb->data + 22)); 518 519 if (prio == TXCMD_QUEUE) { 520 dev_kfree_skb(skb); 521 goto tx_status_ok; 522 } 523 524 /* for sw LPS, just after NULL skb send out, we can 525 * sure AP knows we are sleeping, we should not let 526 * rf sleep 527 */ 528 fc = rtl_get_fc(skb); 529 if (ieee80211_is_nullfunc(fc)) { 530 if (ieee80211_has_pm(fc)) { 531 rtlpriv->mac80211.offchan_delay = true; 532 rtlpriv->psc.state_inap = true; 533 } else { 534 rtlpriv->psc.state_inap = false; 535 } 536 } 537 if (ieee80211_is_action(fc)) { 538 struct ieee80211_mgmt *action_frame = 539 (struct ieee80211_mgmt *)skb->data; 540 if (action_frame->u.action.u.ht_smps.action == 541 WLAN_HT_ACTION_SMPS) { 542 dev_kfree_skb(skb); 543 goto tx_status_ok; 544 } 545 } 546 547 /* update tid tx pkt num */ 548 tid = rtl_get_tid(skb); 549 if (tid <= 7) 550 rtlpriv->link_info.tidtx_inperiod[tid]++; 551 552 info = IEEE80211_SKB_CB(skb); 553 554 if (likely(!ieee80211_is_nullfunc(fc))) { 555 ieee80211_tx_info_clear_status(info); 556 info->flags |= IEEE80211_TX_STAT_ACK; 557 /*info->status.rates[0].count = 1; */ 558 ieee80211_tx_status_irqsafe(hw, skb); 559 } else { 560 rtl_tx_ackqueue(hw, skb); 561 } 562 563 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { 564 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, 565 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", 566 prio, ring->idx, 567 skb_queue_len(&ring->queue)); 568 569 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); 570 } 571tx_status_ok: 572 skb = NULL; 573 } 574 575 if (((rtlpriv->link_info.num_rx_inperiod + 576 rtlpriv->link_info.num_tx_inperiod) > 8) || 577 rtlpriv->link_info.num_rx_inperiod > 2) 578 rtl_lps_leave(hw, false); 579} 580 581static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, 582 struct sk_buff *new_skb, u8 *entry, 583 int rxring_idx, int desc_idx) 584{ 585 struct rtl_priv *rtlpriv = rtl_priv(hw); 586 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 587 u32 bufferaddress; 588 u8 tmp_one = 1; 589 struct sk_buff *skb; 590 591 if (likely(new_skb)) { 592 skb = new_skb; 593 goto remap; 594 } 595 skb = dev_alloc_skb(rtlpci->rxbuffersize); 596 if (!skb) 597 return 0; 598 599remap: 600 /* just set skb->cb to mapping addr for pci_unmap_single use */ 601 *((dma_addr_t *)skb->cb) = 602 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb), 603 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 604 bufferaddress = *((dma_addr_t *)skb->cb); 605 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress)) 606 return 0; 607 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; 608 if (rtlpriv->use_new_trx_flow) { 609 /* skb->cb may be 64 bit address */ 610 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 611 HW_DESC_RX_PREPARE, 612 (u8 *)(dma_addr_t *)skb->cb); 613 } else { 614 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 615 HW_DESC_RXBUFF_ADDR, 616 (u8 *)&bufferaddress); 617 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 618 HW_DESC_RXPKT_LEN, 619 (u8 *)&rtlpci->rxbuffersize); 620 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 621 HW_DESC_RXOWN, 622 (u8 *)&tmp_one); 623 } 624 return 1; 625} 626 627/* inorder to receive 8K AMSDU we have set skb to 628 * 9100bytes in init rx ring, but if this packet is 629 * not a AMSDU, this large packet will be sent to 630 * TCP/IP directly, this cause big packet ping fail 631 * like: "ping -s 65507", so here we will realloc skb 632 * based on the true size of packet, Mac80211 633 * Probably will do it better, but does not yet. 634 * 635 * Some platform will fail when alloc skb sometimes. 636 * in this condition, we will send the old skb to 637 * mac80211 directly, this will not cause any other 638 * issues, but only this packet will be lost by TCP/IP 639 */ 640static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, 641 struct sk_buff *skb, 642 struct ieee80211_rx_status rx_status) 643{ 644 if (unlikely(!rtl_action_proc(hw, skb, false))) { 645 dev_kfree_skb_any(skb); 646 } else { 647 struct sk_buff *uskb = NULL; 648 649 uskb = dev_alloc_skb(skb->len + 128); 650 if (likely(uskb)) { 651 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, 652 sizeof(rx_status)); 653 skb_put_data(uskb, skb->data, skb->len); 654 dev_kfree_skb_any(skb); 655 ieee80211_rx_irqsafe(hw, uskb); 656 } else { 657 ieee80211_rx_irqsafe(hw, skb); 658 } 659 } 660} 661 662/*hsisr interrupt handler*/ 663static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) 664{ 665 struct rtl_priv *rtlpriv = rtl_priv(hw); 666 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 667 668 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], 669 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | 670 rtlpci->sys_irq_mask); 671} 672 673static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 674{ 675 struct rtl_priv *rtlpriv = rtl_priv(hw); 676 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 677 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; 678 struct ieee80211_rx_status rx_status = { 0 }; 679 unsigned int count = rtlpci->rxringcount; 680 u8 own; 681 u8 tmp_one; 682 bool unicast = false; 683 u8 hw_queue = 0; 684 unsigned int rx_remained_cnt = 0; 685 struct rtl_stats stats = { 686 .signal = 0, 687 .rate = 0, 688 }; 689 690 /*RX NORMAL PKT */ 691 while (count--) { 692 struct ieee80211_hdr *hdr; 693 __le16 fc; 694 u16 len; 695 /*rx buffer descriptor */ 696 struct rtl_rx_buffer_desc *buffer_desc = NULL; 697 /*if use new trx flow, it means wifi info */ 698 struct rtl_rx_desc *pdesc = NULL; 699 /*rx pkt */ 700 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ 701 rtlpci->rx_ring[rxring_idx].idx]; 702 struct sk_buff *new_skb; 703 704 if (rtlpriv->use_new_trx_flow) { 705 if (rx_remained_cnt == 0) 706 rx_remained_cnt = 707 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, 708 hw_queue); 709 if (rx_remained_cnt == 0) 710 return; 711 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ 712 rtlpci->rx_ring[rxring_idx].idx]; 713 pdesc = (struct rtl_rx_desc *)skb->data; 714 } else { /* rx descriptor */ 715 pdesc = &rtlpci->rx_ring[rxring_idx].desc[ 716 rtlpci->rx_ring[rxring_idx].idx]; 717 718 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 719 false, 720 HW_DESC_OWN); 721 if (own) /* wait data to be filled by hardware */ 722 return; 723 } 724 725 /* Reaching this point means: data is filled already 726 * AAAAAAttention !!! 727 * We can NOT access 'skb' before 'pci_unmap_single' 728 */ 729 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 730 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 731 732 /* get a new skb - if fail, old one will be reused */ 733 new_skb = dev_alloc_skb(rtlpci->rxbuffersize); 734 if (unlikely(!new_skb)) 735 goto no_new; 736 memset(&rx_status, 0, sizeof(rx_status)); 737 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 738 &rx_status, (u8 *)pdesc, skb); 739 740 if (rtlpriv->use_new_trx_flow) 741 rtlpriv->cfg->ops->rx_check_dma_ok(hw, 742 (u8 *)buffer_desc, 743 hw_queue); 744 745 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false, 746 HW_DESC_RXPKT_LEN); 747 748 if (skb->end - skb->tail > len) { 749 skb_put(skb, len); 750 if (rtlpriv->use_new_trx_flow) 751 skb_reserve(skb, stats.rx_drvinfo_size + 752 stats.rx_bufshift + 24); 753 else 754 skb_reserve(skb, stats.rx_drvinfo_size + 755 stats.rx_bufshift); 756 } else { 757 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 758 "skb->end - skb->tail = %d, len is %d\n", 759 skb->end - skb->tail, len); 760 dev_kfree_skb_any(skb); 761 goto new_trx_end; 762 } 763 /* handle command packet here */ 764 if (stats.packet_report_type == C2H_PACKET) { 765 rtl_c2hcmd_enqueue(hw, skb); 766 goto new_trx_end; 767 } 768 769 /* NOTICE This can not be use for mac80211, 770 * this is done in mac80211 code, 771 * if done here sec DHCP will fail 772 * skb_trim(skb, skb->len - 4); 773 */ 774 775 hdr = rtl_get_hdr(skb); 776 fc = rtl_get_fc(skb); 777 778 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) { 779 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 780 sizeof(rx_status)); 781 782 if (is_broadcast_ether_addr(hdr->addr1)) { 783 ;/*TODO*/ 784 } else if (is_multicast_ether_addr(hdr->addr1)) { 785 ;/*TODO*/ 786 } else { 787 unicast = true; 788 rtlpriv->stats.rxbytesunicast += skb->len; 789 } 790 rtl_is_special_data(hw, skb, false, true); 791 792 if (ieee80211_is_data(fc)) { 793 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); 794 if (unicast) 795 rtlpriv->link_info.num_rx_inperiod++; 796 } 797 798 rtl_collect_scan_list(hw, skb); 799 800 /* static bcn for roaming */ 801 rtl_beacon_statistic(hw, skb); 802 rtl_p2p_info(hw, (void *)skb->data, skb->len); 803 /* for sw lps */ 804 rtl_swlps_beacon(hw, (void *)skb->data, skb->len); 805 rtl_recognize_peer(hw, (void *)skb->data, skb->len); 806 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP && 807 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G && 808 (ieee80211_is_beacon(fc) || 809 ieee80211_is_probe_resp(fc))) { 810 dev_kfree_skb_any(skb); 811 } else { 812 _rtl_pci_rx_to_mac80211(hw, skb, rx_status); 813 } 814 } else { 815 /* drop packets with errors or those too short */ 816 dev_kfree_skb_any(skb); 817 } 818new_trx_end: 819 if (rtlpriv->use_new_trx_flow) { 820 rtlpci->rx_ring[hw_queue].next_rx_rp += 1; 821 rtlpci->rx_ring[hw_queue].next_rx_rp %= 822 RTL_PCI_MAX_RX_COUNT; 823 824 rx_remained_cnt--; 825 rtl_write_word(rtlpriv, 0x3B4, 826 rtlpci->rx_ring[hw_queue].next_rx_rp); 827 } 828 if (((rtlpriv->link_info.num_rx_inperiod + 829 rtlpriv->link_info.num_tx_inperiod) > 8) || 830 rtlpriv->link_info.num_rx_inperiod > 2) 831 rtl_lps_leave(hw, false); 832 skb = new_skb; 833no_new: 834 if (rtlpriv->use_new_trx_flow) { 835 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, 836 rxring_idx, 837 rtlpci->rx_ring[rxring_idx].idx); 838 } else { 839 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, 840 rxring_idx, 841 rtlpci->rx_ring[rxring_idx].idx); 842 if (rtlpci->rx_ring[rxring_idx].idx == 843 rtlpci->rxringcount - 1) 844 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, 845 false, 846 HW_DESC_RXERO, 847 (u8 *)&tmp_one); 848 } 849 rtlpci->rx_ring[rxring_idx].idx = 850 (rtlpci->rx_ring[rxring_idx].idx + 1) % 851 rtlpci->rxringcount; 852 } 853} 854 855static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 856{ 857 struct ieee80211_hw *hw = dev_id; 858 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 859 struct rtl_priv *rtlpriv = rtl_priv(hw); 860 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 861 unsigned long flags; 862 struct rtl_int intvec = {0}; 863 864 irqreturn_t ret = IRQ_HANDLED; 865 866 if (rtlpci->irq_enabled == 0) 867 return ret; 868 869 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 870 rtlpriv->cfg->ops->disable_interrupt(hw); 871 872 /*read ISR: 4/8bytes */ 873 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec); 874 875 /*Shared IRQ or HW disappeared */ 876 if (!intvec.inta || intvec.inta == 0xffff) 877 goto done; 878 879 /*<1> beacon related */ 880 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) 881 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 882 "beacon ok interrupt!\n"); 883 884 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) 885 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 886 "beacon err interrupt!\n"); 887 888 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) 889 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); 890 891 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { 892 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 893 "prepare beacon for interrupt!\n"); 894 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); 895 } 896 897 /*<2> Tx related */ 898 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) 899 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); 900 901 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { 902 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 903 "Manage ok interrupt!\n"); 904 _rtl_pci_tx_isr(hw, MGNT_QUEUE); 905 } 906 907 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { 908 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 909 "HIGH_QUEUE ok interrupt!\n"); 910 _rtl_pci_tx_isr(hw, HIGH_QUEUE); 911 } 912 913 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { 914 rtlpriv->link_info.num_tx_inperiod++; 915 916 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 917 "BK Tx OK interrupt!\n"); 918 _rtl_pci_tx_isr(hw, BK_QUEUE); 919 } 920 921 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { 922 rtlpriv->link_info.num_tx_inperiod++; 923 924 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 925 "BE TX OK interrupt!\n"); 926 _rtl_pci_tx_isr(hw, BE_QUEUE); 927 } 928 929 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { 930 rtlpriv->link_info.num_tx_inperiod++; 931 932 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 933 "VI TX OK interrupt!\n"); 934 _rtl_pci_tx_isr(hw, VI_QUEUE); 935 } 936 937 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { 938 rtlpriv->link_info.num_tx_inperiod++; 939 940 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 941 "Vo TX OK interrupt!\n"); 942 _rtl_pci_tx_isr(hw, VO_QUEUE); 943 } 944 945 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) { 946 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { 947 rtlpriv->link_info.num_tx_inperiod++; 948 949 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 950 "H2C TX OK interrupt!\n"); 951 _rtl_pci_tx_isr(hw, H2C_QUEUE); 952 } 953 } 954 955 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { 956 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { 957 rtlpriv->link_info.num_tx_inperiod++; 958 959 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 960 "CMD TX OK interrupt!\n"); 961 _rtl_pci_tx_isr(hw, TXCMD_QUEUE); 962 } 963 } 964 965 /*<3> Rx related */ 966 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { 967 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); 968 _rtl_pci_rx_interrupt(hw); 969 } 970 971 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { 972 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 973 "rx descriptor unavailable!\n"); 974 _rtl_pci_rx_interrupt(hw); 975 } 976 977 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { 978 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); 979 _rtl_pci_rx_interrupt(hw); 980 } 981 982 /*<4> fw related*/ 983 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { 984 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { 985 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 986 "firmware interrupt!\n"); 987 queue_delayed_work(rtlpriv->works.rtl_wq, 988 &rtlpriv->works.fwevt_wq, 0); 989 } 990 } 991 992 /*<5> hsisr related*/ 993 /* Only 8188EE & 8723BE Supported. 994 * If Other ICs Come in, System will corrupt, 995 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] 996 * are not initialized 997 */ 998 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || 999 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { 1000 if (unlikely(intvec.inta & 1001 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { 1002 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, 1003 "hsisr interrupt!\n"); 1004 _rtl_pci_hs_interrupt(hw); 1005 } 1006 } 1007 1008 if (rtlpriv->rtlhal.earlymode_enable) 1009 tasklet_schedule(&rtlpriv->works.irq_tasklet); 1010 1011done: 1012 rtlpriv->cfg->ops->enable_interrupt(hw); 1013 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1014 return ret; 1015} 1016 1017static void _rtl_pci_irq_tasklet(struct tasklet_struct *t) 1018{ 1019 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet); 1020 struct ieee80211_hw *hw = rtlpriv->hw; 1021 _rtl_pci_tx_chk_waitq(hw); 1022} 1023 1024static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t) 1025{ 1026 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, 1027 works.irq_prepare_bcn_tasklet); 1028 struct ieee80211_hw *hw = rtlpriv->hw; 1029 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1030 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1031 struct rtl8192_tx_ring *ring = NULL; 1032 struct ieee80211_hdr *hdr = NULL; 1033 struct ieee80211_tx_info *info = NULL; 1034 struct sk_buff *pskb = NULL; 1035 struct rtl_tx_desc *pdesc = NULL; 1036 struct rtl_tcb_desc tcb_desc; 1037 /*This is for new trx flow*/ 1038 struct rtl_tx_buffer_desc *pbuffer_desc = NULL; 1039 u8 temp_one = 1; 1040 u8 *entry; 1041 1042 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 1043 ring = &rtlpci->tx_ring[BEACON_QUEUE]; 1044 pskb = __skb_dequeue(&ring->queue); 1045 if (rtlpriv->use_new_trx_flow) 1046 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1047 else 1048 entry = (u8 *)(&ring->desc[ring->idx]); 1049 if (pskb) { 1050 dma_unmap_single(&rtlpci->pdev->dev, 1051 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1052 true, HW_DESC_TXBUFF_ADDR), 1053 pskb->len, DMA_TO_DEVICE); 1054 kfree_skb(pskb); 1055 } 1056 1057 /*NB: the beacon data buffer must be 32-bit aligned. */ 1058 pskb = ieee80211_beacon_get(hw, mac->vif, 0); 1059 if (!pskb) 1060 return; 1061 hdr = rtl_get_hdr(pskb); 1062 info = IEEE80211_SKB_CB(pskb); 1063 pdesc = &ring->desc[0]; 1064 if (rtlpriv->use_new_trx_flow) 1065 pbuffer_desc = &ring->buffer_desc[0]; 1066 1067 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1068 (u8 *)pbuffer_desc, info, NULL, pskb, 1069 BEACON_QUEUE, &tcb_desc); 1070 1071 __skb_queue_tail(&ring->queue, pskb); 1072 1073 if (rtlpriv->use_new_trx_flow) { 1074 temp_one = 4; 1075 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, 1076 HW_DESC_OWN, (u8 *)&temp_one); 1077 } else { 1078 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, 1079 &temp_one); 1080 } 1081} 1082 1083static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) 1084{ 1085 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1086 struct rtl_priv *rtlpriv = rtl_priv(hw); 1087 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1088 u8 i; 1089 u16 desc_num; 1090 1091 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) 1092 desc_num = TX_DESC_NUM_92E; 1093 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) 1094 desc_num = TX_DESC_NUM_8822B; 1095 else 1096 desc_num = RT_TXDESC_NUM; 1097 1098 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1099 rtlpci->txringcount[i] = desc_num; 1100 1101 /*we just alloc 2 desc for beacon queue, 1102 *because we just need first desc in hw beacon. 1103 */ 1104 rtlpci->txringcount[BEACON_QUEUE] = 2; 1105 1106 /*BE queue need more descriptor for performance 1107 *consideration or, No more tx desc will happen, 1108 *and may cause mac80211 mem leakage. 1109 */ 1110 if (!rtl_priv(hw)->use_new_trx_flow) 1111 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; 1112 1113 rtlpci->rxbuffersize = 9100; /*2048/1024; */ 1114 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ 1115} 1116 1117static void _rtl_pci_init_struct(struct ieee80211_hw *hw, 1118 struct pci_dev *pdev) 1119{ 1120 struct rtl_priv *rtlpriv = rtl_priv(hw); 1121 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1122 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1124 1125 rtlpci->up_first_time = true; 1126 rtlpci->being_init_adapter = false; 1127 1128 rtlhal->hw = hw; 1129 rtlpci->pdev = pdev; 1130 1131 /*Tx/Rx related var */ 1132 _rtl_pci_init_trx_var(hw); 1133 1134 /*IBSS*/ 1135 mac->beacon_interval = 100; 1136 1137 /*AMPDU*/ 1138 mac->min_space_cfg = 0; 1139 mac->max_mss_density = 0; 1140 /*set sane AMPDU defaults */ 1141 mac->current_ampdu_density = 7; 1142 mac->current_ampdu_factor = 3; 1143 1144 /*Retry Limit*/ 1145 mac->retry_short = 7; 1146 mac->retry_long = 7; 1147 1148 /*QOS*/ 1149 rtlpci->acm_method = EACMWAY2_SW; 1150 1151 /*task */ 1152 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet); 1153 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet, 1154 _rtl_pci_prepare_bcn_tasklet); 1155 INIT_WORK(&rtlpriv->works.lps_change_work, 1156 rtl_lps_change_work_callback); 1157} 1158 1159static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1160 unsigned int prio, unsigned int entries) 1161{ 1162 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1163 struct rtl_priv *rtlpriv = rtl_priv(hw); 1164 struct rtl_tx_buffer_desc *buffer_desc; 1165 struct rtl_tx_desc *desc; 1166 dma_addr_t buffer_desc_dma, desc_dma; 1167 u32 nextdescaddress; 1168 int i; 1169 1170 /* alloc tx buffer desc for new trx flow*/ 1171 if (rtlpriv->use_new_trx_flow) { 1172 buffer_desc = 1173 dma_alloc_coherent(&rtlpci->pdev->dev, 1174 sizeof(*buffer_desc) * entries, 1175 &buffer_desc_dma, GFP_KERNEL); 1176 1177 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { 1178 pr_err("Cannot allocate TX ring (prio = %d)\n", 1179 prio); 1180 return -ENOMEM; 1181 } 1182 1183 rtlpci->tx_ring[prio].buffer_desc = buffer_desc; 1184 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; 1185 1186 rtlpci->tx_ring[prio].cur_tx_rp = 0; 1187 rtlpci->tx_ring[prio].cur_tx_wp = 0; 1188 } 1189 1190 /* alloc dma for this ring */ 1191 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries, 1192 &desc_dma, GFP_KERNEL); 1193 1194 if (!desc || (unsigned long)desc & 0xFF) { 1195 pr_err("Cannot allocate TX ring (prio = %d)\n", prio); 1196 return -ENOMEM; 1197 } 1198 1199 rtlpci->tx_ring[prio].desc = desc; 1200 rtlpci->tx_ring[prio].dma = desc_dma; 1201 1202 rtlpci->tx_ring[prio].idx = 0; 1203 rtlpci->tx_ring[prio].entries = entries; 1204 skb_queue_head_init(&rtlpci->tx_ring[prio].queue); 1205 1206 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", 1207 prio, desc); 1208 1209 /* init every desc in this ring */ 1210 if (!rtlpriv->use_new_trx_flow) { 1211 for (i = 0; i < entries; i++) { 1212 nextdescaddress = (u32)desc_dma + 1213 ((i + 1) % entries) * 1214 sizeof(*desc); 1215 1216 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], 1217 true, 1218 HW_DESC_TX_NEXTDESC_ADDR, 1219 (u8 *)&nextdescaddress); 1220 } 1221 } 1222 return 0; 1223} 1224 1225static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1226{ 1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1228 struct rtl_priv *rtlpriv = rtl_priv(hw); 1229 int i; 1230 1231 if (rtlpriv->use_new_trx_flow) { 1232 struct rtl_rx_buffer_desc *entry = NULL; 1233 /* alloc dma for this ring */ 1234 rtlpci->rx_ring[rxring_idx].buffer_desc = 1235 dma_alloc_coherent(&rtlpci->pdev->dev, 1236 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1237 rtlpci->rxringcount, 1238 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1239 if (!rtlpci->rx_ring[rxring_idx].buffer_desc || 1240 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { 1241 pr_err("Cannot allocate RX ring\n"); 1242 return -ENOMEM; 1243 } 1244 1245 /* init every desc in this ring */ 1246 rtlpci->rx_ring[rxring_idx].idx = 0; 1247 for (i = 0; i < rtlpci->rxringcount; i++) { 1248 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; 1249 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1250 rxring_idx, i)) 1251 return -ENOMEM; 1252 } 1253 } else { 1254 struct rtl_rx_desc *entry = NULL; 1255 u8 tmp_one = 1; 1256 /* alloc dma for this ring */ 1257 rtlpci->rx_ring[rxring_idx].desc = 1258 dma_alloc_coherent(&rtlpci->pdev->dev, 1259 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1260 rtlpci->rxringcount, 1261 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL); 1262 if (!rtlpci->rx_ring[rxring_idx].desc || 1263 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { 1264 pr_err("Cannot allocate RX ring\n"); 1265 return -ENOMEM; 1266 } 1267 1268 /* init every desc in this ring */ 1269 rtlpci->rx_ring[rxring_idx].idx = 0; 1270 1271 for (i = 0; i < rtlpci->rxringcount; i++) { 1272 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1273 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, 1274 rxring_idx, i)) 1275 return -ENOMEM; 1276 } 1277 1278 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1279 HW_DESC_RXERO, &tmp_one); 1280 } 1281 return 0; 1282} 1283 1284static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, 1285 unsigned int prio) 1286{ 1287 struct rtl_priv *rtlpriv = rtl_priv(hw); 1288 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1289 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; 1290 1291 /* free every desc in this ring */ 1292 while (skb_queue_len(&ring->queue)) { 1293 u8 *entry; 1294 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1295 1296 if (rtlpriv->use_new_trx_flow) 1297 entry = (u8 *)(&ring->buffer_desc[ring->idx]); 1298 else 1299 entry = (u8 *)(&ring->desc[ring->idx]); 1300 1301 dma_unmap_single(&rtlpci->pdev->dev, 1302 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1303 true, HW_DESC_TXBUFF_ADDR), 1304 skb->len, DMA_TO_DEVICE); 1305 kfree_skb(skb); 1306 ring->idx = (ring->idx + 1) % ring->entries; 1307 } 1308 1309 /* free dma of this ring */ 1310 dma_free_coherent(&rtlpci->pdev->dev, 1311 sizeof(*ring->desc) * ring->entries, ring->desc, 1312 ring->dma); 1313 ring->desc = NULL; 1314 if (rtlpriv->use_new_trx_flow) { 1315 dma_free_coherent(&rtlpci->pdev->dev, 1316 sizeof(*ring->buffer_desc) * ring->entries, 1317 ring->buffer_desc, ring->buffer_desc_dma); 1318 ring->buffer_desc = NULL; 1319 } 1320} 1321 1322static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) 1323{ 1324 struct rtl_priv *rtlpriv = rtl_priv(hw); 1325 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1326 int i; 1327 1328 /* free every desc in this ring */ 1329 for (i = 0; i < rtlpci->rxringcount; i++) { 1330 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; 1331 1332 if (!skb) 1333 continue; 1334 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb), 1335 rtlpci->rxbuffersize, DMA_FROM_DEVICE); 1336 kfree_skb(skb); 1337 } 1338 1339 /* free dma of this ring */ 1340 if (rtlpriv->use_new_trx_flow) { 1341 dma_free_coherent(&rtlpci->pdev->dev, 1342 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * 1343 rtlpci->rxringcount, 1344 rtlpci->rx_ring[rxring_idx].buffer_desc, 1345 rtlpci->rx_ring[rxring_idx].dma); 1346 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; 1347 } else { 1348 dma_free_coherent(&rtlpci->pdev->dev, 1349 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * 1350 rtlpci->rxringcount, 1351 rtlpci->rx_ring[rxring_idx].desc, 1352 rtlpci->rx_ring[rxring_idx].dma); 1353 rtlpci->rx_ring[rxring_idx].desc = NULL; 1354 } 1355} 1356 1357static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) 1358{ 1359 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1360 int ret; 1361 int i, rxring_idx; 1362 1363 /* rxring_idx 0:RX_MPDU_QUEUE 1364 * rxring_idx 1:RX_CMD_QUEUE 1365 */ 1366 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1367 ret = _rtl_pci_init_rx_ring(hw, rxring_idx); 1368 if (ret) 1369 return ret; 1370 } 1371 1372 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1373 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]); 1374 if (ret) 1375 goto err_free_rings; 1376 } 1377 1378 return 0; 1379 1380err_free_rings: 1381 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1382 _rtl_pci_free_rx_ring(hw, rxring_idx); 1383 1384 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1385 if (rtlpci->tx_ring[i].desc || 1386 rtlpci->tx_ring[i].buffer_desc) 1387 _rtl_pci_free_tx_ring(hw, i); 1388 1389 return 1; 1390} 1391 1392static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) 1393{ 1394 u32 i, rxring_idx; 1395 1396 /*free rx rings */ 1397 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) 1398 _rtl_pci_free_rx_ring(hw, rxring_idx); 1399 1400 /*free tx rings */ 1401 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) 1402 _rtl_pci_free_tx_ring(hw, i); 1403 1404 return 0; 1405} 1406 1407int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) 1408{ 1409 struct rtl_priv *rtlpriv = rtl_priv(hw); 1410 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1411 int i, rxring_idx; 1412 unsigned long flags; 1413 u8 tmp_one = 1; 1414 u32 bufferaddress; 1415 /* rxring_idx 0:RX_MPDU_QUEUE */ 1416 /* rxring_idx 1:RX_CMD_QUEUE */ 1417 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { 1418 /* force the rx_ring[RX_MPDU_QUEUE/ 1419 * RX_CMD_QUEUE].idx to the first one 1420 *new trx flow, do nothing 1421 */ 1422 if (!rtlpriv->use_new_trx_flow && 1423 rtlpci->rx_ring[rxring_idx].desc) { 1424 struct rtl_rx_desc *entry = NULL; 1425 1426 rtlpci->rx_ring[rxring_idx].idx = 0; 1427 for (i = 0; i < rtlpci->rxringcount; i++) { 1428 entry = &rtlpci->rx_ring[rxring_idx].desc[i]; 1429 bufferaddress = 1430 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1431 false, HW_DESC_RXBUFF_ADDR); 1432 memset((u8 *)entry, 0, 1433 sizeof(*rtlpci->rx_ring 1434 [rxring_idx].desc));/*clear one entry*/ 1435 if (rtlpriv->use_new_trx_flow) { 1436 rtlpriv->cfg->ops->set_desc(hw, 1437 (u8 *)entry, false, 1438 HW_DESC_RX_PREPARE, 1439 (u8 *)&bufferaddress); 1440 } else { 1441 rtlpriv->cfg->ops->set_desc(hw, 1442 (u8 *)entry, false, 1443 HW_DESC_RXBUFF_ADDR, 1444 (u8 *)&bufferaddress); 1445 rtlpriv->cfg->ops->set_desc(hw, 1446 (u8 *)entry, false, 1447 HW_DESC_RXPKT_LEN, 1448 (u8 *)&rtlpci->rxbuffersize); 1449 rtlpriv->cfg->ops->set_desc(hw, 1450 (u8 *)entry, false, 1451 HW_DESC_RXOWN, 1452 (u8 *)&tmp_one); 1453 } 1454 } 1455 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, 1456 HW_DESC_RXERO, (u8 *)&tmp_one); 1457 } 1458 rtlpci->rx_ring[rxring_idx].idx = 0; 1459 } 1460 1461 /*after reset, release previous pending packet, 1462 *and force the tx idx to the first one 1463 */ 1464 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1465 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { 1466 if (rtlpci->tx_ring[i].desc || 1467 rtlpci->tx_ring[i].buffer_desc) { 1468 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; 1469 1470 while (skb_queue_len(&ring->queue)) { 1471 u8 *entry; 1472 struct sk_buff *skb = 1473 __skb_dequeue(&ring->queue); 1474 if (rtlpriv->use_new_trx_flow) 1475 entry = (u8 *)(&ring->buffer_desc 1476 [ring->idx]); 1477 else 1478 entry = (u8 *)(&ring->desc[ring->idx]); 1479 1480 dma_unmap_single(&rtlpci->pdev->dev, 1481 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, 1482 true, HW_DESC_TXBUFF_ADDR), 1483 skb->len, DMA_TO_DEVICE); 1484 dev_kfree_skb_irq(skb); 1485 ring->idx = (ring->idx + 1) % ring->entries; 1486 } 1487 1488 if (rtlpriv->use_new_trx_flow) { 1489 rtlpci->tx_ring[i].cur_tx_rp = 0; 1490 rtlpci->tx_ring[i].cur_tx_wp = 0; 1491 } 1492 1493 ring->idx = 0; 1494 ring->entries = rtlpci->txringcount[i]; 1495 } 1496 } 1497 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1498 1499 return 0; 1500} 1501 1502static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, 1503 struct ieee80211_sta *sta, 1504 struct sk_buff *skb) 1505{ 1506 struct rtl_priv *rtlpriv = rtl_priv(hw); 1507 struct rtl_sta_info *sta_entry = NULL; 1508 u8 tid = rtl_get_tid(skb); 1509 __le16 fc = rtl_get_fc(skb); 1510 1511 if (!sta) 1512 return false; 1513 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1514 1515 if (!rtlpriv->rtlhal.earlymode_enable) 1516 return false; 1517 if (ieee80211_is_nullfunc(fc)) 1518 return false; 1519 if (ieee80211_is_qos_nullfunc(fc)) 1520 return false; 1521 if (ieee80211_is_pspoll(fc)) 1522 return false; 1523 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) 1524 return false; 1525 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) 1526 return false; 1527 if (tid > 7) 1528 return false; 1529 1530 /* maybe every tid should be checked */ 1531 if (!rtlpriv->link_info.higher_busytxtraffic[tid]) 1532 return false; 1533 1534 spin_lock_bh(&rtlpriv->locks.waitq_lock); 1535 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); 1536 spin_unlock_bh(&rtlpriv->locks.waitq_lock); 1537 1538 return true; 1539} 1540 1541static int rtl_pci_tx(struct ieee80211_hw *hw, 1542 struct ieee80211_sta *sta, 1543 struct sk_buff *skb, 1544 struct rtl_tcb_desc *ptcb_desc) 1545{ 1546 struct rtl_priv *rtlpriv = rtl_priv(hw); 1547 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1548 struct rtl8192_tx_ring *ring; 1549 struct rtl_tx_desc *pdesc; 1550 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; 1551 u16 idx; 1552 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); 1553 unsigned long flags; 1554 struct ieee80211_hdr *hdr = rtl_get_hdr(skb); 1555 __le16 fc = rtl_get_fc(skb); 1556 u8 *pda_addr = hdr->addr1; 1557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1558 u8 own; 1559 u8 temp_one = 1; 1560 1561 if (ieee80211_is_mgmt(fc)) 1562 rtl_tx_mgmt_proc(hw, skb); 1563 1564 if (rtlpriv->psc.sw_ps_enabled) { 1565 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && 1566 !ieee80211_has_pm(fc)) 1567 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 1568 } 1569 1570 rtl_action_proc(hw, skb, true); 1571 1572 if (is_multicast_ether_addr(pda_addr)) 1573 rtlpriv->stats.txbytesmulticast += skb->len; 1574 else if (is_broadcast_ether_addr(pda_addr)) 1575 rtlpriv->stats.txbytesbroadcast += skb->len; 1576 else 1577 rtlpriv->stats.txbytesunicast += skb->len; 1578 1579 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 1580 ring = &rtlpci->tx_ring[hw_queue]; 1581 if (hw_queue != BEACON_QUEUE) { 1582 if (rtlpriv->use_new_trx_flow) 1583 idx = ring->cur_tx_wp; 1584 else 1585 idx = (ring->idx + skb_queue_len(&ring->queue)) % 1586 ring->entries; 1587 } else { 1588 idx = 0; 1589 } 1590 1591 pdesc = &ring->desc[idx]; 1592 if (rtlpriv->use_new_trx_flow) { 1593 ptx_bd_desc = &ring->buffer_desc[idx]; 1594 } else { 1595 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, 1596 true, HW_DESC_OWN); 1597 1598 if (own == 1 && hw_queue != BEACON_QUEUE) { 1599 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1600 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1601 hw_queue, ring->idx, idx, 1602 skb_queue_len(&ring->queue)); 1603 1604 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, 1605 flags); 1606 return skb->len; 1607 } 1608 } 1609 1610 if (rtlpriv->cfg->ops->get_available_desc && 1611 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { 1612 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1613 "get_available_desc fail\n"); 1614 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1615 return skb->len; 1616 } 1617 1618 if (ieee80211_is_data(fc)) 1619 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); 1620 1621 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, 1622 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); 1623 1624 __skb_queue_tail(&ring->queue, skb); 1625 1626 if (rtlpriv->use_new_trx_flow) { 1627 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1628 HW_DESC_OWN, &hw_queue); 1629 } else { 1630 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, 1631 HW_DESC_OWN, &temp_one); 1632 } 1633 1634 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && 1635 hw_queue != BEACON_QUEUE) { 1636 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, 1637 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", 1638 hw_queue, ring->idx, idx, 1639 skb_queue_len(&ring->queue)); 1640 1641 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 1642 } 1643 1644 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); 1645 1646 rtlpriv->cfg->ops->tx_polling(hw, hw_queue); 1647 1648 return 0; 1649} 1650 1651static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1652{ 1653 struct rtl_priv *rtlpriv = rtl_priv(hw); 1654 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1655 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1656 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1657 u16 i = 0; 1658 int queue_id; 1659 struct rtl8192_tx_ring *ring; 1660 1661 if (mac->skip_scan) 1662 return; 1663 1664 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { 1665 u32 queue_len; 1666 1667 if (((queues >> queue_id) & 0x1) == 0) { 1668 queue_id--; 1669 continue; 1670 } 1671 ring = &pcipriv->dev.tx_ring[queue_id]; 1672 queue_len = skb_queue_len(&ring->queue); 1673 if (queue_len == 0 || queue_id == BEACON_QUEUE || 1674 queue_id == TXCMD_QUEUE) { 1675 queue_id--; 1676 continue; 1677 } else { 1678 msleep(20); 1679 i++; 1680 } 1681 1682 /* we just wait 1s for all queues */ 1683 if (rtlpriv->psc.rfpwr_state == ERFOFF || 1684 is_hal_stop(rtlhal) || i >= 200) 1685 return; 1686 } 1687} 1688 1689static void rtl_pci_deinit(struct ieee80211_hw *hw) 1690{ 1691 struct rtl_priv *rtlpriv = rtl_priv(hw); 1692 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1693 1694 _rtl_pci_deinit_trx_ring(hw); 1695 1696 synchronize_irq(rtlpci->pdev->irq); 1697 tasklet_kill(&rtlpriv->works.irq_tasklet); 1698 cancel_work_sync(&rtlpriv->works.lps_change_work); 1699 1700 destroy_workqueue(rtlpriv->works.rtl_wq); 1701} 1702 1703static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1704{ 1705 int err; 1706 1707 _rtl_pci_init_struct(hw, pdev); 1708 1709 err = _rtl_pci_init_trx_ring(hw); 1710 if (err) { 1711 pr_err("tx ring initialization failed\n"); 1712 return err; 1713 } 1714 1715 return 0; 1716} 1717 1718static int rtl_pci_start(struct ieee80211_hw *hw) 1719{ 1720 struct rtl_priv *rtlpriv = rtl_priv(hw); 1721 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1722 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1723 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1724 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 1725 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; 1726 1727 int err; 1728 1729 rtl_pci_reset_trx_ring(hw); 1730 1731 rtlpci->driver_is_goingto_unload = false; 1732 if (rtlpriv->cfg->ops->get_btc_status && 1733 rtlpriv->cfg->ops->get_btc_status()) { 1734 rtlpriv->btcoexist.btc_info.ap_num = 36; 1735 btc_ops->btc_init_variables(rtlpriv); 1736 btc_ops->btc_init_hal_vars(rtlpriv); 1737 } else if (btc_ops) { 1738 btc_ops->btc_init_variables_wifi_only(rtlpriv); 1739 } 1740 1741 err = rtlpriv->cfg->ops->hw_init(hw); 1742 if (err) { 1743 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1744 "Failed to config hardware!\n"); 1745 kfree(rtlpriv->btcoexist.btc_context); 1746 kfree(rtlpriv->btcoexist.wifi_only_context); 1747 return err; 1748 } 1749 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 1750 &rtlmac->retry_long); 1751 1752 rtlpriv->cfg->ops->enable_interrupt(hw); 1753 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); 1754 1755 rtl_init_rx_config(hw); 1756 1757 /*should be after adapter start and interrupt enable. */ 1758 set_hal_start(rtlhal); 1759 1760 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1761 1762 rtlpci->up_first_time = false; 1763 1764 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); 1765 return 0; 1766} 1767 1768static void rtl_pci_stop(struct ieee80211_hw *hw) 1769{ 1770 struct rtl_priv *rtlpriv = rtl_priv(hw); 1771 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1772 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1774 unsigned long flags; 1775 u8 rf_timeout = 0; 1776 1777 if (rtlpriv->cfg->ops->get_btc_status()) 1778 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv); 1779 1780 if (rtlpriv->btcoexist.btc_ops) 1781 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv); 1782 1783 /*should be before disable interrupt&adapter 1784 *and will do it immediately. 1785 */ 1786 set_hal_stop(rtlhal); 1787 1788 rtlpci->driver_is_goingto_unload = true; 1789 rtlpriv->cfg->ops->disable_interrupt(hw); 1790 cancel_work_sync(&rtlpriv->works.lps_change_work); 1791 1792 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1793 while (ppsc->rfchange_inprogress) { 1794 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1795 if (rf_timeout > 100) { 1796 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1797 break; 1798 } 1799 mdelay(1); 1800 rf_timeout++; 1801 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1802 } 1803 ppsc->rfchange_inprogress = true; 1804 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1805 1806 rtlpriv->cfg->ops->hw_disable(hw); 1807 /* some things are not needed if firmware not available */ 1808 if (!rtlpriv->max_fw_size) 1809 return; 1810 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1811 1812 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1813 ppsc->rfchange_inprogress = false; 1814 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); 1815 1816 rtl_pci_enable_aspm(hw); 1817} 1818 1819static bool _rtl_pci_find_adapter(struct pci_dev *pdev, 1820 struct ieee80211_hw *hw) 1821{ 1822 struct rtl_priv *rtlpriv = rtl_priv(hw); 1823 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1824 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1825 struct pci_dev *bridge_pdev = pdev->bus->self; 1826 u16 venderid; 1827 u16 deviceid; 1828 u8 revisionid; 1829 u16 irqline; 1830 u8 tmp; 1831 1832 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1833 venderid = pdev->vendor; 1834 deviceid = pdev->device; 1835 pci_read_config_byte(pdev, 0x8, &revisionid); 1836 pci_read_config_word(pdev, 0x3C, &irqline); 1837 1838 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses 1839 * r8192e_pci, and RTL8192SE, which uses this driver. If the 1840 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then 1841 * the correct driver is r8192e_pci, thus this routine should 1842 * return false. 1843 */ 1844 if (deviceid == RTL_PCI_8192SE_DID && 1845 revisionid == RTL_PCI_REVISION_ID_8192PCIE) 1846 return false; 1847 1848 if (deviceid == RTL_PCI_8192_DID || 1849 deviceid == RTL_PCI_0044_DID || 1850 deviceid == RTL_PCI_0047_DID || 1851 deviceid == RTL_PCI_8192SE_DID || 1852 deviceid == RTL_PCI_8174_DID || 1853 deviceid == RTL_PCI_8173_DID || 1854 deviceid == RTL_PCI_8172_DID || 1855 deviceid == RTL_PCI_8171_DID) { 1856 switch (revisionid) { 1857 case RTL_PCI_REVISION_ID_8192PCIE: 1858 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1859 "8192 PCI-E is found - vid/did=%x/%x\n", 1860 venderid, deviceid); 1861 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; 1862 return false; 1863 case RTL_PCI_REVISION_ID_8192SE: 1864 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1865 "8192SE is found - vid/did=%x/%x\n", 1866 venderid, deviceid); 1867 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1868 break; 1869 default: 1870 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1871 "Err: Unknown device - vid/did=%x/%x\n", 1872 venderid, deviceid); 1873 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; 1874 break; 1875 } 1876 } else if (deviceid == RTL_PCI_8723AE_DID) { 1877 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; 1878 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1879 "8723AE PCI-E is found - vid/did=%x/%x\n", 1880 venderid, deviceid); 1881 } else if (deviceid == RTL_PCI_8192CET_DID || 1882 deviceid == RTL_PCI_8192CE_DID || 1883 deviceid == RTL_PCI_8191CE_DID || 1884 deviceid == RTL_PCI_8188CE_DID) { 1885 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; 1886 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1887 "8192C PCI-E is found - vid/did=%x/%x\n", 1888 venderid, deviceid); 1889 } else if (deviceid == RTL_PCI_8192DE_DID || 1890 deviceid == RTL_PCI_8192DE_DID2) { 1891 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; 1892 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1893 "8192D PCI-E is found - vid/did=%x/%x\n", 1894 venderid, deviceid); 1895 } else if (deviceid == RTL_PCI_8188EE_DID) { 1896 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; 1897 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1898 "Find adapter, Hardware type is 8188EE\n"); 1899 } else if (deviceid == RTL_PCI_8723BE_DID) { 1900 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; 1901 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1902 "Find adapter, Hardware type is 8723BE\n"); 1903 } else if (deviceid == RTL_PCI_8192EE_DID) { 1904 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; 1905 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1906 "Find adapter, Hardware type is 8192EE\n"); 1907 } else if (deviceid == RTL_PCI_8821AE_DID) { 1908 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; 1909 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1910 "Find adapter, Hardware type is 8821AE\n"); 1911 } else if (deviceid == RTL_PCI_8812AE_DID) { 1912 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; 1913 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1914 "Find adapter, Hardware type is 8812AE\n"); 1915 } else if (deviceid == RTL_PCI_8822BE_DID) { 1916 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; 1917 rtlhal->bandset = BAND_ON_BOTH; 1918 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1919 "Find adapter, Hardware type is 8822BE\n"); 1920 } else { 1921 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, 1922 "Err: Unknown device - vid/did=%x/%x\n", 1923 venderid, deviceid); 1924 1925 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; 1926 } 1927 1928 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { 1929 if (revisionid == 0 || revisionid == 1) { 1930 if (revisionid == 0) { 1931 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1932 "Find 92DE MAC0\n"); 1933 rtlhal->interfaceindex = 0; 1934 } else if (revisionid == 1) { 1935 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1936 "Find 92DE MAC1\n"); 1937 rtlhal->interfaceindex = 1; 1938 } 1939 } else { 1940 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, 1941 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", 1942 venderid, deviceid, revisionid); 1943 rtlhal->interfaceindex = 0; 1944 } 1945 } 1946 1947 switch (rtlhal->hw_type) { 1948 case HARDWARE_TYPE_RTL8192EE: 1949 case HARDWARE_TYPE_RTL8822BE: 1950 /* use new trx flow */ 1951 rtlpriv->use_new_trx_flow = true; 1952 break; 1953 1954 default: 1955 rtlpriv->use_new_trx_flow = false; 1956 break; 1957 } 1958 1959 /*find bus info */ 1960 pcipriv->ndis_adapter.busnumber = pdev->bus->number; 1961 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); 1962 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); 1963 1964 /*find bridge info */ 1965 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; 1966 /* some ARM have no bridge_pdev and will crash here 1967 * so we should check if bridge_pdev is NULL 1968 */ 1969 if (bridge_pdev) { 1970 /*find bridge info if available */ 1971 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { 1972 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { 1973 pcipriv->ndis_adapter.pcibridge_vendor = tmp; 1974 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1975 "Pci Bridge Vendor is found index: %d\n", 1976 tmp); 1977 break; 1978 } 1979 } 1980 } 1981 1982 if (pcipriv->ndis_adapter.pcibridge_vendor != 1983 PCI_BRIDGE_VENDOR_UNKNOWN) { 1984 pcipriv->ndis_adapter.pcibridge_busnum = 1985 bridge_pdev->bus->number; 1986 pcipriv->ndis_adapter.pcibridge_devnum = 1987 PCI_SLOT(bridge_pdev->devfn); 1988 pcipriv->ndis_adapter.pcibridge_funcnum = 1989 PCI_FUNC(bridge_pdev->devfn); 1990 1991 if (pcipriv->ndis_adapter.pcibridge_vendor == 1992 PCI_BRIDGE_VENDOR_AMD) { 1993 pcipriv->ndis_adapter.amd_l1_patch = 1994 rtl_pci_get_amd_l1_patch(hw); 1995 } 1996 } 1997 1998 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 1999 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", 2000 pcipriv->ndis_adapter.busnumber, 2001 pcipriv->ndis_adapter.devnumber, 2002 pcipriv->ndis_adapter.funcnumber, 2003 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); 2004 2005 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2006 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n", 2007 pcipriv->ndis_adapter.pcibridge_busnum, 2008 pcipriv->ndis_adapter.pcibridge_devnum, 2009 pcipriv->ndis_adapter.pcibridge_funcnum, 2010 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], 2011 pcipriv->ndis_adapter.amd_l1_patch); 2012 2013 rtl_pci_parse_configuration(pdev, hw); 2014 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); 2015 2016 return true; 2017} 2018 2019static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) 2020{ 2021 struct rtl_priv *rtlpriv = rtl_priv(hw); 2022 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2023 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2024 int ret; 2025 2026 ret = pci_enable_msi(rtlpci->pdev); 2027 if (ret < 0) 2028 return ret; 2029 2030 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2031 IRQF_SHARED, KBUILD_MODNAME, hw); 2032 if (ret < 0) { 2033 pci_disable_msi(rtlpci->pdev); 2034 return ret; 2035 } 2036 2037 rtlpci->using_msi = true; 2038 2039 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2040 "MSI Interrupt Mode!\n"); 2041 return 0; 2042} 2043 2044static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) 2045{ 2046 struct rtl_priv *rtlpriv = rtl_priv(hw); 2047 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2048 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2049 int ret; 2050 2051 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, 2052 IRQF_SHARED, KBUILD_MODNAME, hw); 2053 if (ret < 0) 2054 return ret; 2055 2056 rtlpci->using_msi = false; 2057 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, 2058 "Pin-based Interrupt Mode!\n"); 2059 return 0; 2060} 2061 2062static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) 2063{ 2064 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2065 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2066 int ret; 2067 2068 if (rtlpci->msi_support) { 2069 ret = rtl_pci_intr_mode_msi(hw); 2070 if (ret < 0) 2071 ret = rtl_pci_intr_mode_legacy(hw); 2072 } else { 2073 ret = rtl_pci_intr_mode_legacy(hw); 2074 } 2075 return ret; 2076} 2077 2078static void platform_enable_dma64(struct pci_dev *pdev, bool dma64) 2079{ 2080 u8 value; 2081 2082 pci_read_config_byte(pdev, 0x719, &value); 2083 2084 /* 0x719 Bit5 is DMA64 bit fetch. */ 2085 if (dma64) 2086 value |= BIT(5); 2087 else 2088 value &= ~BIT(5); 2089 2090 pci_write_config_byte(pdev, 0x719, value); 2091} 2092 2093int rtl_pci_probe(struct pci_dev *pdev, 2094 const struct pci_device_id *id) 2095{ 2096 struct ieee80211_hw *hw = NULL; 2097 2098 struct rtl_priv *rtlpriv = NULL; 2099 struct rtl_pci_priv *pcipriv = NULL; 2100 struct rtl_pci *rtlpci; 2101 unsigned long pmem_start, pmem_len, pmem_flags; 2102 int err; 2103 2104 err = pci_enable_device(pdev); 2105 if (err) { 2106 WARN_ONCE(true, "%s : Cannot enable new PCI device\n", 2107 pci_name(pdev)); 2108 return err; 2109 } 2110 2111 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 && 2112 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2113 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { 2114 WARN_ONCE(true, 2115 "Unable to obtain 64bit DMA for consistent allocations\n"); 2116 err = -ENOMEM; 2117 goto fail1; 2118 } 2119 2120 platform_enable_dma64(pdev, true); 2121 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2122 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 2123 WARN_ONCE(true, 2124 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n"); 2125 err = -ENOMEM; 2126 goto fail1; 2127 } 2128 2129 platform_enable_dma64(pdev, false); 2130 } 2131 2132 pci_set_master(pdev); 2133 2134 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + 2135 sizeof(struct rtl_priv), &rtl_ops); 2136 if (!hw) { 2137 WARN_ONCE(true, 2138 "%s : ieee80211 alloc failed\n", pci_name(pdev)); 2139 err = -ENOMEM; 2140 goto fail1; 2141 } 2142 2143 SET_IEEE80211_DEV(hw, &pdev->dev); 2144 pci_set_drvdata(pdev, hw); 2145 2146 rtlpriv = hw->priv; 2147 rtlpriv->hw = hw; 2148 pcipriv = (void *)rtlpriv->priv; 2149 pcipriv->dev.pdev = pdev; 2150 init_completion(&rtlpriv->firmware_loading_complete); 2151 /*proximity init here*/ 2152 rtlpriv->proximity.proxim_on = false; 2153 2154 pcipriv = (void *)rtlpriv->priv; 2155 pcipriv->dev.pdev = pdev; 2156 2157 /* init cfg & intf_ops */ 2158 rtlpriv->rtlhal.interface = INTF_PCI; 2159 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); 2160 rtlpriv->intf_ops = &rtl_pci_ops; 2161 rtlpriv->glb_var = &rtl_global_var; 2162 rtl_efuse_ops_init(hw); 2163 2164 /* MEM map */ 2165 err = pci_request_regions(pdev, KBUILD_MODNAME); 2166 if (err) { 2167 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n"); 2168 goto fail1; 2169 } 2170 2171 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); 2172 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); 2173 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); 2174 2175 /*shared mem start */ 2176 rtlpriv->io.pci_mem_start = 2177 (unsigned long)pci_iomap(pdev, 2178 rtlpriv->cfg->bar_id, pmem_len); 2179 if (rtlpriv->io.pci_mem_start == 0) { 2180 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n"); 2181 err = -ENOMEM; 2182 goto fail2; 2183 } 2184 2185 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2186 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", 2187 pmem_start, pmem_len, pmem_flags, 2188 rtlpriv->io.pci_mem_start); 2189 2190 /* Disable Clk Request */ 2191 pci_write_config_byte(pdev, 0x81, 0); 2192 /* leave D3 mode */ 2193 pci_write_config_byte(pdev, 0x44, 0); 2194 pci_write_config_byte(pdev, 0x04, 0x06); 2195 pci_write_config_byte(pdev, 0x04, 0x07); 2196 2197 /* find adapter */ 2198 if (!_rtl_pci_find_adapter(pdev, hw)) { 2199 err = -ENODEV; 2200 goto fail2; 2201 } 2202 2203 /* Init IO handler */ 2204 _rtl_pci_io_handler_init(&pdev->dev, hw); 2205 2206 /*like read eeprom and so on */ 2207 rtlpriv->cfg->ops->read_eeprom_info(hw); 2208 2209 if (rtlpriv->cfg->ops->init_sw_vars(hw)) { 2210 pr_err("Can't init_sw_vars\n"); 2211 err = -ENODEV; 2212 goto fail3; 2213 } 2214 rtl_init_sw_leds(hw); 2215 2216 /*aspm */ 2217 rtl_pci_init_aspm(hw); 2218 2219 /* Init mac80211 sw */ 2220 err = rtl_init_core(hw); 2221 if (err) { 2222 pr_err("Can't allocate sw for mac80211\n"); 2223 goto fail3; 2224 } 2225 2226 /* Init PCI sw */ 2227 err = rtl_pci_init(hw, pdev); 2228 if (err) { 2229 pr_err("Failed to init PCI\n"); 2230 goto fail3; 2231 } 2232 2233 err = ieee80211_register_hw(hw); 2234 if (err) { 2235 pr_err("Can't register mac80211 hw.\n"); 2236 err = -ENODEV; 2237 goto fail3; 2238 } 2239 rtlpriv->mac80211.mac80211_registered = 1; 2240 2241 /* add for debug */ 2242 rtl_debug_add_one(hw); 2243 2244 /*init rfkill */ 2245 rtl_init_rfkill(hw); /* Init PCI sw */ 2246 2247 rtlpci = rtl_pcidev(pcipriv); 2248 err = rtl_pci_intr_mode_decide(hw); 2249 if (err) { 2250 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, 2251 "%s: failed to register IRQ handler\n", 2252 wiphy_name(hw->wiphy)); 2253 goto fail3; 2254 } 2255 rtlpci->irq_alloc = 1; 2256 2257 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2258 return 0; 2259 2260fail3: 2261 pci_set_drvdata(pdev, NULL); 2262 rtl_deinit_core(hw); 2263 2264fail2: 2265 if (rtlpriv->io.pci_mem_start != 0) 2266 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2267 2268 pci_release_regions(pdev); 2269 complete(&rtlpriv->firmware_loading_complete); 2270 2271fail1: 2272 if (hw) 2273 ieee80211_free_hw(hw); 2274 pci_disable_device(pdev); 2275 2276 return err; 2277} 2278EXPORT_SYMBOL(rtl_pci_probe); 2279 2280void rtl_pci_disconnect(struct pci_dev *pdev) 2281{ 2282 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 2283 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 2284 struct rtl_priv *rtlpriv = rtl_priv(hw); 2285 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); 2286 struct rtl_mac *rtlmac = rtl_mac(rtlpriv); 2287 2288 /* just in case driver is removed before firmware callback */ 2289 wait_for_completion(&rtlpriv->firmware_loading_complete); 2290 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); 2291 2292 /* remove form debug */ 2293 rtl_debug_remove_one(hw); 2294 2295 /*ieee80211_unregister_hw will call ops_stop */ 2296 if (rtlmac->mac80211_registered == 1) { 2297 ieee80211_unregister_hw(hw); 2298 rtlmac->mac80211_registered = 0; 2299 } else { 2300 rtl_deinit_deferred_work(hw, false); 2301 rtlpriv->intf_ops->adapter_stop(hw); 2302 } 2303 rtlpriv->cfg->ops->disable_interrupt(hw); 2304 2305 /*deinit rfkill */ 2306 rtl_deinit_rfkill(hw); 2307 2308 rtl_pci_deinit(hw); 2309 rtl_deinit_core(hw); 2310 rtlpriv->cfg->ops->deinit_sw_vars(hw); 2311 2312 if (rtlpci->irq_alloc) { 2313 free_irq(rtlpci->pdev->irq, hw); 2314 rtlpci->irq_alloc = 0; 2315 } 2316 2317 if (rtlpci->using_msi) 2318 pci_disable_msi(rtlpci->pdev); 2319 2320 list_del(&rtlpriv->list); 2321 if (rtlpriv->io.pci_mem_start != 0) { 2322 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); 2323 pci_release_regions(pdev); 2324 } 2325 2326 pci_disable_device(pdev); 2327 2328 rtl_pci_disable_aspm(hw); 2329 2330 pci_set_drvdata(pdev, NULL); 2331 2332 ieee80211_free_hw(hw); 2333} 2334EXPORT_SYMBOL(rtl_pci_disconnect); 2335 2336#ifdef CONFIG_PM_SLEEP 2337/*************************************** 2338 * kernel pci power state define: 2339 * PCI_D0 ((pci_power_t __force) 0) 2340 * PCI_D1 ((pci_power_t __force) 1) 2341 * PCI_D2 ((pci_power_t __force) 2) 2342 * PCI_D3hot ((pci_power_t __force) 3) 2343 * PCI_D3cold ((pci_power_t __force) 4) 2344 * PCI_UNKNOWN ((pci_power_t __force) 5) 2345 2346 * This function is called when system 2347 * goes into suspend state mac80211 will 2348 * call rtl_mac_stop() from the mac80211 2349 * suspend function first, So there is 2350 * no need to call hw_disable here. 2351 ****************************************/ 2352int rtl_pci_suspend(struct device *dev) 2353{ 2354 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2355 struct rtl_priv *rtlpriv = rtl_priv(hw); 2356 2357 rtlpriv->cfg->ops->hw_suspend(hw); 2358 rtl_deinit_rfkill(hw); 2359 2360 return 0; 2361} 2362EXPORT_SYMBOL(rtl_pci_suspend); 2363 2364int rtl_pci_resume(struct device *dev) 2365{ 2366 struct ieee80211_hw *hw = dev_get_drvdata(dev); 2367 struct rtl_priv *rtlpriv = rtl_priv(hw); 2368 2369 rtlpriv->cfg->ops->hw_resume(hw); 2370 rtl_init_rfkill(hw); 2371 return 0; 2372} 2373EXPORT_SYMBOL(rtl_pci_resume); 2374#endif /* CONFIG_PM_SLEEP */ 2375 2376const struct rtl_intf_ops rtl_pci_ops = { 2377 .adapter_start = rtl_pci_start, 2378 .adapter_stop = rtl_pci_stop, 2379 .check_buddy_priv = rtl_pci_check_buddy_priv, 2380 .adapter_tx = rtl_pci_tx, 2381 .flush = rtl_pci_flush, 2382 .reset_trx_ring = rtl_pci_reset_trx_ring, 2383 .waitq_insert = rtl_pci_tx_chk_waitq_insert, 2384 2385 .disable_aspm = rtl_pci_disable_aspm, 2386 .enable_aspm = rtl_pci_enable_aspm, 2387}; 2388