1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8#include <asm/byteorder.h> 9#include <linux/average.h> 10 11#define RTL8XXXU_DEBUG_REG_WRITE 0x01 12#define RTL8XXXU_DEBUG_REG_READ 0x02 13#define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 14#define RTL8XXXU_DEBUG_RFREG_READ 0x08 15#define RTL8XXXU_DEBUG_CHANNEL 0x10 16#define RTL8XXXU_DEBUG_TX 0x20 17#define RTL8XXXU_DEBUG_TX_DUMP 0x40 18#define RTL8XXXU_DEBUG_RX 0x80 19#define RTL8XXXU_DEBUG_RX_DUMP 0x100 20#define RTL8XXXU_DEBUG_USB 0x200 21#define RTL8XXXU_DEBUG_KEY 0x400 22#define RTL8XXXU_DEBUG_H2C 0x800 23#define RTL8XXXU_DEBUG_ACTION 0x1000 24#define RTL8XXXU_DEBUG_EFUSE 0x2000 25#define RTL8XXXU_DEBUG_INTERRUPT 0x4000 26 27#define RTW_USB_CONTROL_MSG_TIMEOUT 500 28#define RTL8XXXU_MAX_REG_POLL 500 29#define USB_INTR_CONTENT_LENGTH 56 30 31#define RTL8XXXU_OUT_ENDPOINTS 6 32 33#define REALTEK_USB_READ 0xc0 34#define REALTEK_USB_WRITE 0x40 35#define REALTEK_USB_CMD_REQ 0x05 36#define REALTEK_USB_CMD_IDX 0x00 37 38#define TX_TOTAL_PAGE_NUM 0xf8 39#define TX_TOTAL_PAGE_NUM_8188F 0xf7 40#define TX_TOTAL_PAGE_NUM_8188E 0xa9 41#define TX_TOTAL_PAGE_NUM_8192E 0xf3 42#define TX_TOTAL_PAGE_NUM_8723B 0xf7 43#define TX_TOTAL_PAGE_NUM_8192F 0xf7 44/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ 45#define TX_PAGE_NUM_PUBQ 0xe7 46#define TX_PAGE_NUM_HI_PQ 0x0c 47#define TX_PAGE_NUM_LO_PQ 0x02 48#define TX_PAGE_NUM_NORM_PQ 0x02 49 50#define TX_PAGE_NUM_PUBQ_8188F 0xe5 51#define TX_PAGE_NUM_HI_PQ_8188F 0x0c 52#define TX_PAGE_NUM_LO_PQ_8188F 0x02 53#define TX_PAGE_NUM_NORM_PQ_8188F 0x02 54 55#define TX_PAGE_NUM_PUBQ_8188E 0x47 56#define TX_PAGE_NUM_HI_PQ_8188E 0x29 57#define TX_PAGE_NUM_LO_PQ_8188E 0x1c 58#define TX_PAGE_NUM_NORM_PQ_8188E 0x1c 59 60#define TX_PAGE_NUM_PUBQ_8192E 0xe7 61#define TX_PAGE_NUM_HI_PQ_8192E 0x08 62#define TX_PAGE_NUM_LO_PQ_8192E 0x0c 63#define TX_PAGE_NUM_NORM_PQ_8192E 0x00 64 65#define TX_PAGE_NUM_PUBQ_8723B 0xe7 66#define TX_PAGE_NUM_HI_PQ_8723B 0x0c 67#define TX_PAGE_NUM_LO_PQ_8723B 0x02 68#define TX_PAGE_NUM_NORM_PQ_8723B 0x02 69 70#define TX_PAGE_NUM_PUBQ_8192F 0xde 71#define TX_PAGE_NUM_HI_PQ_8192F 0x08 72#define TX_PAGE_NUM_LO_PQ_8192F 0x08 73#define TX_PAGE_NUM_NORM_PQ_8192F 0x08 74 75#define RTL_FW_PAGE_SIZE 4096 76#define RTL8XXXU_FIRMWARE_POLL_MAX 1000 77 78#define RTL8723A_CHANNEL_GROUPS 3 79#define RTL8723A_MAX_RF_PATHS 2 80#define RTL8723B_CHANNEL_GROUPS 6 81#define RTL8723B_TX_COUNT 4 82#define RTL8723B_MAX_RF_PATHS 4 83#define RTL8XXXU_MAX_CHANNEL_GROUPS 6 84#define RF6052_MAX_TX_PWR 0x3f 85 86#define EFUSE_MAP_LEN 512 87#define EFUSE_MAX_SECTION_8723A 64 88#define EFUSE_REAL_CONTENT_LEN_8723A 512 89#define EFUSE_BT_MAP_LEN_8723A 1024 90#define EFUSE_MAX_WORD_UNIT 4 91#define EFUSE_UNDEFINED 0xff 92 93enum rtl8xxxu_rtl_chip { 94 RTL8192S = 0x81920, 95 RTL8191S = 0x81910, 96 RTL8192C = 0x8192c, 97 RTL8191C = 0x8191c, 98 RTL8188C = 0x8188c, 99 RTL8188R = 0x81889, 100 RTL8192D = 0x8192d, 101 RTL8723A = 0x8723a, 102 RTL8188E = 0x8188e, 103 RTL8812 = 0x88120, 104 RTL8821 = 0x88210, 105 RTL8192E = 0x8192e, 106 RTL8191E = 0x8191e, 107 RTL8723B = 0x8723b, 108 RTL8814A = 0x8814a, 109 RTL8881A = 0x8881a, 110 RTL8821B = 0x8821b, 111 RTL8822B = 0x8822b, 112 RTL8703B = 0x8703b, 113 RTL8195A = 0x8195a, 114 RTL8188F = 0x8188f, 115 RTL8710B = 0x8710b, 116 RTL8192F = 0x8192f, 117}; 118 119enum rtl8xxxu_rx_type { 120 RX_TYPE_DATA_PKT = 0, 121 RX_TYPE_C2H = 1, 122 RX_TYPE_ERROR = -1 123}; 124 125struct rtl8xxxu_rxdesc16 { 126#ifdef __LITTLE_ENDIAN 127 u32 pktlen:14; 128 u32 crc32:1; 129 u32 icverr:1; 130 u32 drvinfo_sz:4; 131 u32 security:3; 132 u32 qos:1; 133 u32 shift:2; 134 u32 phy_stats:1; 135 u32 swdec:1; 136 u32 ls:1; 137 u32 fs:1; 138 u32 eor:1; 139 u32 own:1; 140 141 u32 macid:5; 142 u32 tid:4; 143 u32 hwrsvd:4; 144 u32 amsdu:1; 145 u32 paggr:1; 146 u32 faggr:1; 147 u32 a1fit:4; 148 u32 a2fit:4; 149 u32 pam:1; 150 u32 pwr:1; 151 u32 md:1; 152 u32 mf:1; 153 u32 type:2; 154 u32 mc:1; 155 u32 bc:1; 156 157 u32 seq:12; 158 u32 frag:4; 159 u32 pkt_cnt:8; 160 u32 reserved:6; 161 u32 nextind:1; 162 u32 reserved0:1; 163 164 u32 rxmcs:6; 165 u32 rxht:1; 166 u32 gf:1; 167 u32 splcp:1; 168 u32 bw:1; 169 u32 htc:1; 170 u32 eosp:1; 171 u32 bssidfit:2; 172 u32 rpt_sel:2; /* 8188e */ 173 u32 reserved1:14; 174 u32 unicastwake:1; 175 u32 magicwake:1; 176 177 u32 pattern0match:1; 178 u32 pattern1match:1; 179 u32 pattern2match:1; 180 u32 pattern3match:1; 181 u32 pattern4match:1; 182 u32 pattern5match:1; 183 u32 pattern6match:1; 184 u32 pattern7match:1; 185 u32 pattern8match:1; 186 u32 pattern9match:1; 187 u32 patternamatch:1; 188 u32 patternbmatch:1; 189 u32 patterncmatch:1; 190 u32 reserved2:19; 191#else 192 u32 own:1; 193 u32 eor:1; 194 u32 fs:1; 195 u32 ls:1; 196 u32 swdec:1; 197 u32 phy_stats:1; 198 u32 shift:2; 199 u32 qos:1; 200 u32 security:3; 201 u32 drvinfo_sz:4; 202 u32 icverr:1; 203 u32 crc32:1; 204 u32 pktlen:14; 205 206 u32 bc:1; 207 u32 mc:1; 208 u32 type:2; 209 u32 mf:1; 210 u32 md:1; 211 u32 pwr:1; 212 u32 pam:1; 213 u32 a2fit:4; 214 u32 a1fit:4; 215 u32 faggr:1; 216 u32 paggr:1; 217 u32 amsdu:1; 218 u32 hwrsvd:4; 219 u32 tid:4; 220 u32 macid:5; 221 222 u32 reserved0:1; 223 u32 nextind:1; 224 u32 reserved:6; 225 u32 pkt_cnt:8; 226 u32 frag:4; 227 u32 seq:12; 228 229 u32 magicwake:1; 230 u32 unicastwake:1; 231 u32 reserved1:14; 232 u32 rpt_sel:2; /* 8188e */ 233 u32 bssidfit:2; 234 u32 eosp:1; 235 u32 htc:1; 236 u32 bw:1; 237 u32 splcp:1; 238 u32 gf:1; 239 u32 rxht:1; 240 u32 rxmcs:6; 241 242 u32 reserved2:19; 243 u32 patterncmatch:1; 244 u32 patternbmatch:1; 245 u32 patternamatch:1; 246 u32 pattern9match:1; 247 u32 pattern8match:1; 248 u32 pattern7match:1; 249 u32 pattern6match:1; 250 u32 pattern5match:1; 251 u32 pattern4match:1; 252 u32 pattern3match:1; 253 u32 pattern2match:1; 254 u32 pattern1match:1; 255 u32 pattern0match:1; 256#endif 257 u32 tsfl; 258#if 0 259 u32 bassn:12; 260 u32 bavld:1; 261 u32 reserved3:19; 262#endif 263}; 264 265struct rtl8xxxu_rxdesc24 { 266#ifdef __LITTLE_ENDIAN 267 u32 pktlen:14; 268 u32 crc32:1; 269 u32 icverr:1; 270 u32 drvinfo_sz:4; 271 u32 security:3; 272 u32 qos:1; 273 u32 shift:2; 274 u32 phy_stats:1; 275 u32 swdec:1; 276 u32 ls:1; 277 u32 fs:1; 278 u32 eor:1; 279 u32 own:1; 280 281 u32 macid:7; 282 u32 dummy1_0:1; 283 u32 tid:4; 284 u32 dummy1_1:1; 285 u32 amsdu:1; 286 u32 rxid_match:1; 287 u32 paggr:1; 288 u32 a1fit:4; /* 16 */ 289 u32 chkerr:1; 290 u32 ipver:1; 291 u32 tcpudp:1; 292 u32 chkvld:1; 293 u32 pam:1; 294 u32 pwr:1; 295 u32 more_data:1; 296 u32 more_frag:1; 297 u32 type:2; 298 u32 mc:1; 299 u32 bc:1; 300 301 u32 seq:12; 302 u32 frag:4; 303 u32 rx_is_qos:1; /* 16 */ 304 u32 dummy2_0:1; 305 u32 wlanhd_iv_len:6; 306 u32 dummy2_1:4; 307 u32 rpt_sel:1; 308 u32 dummy2_2:3; 309 310 u32 rxmcs:7; 311 u32 dummy3_0:3; 312 u32 htc:1; 313 u32 eosp:1; 314 u32 bssidfit:2; 315 u32 dummy3_1:2; 316 u32 usb_agg_pktnum:8; /* 16 */ 317 u32 dummy3_2:5; 318 u32 pattern_match:1; 319 u32 unicast_match:1; 320 u32 magic_match:1; 321 322 u32 splcp:1; 323 u32 ldcp:1; 324 u32 stbc:1; 325 u32 dummy4_0:1; 326 u32 bw:2; 327 u32 dummy4_1:26; 328#else 329 u32 own:1; 330 u32 eor:1; 331 u32 fs:1; 332 u32 ls:1; 333 u32 swdec:1; 334 u32 phy_stats:1; 335 u32 shift:2; 336 u32 qos:1; 337 u32 security:3; 338 u32 drvinfo_sz:4; 339 u32 icverr:1; 340 u32 crc32:1; 341 u32 pktlen:14; 342 343 u32 bc:1; 344 u32 mc:1; 345 u32 type:2; 346 u32 mf:1; 347 u32 md:1; 348 u32 pwr:1; 349 u32 pam:1; 350 u32 a2fit:4; 351 u32 a1fit:4; 352 u32 faggr:1; 353 u32 paggr:1; 354 u32 amsdu:1; 355 u32 hwrsvd:4; 356 u32 tid:4; 357 u32 macid:5; 358 359 u32 dummy2_2:3; 360 u32 rpt_sel:1; 361 u32 dummy2_1:4; 362 u32 wlanhd_iv_len:6; 363 u32 dummy2_0:1; 364 u32 rx_is_qos:1; 365 u32 frag:4; /* 16 */ 366 u32 seq:12; 367 368 u32 magic_match:1; 369 u32 unicast_match:1; 370 u32 pattern_match:1; 371 u32 dummy3_2:5; 372 u32 usb_agg_pktnum:8; 373 u32 dummy3_1:2; /* 16 */ 374 u32 bssidfit:2; 375 u32 eosp:1; 376 u32 htc:1; 377 u32 dummy3_0:3; 378 u32 rxmcs:7; 379 380 u32 dumm4_1:26; 381 u32 bw:2; 382 u32 dummy4_0:1; 383 u32 stbc:1; 384 u32 ldcp:1; 385 u32 splcp:1; 386#endif 387 u32 tsfl; 388}; 389 390struct rtl8xxxu_txdesc32 { 391 __le16 pkt_size; 392 u8 pkt_offset; 393 u8 txdw0; 394 __le32 txdw1; 395 __le32 txdw2; 396 __le32 txdw3; 397 __le32 txdw4; 398 __le32 txdw5; 399 __le32 txdw6; 400 __le16 csum; 401 __le16 txdw7; 402}; 403 404struct rtl8xxxu_txdesc40 { 405 __le16 pkt_size; 406 u8 pkt_offset; 407 u8 txdw0; 408 __le32 txdw1; 409 __le32 txdw2; 410 __le32 txdw3; 411 __le32 txdw4; 412 __le32 txdw5; 413 __le32 txdw6; 414 __le16 csum; 415 __le16 txdw7; 416 __le32 txdw8; 417 __le32 txdw9; 418}; 419 420/* CCK Rates, TxHT = 0 */ 421#define DESC_RATE_1M 0x00 422#define DESC_RATE_2M 0x01 423#define DESC_RATE_5_5M 0x02 424#define DESC_RATE_11M 0x03 425 426/* OFDM Rates, TxHT = 0 */ 427#define DESC_RATE_6M 0x04 428#define DESC_RATE_9M 0x05 429#define DESC_RATE_12M 0x06 430#define DESC_RATE_18M 0x07 431#define DESC_RATE_24M 0x08 432#define DESC_RATE_36M 0x09 433#define DESC_RATE_48M 0x0a 434#define DESC_RATE_54M 0x0b 435 436/* MCS Rates, TxHT = 1 */ 437#define DESC_RATE_MCS0 0x0c 438#define DESC_RATE_MCS1 0x0d 439#define DESC_RATE_MCS2 0x0e 440#define DESC_RATE_MCS3 0x0f 441#define DESC_RATE_MCS4 0x10 442#define DESC_RATE_MCS5 0x11 443#define DESC_RATE_MCS6 0x12 444#define DESC_RATE_MCS7 0x13 445#define DESC_RATE_MCS8 0x14 446#define DESC_RATE_MCS9 0x15 447#define DESC_RATE_MCS10 0x16 448#define DESC_RATE_MCS11 0x17 449#define DESC_RATE_MCS12 0x18 450#define DESC_RATE_MCS13 0x19 451#define DESC_RATE_MCS14 0x1a 452#define DESC_RATE_MCS15 0x1b 453#define DESC_RATE_MCS15_SG 0x1c 454#define DESC_RATE_MCS32 0x20 455 456#define TXDESC_OFFSET_SZ 0 457#define TXDESC_OFFSET_SHT 16 458#if 0 459#define TXDESC_BMC BIT(24) 460#define TXDESC_LSG BIT(26) 461#define TXDESC_FSG BIT(27) 462#define TXDESC_OWN BIT(31) 463#else 464#define TXDESC_BROADMULTICAST BIT(0) 465#define TXDESC_HTC BIT(1) 466#define TXDESC_LAST_SEGMENT BIT(2) 467#define TXDESC_FIRST_SEGMENT BIT(3) 468#define TXDESC_LINIP BIT(4) 469#define TXDESC_NO_ACM BIT(5) 470#define TXDESC_GF BIT(6) 471#define TXDESC_OWN BIT(7) 472#endif 473 474/* Word 1 */ 475/* 476 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are 477 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. 478 */ 479#define TXDESC_PKT_OFFSET_SZ 0 480#define TXDESC32_AGG_ENABLE BIT(5) 481#define TXDESC32_AGG_BREAK BIT(6) 482#define TXDESC40_MACID_SHIFT 0 483#define TXDESC40_MACID_MASK 0x00f0 484#define TXDESC_QUEUE_SHIFT 8 485#define TXDESC_QUEUE_MASK 0x1f00 486#define TXDESC_QUEUE_BK 0x2 487#define TXDESC_QUEUE_BE 0x0 488#define TXDESC_QUEUE_VI 0x5 489#define TXDESC_QUEUE_VO 0x7 490#define TXDESC_QUEUE_BEACON 0x10 491#define TXDESC_QUEUE_HIGH 0x11 492#define TXDESC_QUEUE_MGNT 0x12 493#define TXDESC_QUEUE_CMD 0x13 494#define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) 495#define TXDESC40_RDG_NAV_EXT BIT(13) 496#define TXDESC40_LSIG_TXOP_ENABLE BIT(14) 497#define TXDESC40_PIFS BIT(15) 498 499#define DESC_RATE_ID_SHIFT 16 500#define DESC_RATE_ID_MASK 0xf 501#define TXDESC_NAVUSEHDR BIT(20) 502#define TXDESC_EN_DESC_ID BIT(21) 503#define TXDESC_SEC_RC4 0x00400000 504#define TXDESC_SEC_AES 0x00c00000 505#define TXDESC_PKT_OFFSET_SHIFT 26 506#define TXDESC_AGG_EN BIT(29) 507#define TXDESC_HWPC BIT(31) 508 509/* Word 2 */ 510#define TXDESC40_PAID_SHIFT 0 511#define TXDESC40_PAID_MASK 0x1ff 512#define TXDESC40_CCA_RTS_SHIFT 10 513#define TXDESC40_CCA_RTS_MASK 0xc00 514#define TXDESC40_AGG_ENABLE BIT(12) 515#define TXDESC40_RDG_ENABLE BIT(13) 516#define TXDESC40_AGG_BREAK BIT(16) 517#define TXDESC40_MORE_FRAG BIT(17) 518#define TXDESC40_RAW BIT(18) 519#define TXDESC32_ACK_REPORT BIT(19) 520#define TXDESC40_SPE_RPT BIT(19) 521#define TXDESC_AMPDU_DENSITY_SHIFT 20 522#define TXDESC40_BT_INT BIT(23) 523#define TXDESC40_GID_SHIFT 24 524#define TXDESC_ANTENNA_SELECT_A BIT(24) 525#define TXDESC_ANTENNA_SELECT_B BIT(25) 526 527/* Word 3 */ 528#define TXDESC40_USE_DRIVER_RATE BIT(8) 529#define TXDESC40_CTS_SELF_ENABLE BIT(11) 530#define TXDESC40_RTS_CTS_ENABLE BIT(12) 531#define TXDESC40_HW_RTS_ENABLE BIT(13) 532#define TXDESC32_SEQ_SHIFT 16 533#define TXDESC32_SEQ_MASK 0x0fff0000 534 535/* Word 4 */ 536#define TXDESC32_RTS_RATE_SHIFT 0 537#define TXDESC32_RTS_RATE_MASK 0x3f 538#define TXDESC32_QOS BIT(6) 539#define TXDESC32_HW_SEQ_ENABLE BIT(7) 540#define TXDESC32_USE_DRIVER_RATE BIT(8) 541#define TXDESC_DISABLE_DATA_FB BIT(10) 542#define TXDESC32_CTS_SELF_ENABLE BIT(11) 543#define TXDESC32_RTS_CTS_ENABLE BIT(12) 544#define TXDESC32_HW_RTS_ENABLE BIT(13) 545#define TXDESC32_PT_STAGE_MASK GENMASK(17, 15) 546#define TXDESC_PRIME_CH_OFF_LOWER BIT(20) 547#define TXDESC_PRIME_CH_OFF_UPPER BIT(21) 548#define TXDESC32_SHORT_PREAMBLE BIT(24) 549#define TXDESC_DATA_BW BIT(25) 550#define TXDESC_RTS_DATA_BW BIT(27) 551#define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) 552#define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) 553#define TXDESC40_DATA_RATE_FB_SHIFT 8 554#define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 555#define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) 556#define TXDESC40_RETRY_LIMIT_SHIFT 18 557#define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 558#define TXDESC40_RTS_RATE_SHIFT 24 559#define TXDESC40_RTS_RATE_MASK 0x3f000000 560 561/* Word 5 */ 562#define TXDESC40_SHORT_PREAMBLE BIT(4) 563#define TXDESC32_SHORT_GI BIT(6) 564#define TXDESC_CCX_TAG BIT(7) 565#define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) 566#define TXDESC32_RETRY_LIMIT_SHIFT 18 567#define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 568 569/* Word 6 */ 570#define TXDESC_MAX_AGG_SHIFT 11 571#define TXDESC_USB_TX_AGG_SHIT 24 572 573/* Word 7 */ 574#define TXDESC_ANTENNA_SELECT_C BIT(29) 575 576/* Word 8 */ 577#define TXDESC40_HW_SEQ_ENABLE BIT(15) 578 579/* Word 9 */ 580#define TXDESC40_SEQ_SHIFT 12 581#define TXDESC40_SEQ_MASK 0x00fff000 582 583struct phy_rx_agc_info { 584#ifdef __LITTLE_ENDIAN 585 u8 gain:7, trsw:1; 586#else 587 u8 trsw:1, gain:7; 588#endif 589}; 590 591#define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5) 592#define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0) 593 594struct rtl8723au_phy_stats { 595 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; 596 u8 ch_corr[RTL8723A_MAX_RF_PATHS]; 597 u8 cck_sig_qual_ofdm_pwdb_all; 598 u8 cck_agc_rpt_ofdm_cfosho_a; 599 u8 cck_rpt_b_ofdm_cfosho_b; 600 u8 reserved_1; 601 u8 noise_power_db_msb; 602 s8 path_cfotail[RTL8723A_MAX_RF_PATHS]; 603 u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; 604 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; 605 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; 606 u8 noise_power_db_lsb; 607 u8 reserved_2[3]; 608 u8 stream_csi[RTL8723A_MAX_RF_PATHS]; 609 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; 610 s8 sig_evm; 611 u8 reserved_3; 612 613#ifdef __LITTLE_ENDIAN 614 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 615 u8 sgi_en:1; 616 u8 rxsc:2; 617 u8 idle_long:1; 618 u8 r_ant_train_en:1; 619 u8 antenna_select_b:1; 620 u8 antenna_select:1; 621#else /* _BIG_ENDIAN_ */ 622 u8 antenna_select:1; 623 u8 antenna_select_b:1; 624 u8 r_ant_train_en:1; 625 u8 idle_long:1; 626 u8 rxsc:2; 627 u8 sgi_en:1; 628 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 629#endif 630}; 631 632struct jaguar2_phy_stats_type0 { 633 /* DW0 */ 634 u8 page_num; 635 u8 pwdb; 636#ifdef __LITTLE_ENDIAN 637 u8 gain: 6; 638 u8 rsvd_0: 1; 639 u8 trsw: 1; 640#else 641 u8 trsw: 1; 642 u8 rsvd_0: 1; 643 u8 gain: 6; 644#endif 645 u8 rsvd_1; 646 647 /* DW1 */ 648 u8 rsvd_2; 649#ifdef __LITTLE_ENDIAN 650 u8 rxsc: 4; 651 u8 agc_table: 4; 652#else 653 u8 agc_table: 4; 654 u8 rxsc: 4; 655#endif 656 u8 channel; 657 u8 band; 658 659 /* DW2 */ 660 u16 length; 661#ifdef __LITTLE_ENDIAN 662 u8 antidx_a: 3; 663 u8 antidx_b: 3; 664 u8 rsvd_3: 2; 665 u8 antidx_c: 3; 666 u8 antidx_d: 3; 667 u8 rsvd_4:2; 668#else 669 u8 rsvd_3: 2; 670 u8 antidx_b: 3; 671 u8 antidx_a: 3; 672 u8 rsvd_4:2; 673 u8 antidx_d: 3; 674 u8 antidx_c: 3; 675#endif 676 677 /* DW3 */ 678 u8 signal_quality; 679#ifdef __LITTLE_ENDIAN 680 u8 vga:5; 681 u8 lna_l:3; 682 u8 bb_power:6; 683 u8 rsvd_9:1; 684 u8 lna_h:1; 685#else 686 u8 lna_l:3; 687 u8 vga:5; 688 u8 lna_h:1; 689 u8 rsvd_9:1; 690 u8 bb_power:6; 691#endif 692 u8 rsvd_5; 693 694 /* DW4 */ 695 u32 rsvd_6; 696 697 /* DW5 */ 698 u32 rsvd_7; 699 700 /* DW6 */ 701 u32 rsvd_8; 702} __packed; 703 704struct jaguar2_phy_stats_type1 { 705 /* DW0 and DW1 */ 706 u8 page_num; 707 u8 pwdb[4]; 708#ifdef __LITTLE_ENDIAN 709 u8 l_rxsc: 4; 710 u8 ht_rxsc: 4; 711#else 712 u8 ht_rxsc: 4; 713 u8 l_rxsc: 4; 714#endif 715 u8 channel; 716#ifdef __LITTLE_ENDIAN 717 u8 band: 2; 718 u8 rsvd_0: 1; 719 u8 hw_antsw_occu: 1; 720 u8 gnt_bt: 1; 721 u8 ldpc: 1; 722 u8 stbc: 1; 723 u8 beamformed: 1; 724#else 725 u8 beamformed: 1; 726 u8 stbc: 1; 727 u8 ldpc: 1; 728 u8 gnt_bt: 1; 729 u8 hw_antsw_occu: 1; 730 u8 rsvd_0: 1; 731 u8 band: 2; 732#endif 733 734 /* DW2 */ 735 u16 lsig_length; 736#ifdef __LITTLE_ENDIAN 737 u8 antidx_a: 3; 738 u8 antidx_b: 3; 739 u8 rsvd_1: 2; 740 u8 antidx_c: 3; 741 u8 antidx_d: 3; 742 u8 rsvd_2: 2; 743#else 744 u8 rsvd_1: 2; 745 u8 antidx_b: 3; 746 u8 antidx_a: 3; 747 u8 rsvd_2: 2; 748 u8 antidx_d: 3; 749 u8 antidx_c: 3; 750#endif 751 752 /* DW3 */ 753 u8 paid; 754#ifdef __LITTLE_ENDIAN 755 u8 paid_msb: 1; 756 u8 gid: 6; 757 u8 rsvd_3: 1; 758#else 759 u8 rsvd_3: 1; 760 u8 gid: 6; 761 u8 paid_msb: 1; 762#endif 763 u8 intf_pos; 764#ifdef __LITTLE_ENDIAN 765 u8 intf_pos_msb: 1; 766 u8 rsvd_4: 2; 767 u8 nb_intf_flag: 1; 768 u8 rf_mode: 2; 769 u8 rsvd_5: 2; 770#else 771 u8 rsvd_5: 2; 772 u8 rf_mode: 2; 773 u8 nb_intf_flag: 1; 774 u8 rsvd_4: 2; 775 u8 intf_pos_msb: 1; 776#endif 777 778 /* DW4 */ 779 s8 rxevm[4]; /* s(8,1) */ 780 781 /* DW5 */ 782 s8 cfo_tail[4]; /* s(8,7) */ 783 784 /* DW6 */ 785 s8 rxsnr[4]; /* s(8,1) */ 786} __packed; 787 788struct jaguar2_phy_stats_type2 { 789 /* DW0 ane DW1 */ 790 u8 page_num; 791 u8 pwdb[4]; 792#ifdef __LITTLE_ENDIAN 793 u8 l_rxsc: 4; 794 u8 ht_rxsc: 4; 795#else 796 u8 ht_rxsc: 4; 797 u8 l_rxsc: 4; 798#endif 799 u8 channel; 800#ifdef __LITTLE_ENDIAN 801 u8 band: 2; 802 u8 rsvd_0: 1; 803 u8 hw_antsw_occu: 1; 804 u8 gnt_bt: 1; 805 u8 ldpc: 1; 806 u8 stbc: 1; 807 u8 beamformed: 1; 808#else 809 u8 beamformed: 1; 810 u8 stbc: 1; 811 u8 ldpc: 1; 812 u8 gnt_bt: 1; 813 u8 hw_antsw_occu: 1; 814 u8 rsvd_0: 1; 815 u8 band: 2; 816#endif 817 818 /* DW2 */ 819#ifdef __LITTLE_ENDIAN 820 u8 shift_l_map: 6; 821 u8 rsvd_1: 2; 822#else 823 u8 rsvd_1: 2; 824 u8 shift_l_map: 6; 825#endif 826 u8 cnt_pw2cca; 827#ifdef __LITTLE_ENDIAN 828 u8 agc_table_a: 4; 829 u8 agc_table_b: 4; 830 u8 agc_table_c: 4; 831 u8 agc_table_d: 4; 832#else 833 u8 agc_table_b: 4; 834 u8 agc_table_a: 4; 835 u8 agc_table_d: 4; 836 u8 agc_table_c: 4; 837#endif 838 839 /* DW3 ~ DW6*/ 840 u8 cnt_cca2agc_rdy; 841#ifdef __LITTLE_ENDIAN 842 u8 gain_a: 6; 843 u8 rsvd_2: 1; 844 u8 trsw_a: 1; 845 u8 gain_b: 6; 846 u8 rsvd_3: 1; 847 u8 trsw_b: 1; 848 u8 gain_c: 6; 849 u8 rsvd_4: 1; 850 u8 trsw_c: 1; 851 u8 gain_d: 6; 852 u8 rsvd_5: 1; 853 u8 trsw_d: 1; 854 u8 aagc_step_a: 2; 855 u8 aagc_step_b: 2; 856 u8 aagc_step_c: 2; 857 u8 aagc_step_d: 2; 858#else 859 u8 trsw_a: 1; 860 u8 rsvd_2: 1; 861 u8 gain_a: 6; 862 u8 trsw_b: 1; 863 u8 rsvd_3: 1; 864 u8 gain_b: 6; 865 u8 trsw_c: 1; 866 u8 rsvd_4: 1; 867 u8 gain_c: 6; 868 u8 trsw_d: 1; 869 u8 rsvd_5: 1; 870 u8 gain_d: 6; 871 u8 aagc_step_d: 2; 872 u8 aagc_step_c: 2; 873 u8 aagc_step_b: 2; 874 u8 aagc_step_a: 2; 875#endif 876 u8 ht_aagc_gain[4]; 877 u8 dagc_gain[4]; 878#ifdef __LITTLE_ENDIAN 879 u8 counter: 6; 880 u8 rsvd_6: 2; 881 u8 syn_count: 5; 882 u8 rsvd_7:3; 883#else 884 u8 rsvd_6: 2; 885 u8 counter: 6; 886 u8 rsvd_7:3; 887 u8 syn_count: 5; 888#endif 889} __packed; 890 891/* 892 * Regs to backup 893 */ 894#define RTL8XXXU_ADDA_REGS 16 895#define RTL8XXXU_MAC_REGS 4 896#define RTL8XXXU_BB_REGS 9 897 898struct rtl8xxxu_firmware_header { 899 __le16 signature; /* 92C0: test chip; 92C, 900 88C0: test chip; 901 88C1: MP A-cut; 902 92C1: MP A-cut */ 903 u8 category; /* AP/NIC and USB/PCI */ 904 u8 function; 905 906 __le16 major_version; /* FW Version */ 907 u8 minor_version; /* FW Subversion, default 0x00 */ 908 u8 reserved1; 909 910 u8 month; /* Release time Month field */ 911 u8 date; /* Release time Date field */ 912 u8 hour; /* Release time Hour field */ 913 u8 minute; /* Release time Minute field */ 914 915 __le16 ramcodesize; /* Size of RAM code */ 916 u16 reserved2; 917 918 __le32 svn_idx; /* SVN entry index */ 919 u32 reserved3; 920 921 u32 reserved4; 922 u32 reserved5; 923 924 u8 data[]; 925}; 926 927/* 928 * 8723au/8192cu/8188ru required base power index offset tables. 929 */ 930struct rtl8xxxu_power_base { 931 u32 reg_0e00; 932 u32 reg_0e04; 933 u32 reg_0e08; 934 u32 reg_086c; 935 936 u32 reg_0e10; 937 u32 reg_0e14; 938 u32 reg_0e18; 939 u32 reg_0e1c; 940 941 u32 reg_0830; 942 u32 reg_0834; 943 u32 reg_0838; 944 u32 reg_086c_2; 945 946 u32 reg_083c; 947 u32 reg_0848; 948 u32 reg_084c; 949 u32 reg_0868; 950}; 951 952/* 953 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 954 */ 955struct rtl8723au_idx { 956#ifdef __LITTLE_ENDIAN 957 int a:4; 958 int b:4; 959#else 960 int b:4; 961 int a:4; 962#endif 963} __attribute__((packed)); 964 965struct rtl8723au_efuse { 966 __le16 rtl_id; 967 u8 res0[0xe]; 968 u8 cck_tx_power_index_A[3]; /* 0x10 */ 969 u8 cck_tx_power_index_B[3]; 970 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ 971 u8 ht40_1s_tx_power_index_B[3]; 972 /* 973 * The following entries are half-bytes split as: 974 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 975 */ 976 struct rtl8723au_idx ht20_tx_power_index_diff[3]; 977 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 978 struct rtl8723au_idx ht40_max_power_offset[3]; 979 struct rtl8723au_idx ht20_max_power_offset[3]; 980 u8 channel_plan; /* 0x28 */ 981 u8 tssi_a; 982 u8 thermal_meter; 983 u8 rf_regulatory; 984 u8 rf_option_2; 985 u8 rf_option_3; 986 u8 rf_option_4; 987 u8 res7; 988 u8 version /* 0x30 */; 989 u8 customer_id_major; 990 u8 customer_id_minor; 991 u8 xtal_k; 992 u8 chipset; /* 0x34 */ 993 u8 res8[0x82]; 994 u8 vid; /* 0xb7 */ 995 u8 res9; 996 u8 pid; /* 0xb9 */ 997 u8 res10[0x0c]; 998 u8 mac_addr[ETH_ALEN]; /* 0xc6 */ 999 u8 res11[2]; 1000 u8 vendor_name[7]; 1001 u8 res12[2]; 1002 u8 device_name[0x29]; /* 0xd7 */ 1003}; 1004 1005struct rtl8192cu_efuse { 1006 __le16 rtl_id; 1007 __le16 hpon; 1008 u8 res0[2]; 1009 __le16 clk; 1010 __le16 testr; 1011 __le16 vid; 1012 __le16 did; 1013 __le16 svid; 1014 __le16 smid; /* 0x10 */ 1015 u8 res1[4]; 1016 u8 mac_addr[ETH_ALEN]; /* 0x16 */ 1017 u8 res2[2]; 1018 u8 vendor_name[7]; 1019 u8 res3[3]; 1020 u8 device_name[0x14]; /* 0x28 */ 1021 u8 res4[0x1e]; /* 0x3c */ 1022 u8 cck_tx_power_index_A[3]; /* 0x5a */ 1023 u8 cck_tx_power_index_B[3]; 1024 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ 1025 u8 ht40_1s_tx_power_index_B[3]; 1026 /* 1027 * The following entries are half-bytes split as: 1028 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1029 */ 1030 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; 1031 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ 1032 struct rtl8723au_idx ofdm_tx_power_index_diff[3]; 1033 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ 1034 struct rtl8723au_idx ht20_max_power_offset[3]; 1035 u8 channel_plan; /* 0x75 */ 1036 u8 tssi_a; 1037 u8 tssi_b; 1038 u8 thermal_meter; /* xtal_k */ /* 0x78 */ 1039 u8 rf_regulatory; 1040 u8 rf_option_2; 1041 u8 rf_option_3; 1042 u8 rf_option_4; 1043 u8 res5[1]; /* 0x7d */ 1044 u8 version; 1045 u8 customer_id; 1046}; 1047 1048struct rtl8723bu_pwr_idx { 1049#ifdef __LITTLE_ENDIAN 1050 int ht20:4; 1051 int ht40:4; 1052 int ofdm:4; 1053 int cck:4; 1054#else 1055 int cck:4; 1056 int ofdm:4; 1057 int ht40:4; 1058 int ht20:4; 1059#endif 1060} __attribute__((packed)); 1061 1062struct rtl8723bu_efuse_tx_power { 1063 u8 cck_base[6]; 1064 u8 ht40_base[5]; 1065 struct rtl8723au_idx ht20_ofdm_1s_diff; 1066 struct rtl8723bu_pwr_idx pwr_diff[3]; 1067 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1068}; 1069 1070struct rtl8723bu_efuse { 1071 __le16 rtl_id; 1072 u8 res0[0x0e]; 1073 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1074 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1075 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ 1076 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ 1077 u8 channel_plan; /* 0xb8 */ 1078 u8 xtal_k; 1079 u8 thermal_meter; 1080 u8 iqk_lck; 1081 u8 pa_type; /* 0xbc */ 1082 u8 lna_type_2g; /* 0xbd */ 1083 u8 res2[3]; 1084 u8 rf_board_option; 1085 u8 rf_feature_option; 1086 u8 rf_bt_setting; 1087 u8 eeprom_version; 1088 u8 eeprom_customer_id; 1089 u8 res3[2]; 1090 u8 tx_pwr_calibrate_rate; 1091 u8 rf_antenna_option; /* 0xc9 */ 1092 u8 rfe_option; 1093 u8 res4[9]; 1094 u8 usb_optional_function; 1095 u8 res5[0x1e]; 1096 u8 res6[2]; 1097 u8 serial[0x0b]; /* 0xf5 */ 1098 u8 vid; /* 0x100 */ 1099 u8 res7; 1100 u8 pid; 1101 u8 res8[4]; 1102 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1103 u8 res9[2]; 1104 u8 vendor_name[0x07]; 1105 u8 res10[2]; 1106 u8 device_name[0x14]; 1107 u8 res11[0xcf]; 1108 u8 package_type; /* 0x1fb */ 1109 u8 res12[0x4]; 1110}; 1111 1112struct rtl8192eu_efuse_tx_power { 1113 u8 cck_base[6]; 1114 u8 ht40_base[5]; 1115 struct rtl8723au_idx ht20_ofdm_1s_diff; 1116 struct rtl8723bu_pwr_idx pwr_diff[3]; 1117 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ 1118}; 1119 1120struct rtl8192eu_efuse { 1121 __le16 rtl_id; 1122 u8 res0[0x0e]; 1123 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1124 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1125 u8 res2[0x54]; 1126 u8 channel_plan; /* 0xb8 */ 1127 u8 xtal_k; 1128 u8 thermal_meter; 1129 u8 iqk_lck; 1130 u8 pa_type; /* 0xbc */ 1131 u8 lna_type_2g; /* 0xbd */ 1132 u8 res3[1]; 1133 u8 lna_type_5g; /* 0xbf */ 1134 u8 res4[1]; 1135 u8 rf_board_option; 1136 u8 rf_feature_option; 1137 u8 rf_bt_setting; 1138 u8 eeprom_version; 1139 u8 eeprom_customer_id; 1140 u8 res5[3]; 1141 u8 rf_antenna_option; /* 0xc9 */ 1142 u8 res6[6]; 1143 u8 vid; /* 0xd0 */ 1144 u8 res7[1]; 1145 u8 pid; /* 0xd2 */ 1146 u8 res8[1]; 1147 u8 usb_optional_function; 1148 u8 res9[2]; 1149 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1150 u8 device_info[80]; 1151 u8 res11[3]; 1152 u8 unknown[0x0d]; /* 0x130 */ 1153 u8 res12[0xc3]; 1154}; 1155 1156struct rtl8188fu_efuse_tx_power { 1157 u8 cck_base[6]; 1158 u8 ht40_base[5]; 1159 /* a: ofdm; b: ht20 */ 1160 struct rtl8723au_idx ht20_ofdm_1s_diff; 1161}; 1162 1163struct rtl8188fu_efuse { 1164 __le16 rtl_id; 1165 u8 res0[0x0e]; 1166 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1167 u8 res1[0x9c]; /* 0x1c */ 1168 u8 channel_plan; /* 0xb8 */ 1169 u8 xtal_k; 1170 u8 thermal_meter; 1171 u8 iqk_lck; 1172 u8 res2[5]; 1173 u8 rf_board_option; 1174 u8 rf_feature_option; 1175 u8 rf_bt_setting; 1176 u8 eeprom_version; 1177 u8 eeprom_customer_id; 1178 u8 res3[2]; 1179 u8 kfree_thermal_k_on; 1180 u8 rf_antenna_option; /* 0xc9 */ 1181 u8 rfe_option; 1182 u8 country_code; 1183 u8 res4[4]; 1184 u8 vid; /* 0xd0 */ 1185 u8 res5[1]; 1186 u8 pid; /* 0xd2 */ 1187 u8 res6[1]; 1188 u8 usb_optional_function; 1189 u8 res7[2]; 1190 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1191 u8 res8[2]; 1192 u8 vendor_name[7]; 1193 u8 res9[2]; 1194 u8 device_name[7]; /* 0xe8 */ 1195 u8 res10[0x41]; 1196 u8 unknown[0x0d]; /* 0x130 */ 1197 u8 res11[0xc3]; 1198}; 1199 1200struct rtl8188eu_efuse { 1201 __le16 rtl_id; 1202 u8 res0[0x0e]; 1203 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1204 u8 res1[0x7e]; /* 0x3a */ 1205 u8 channel_plan; /* 0xb8 */ 1206 u8 xtal_k; 1207 u8 thermal_meter; 1208 u8 iqk_lck; 1209 u8 res2[5]; 1210 u8 rf_board_option; 1211 u8 rf_feature_option; 1212 u8 rf_bt_setting; 1213 u8 eeprom_version; 1214 u8 eeprom_customer_id; 1215 u8 res3[3]; 1216 u8 rf_antenna_option; /* 0xc9 */ 1217 u8 res4[6]; 1218 u8 vid; /* 0xd0 */ 1219 u8 res5[1]; 1220 u8 pid; /* 0xd2 */ 1221 u8 res6[1]; 1222 u8 usb_optional_function; 1223 u8 res7[2]; 1224 u8 mac_addr[ETH_ALEN]; /* 0xd7 */ 1225 u8 res8[2]; 1226 u8 vendor_name[7]; 1227 u8 res9[2]; 1228 u8 device_name[0x0b]; /* 0xe8 */ 1229 u8 res10[2]; 1230 u8 serial[0x0b]; /* 0xf5 */ 1231 u8 res11[0x30]; 1232 u8 unknown[0x0d]; /* 0x130 */ 1233 u8 res12[0xc3]; 1234} __packed; 1235 1236struct rtl8710bu_efuse { 1237 __le16 rtl_id; 1238 u8 res0[0x1e]; 1239 struct rtl8188fu_efuse_tx_power tx_power_index_A; /* 0x20 */ 1240 u8 res1[0x9c]; /* 0x2c */ 1241 u8 channel_plan; /* 0xc8 */ 1242 u8 xtal_k; /* 0xc9 */ 1243 u8 thermal_meter; /* 0xca */ 1244 u8 res2[0x4f]; 1245 u8 mac_addr[ETH_ALEN]; /* 0x11a */ 1246 u8 res3[0x11]; 1247 u8 rf_board_option; /* 0x131 */ 1248 u8 res4[2]; 1249 u8 eeprom_version; /* 0x134 */ 1250 u8 eeprom_customer_id; /* 0x135 */ 1251 u8 res5[5]; 1252 u8 country_code; /* 0x13b */ 1253 u8 res6[0x84]; 1254 u8 vid[2]; /* 0x1c0 */ 1255 u8 pid[2]; /* 0x1c2 */ 1256 u8 res7[0x3c]; 1257} __packed; 1258 1259struct rtl8192fu_efuse { 1260 __le16 rtl_id; 1261 u8 res0[0x0e]; 1262 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ 1263 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ 1264 u8 res2[0x54]; 1265 u8 channel_plan; /* 0xb8 */ 1266 u8 xtal_k; /* 0xb9 */ 1267 u8 thermal_meter; /* 0xba */ 1268 u8 iqk_lck; /* 0xbb */ 1269 u8 pa_type; /* 0xbc */ 1270 u8 lna_type_2g; /* 0xbd */ 1271 u8 res3[1]; 1272 u8 lna_type_5g; /* 0xbf */ 1273 u8 res4[1]; 1274 u8 rf_board_option; /* 0xc1 */ 1275 u8 rf_feature_option; /* 0xc2 */ 1276 u8 rf_bt_setting; /* 0xc3 */ 1277 u8 eeprom_version; /* 0xc4 */ 1278 u8 eeprom_customer_id; /* 0xc5 */ 1279 u8 res5[3]; 1280 u8 rf_antenna_option; /* 0xc9 */ 1281 u8 rfe_option; /* 0xca */ 1282 u8 country_code; /* 0xcb */ 1283 u8 res6[52]; 1284 u8 vid[2]; /* 0x100 */ 1285 u8 pid[2]; /* 0x102 */ 1286 u8 usb_optional_function; /* 0x104 */ 1287 u8 res7[2]; 1288 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 1289 u8 device_info[80]; /* 0x10d */ 1290 u8 res9[163]; 1291} __packed; 1292 1293struct rtl8xxxu_reg8val { 1294 u16 reg; 1295 u8 val; 1296}; 1297 1298struct rtl8xxxu_reg32val { 1299 u16 reg; 1300 u32 val; 1301}; 1302 1303struct rtl8xxxu_rfregval { 1304 u8 reg; 1305 u32 val; 1306}; 1307 1308enum rtl8xxxu_rfpath { 1309 RF_A = 0, 1310 RF_B = 1, 1311}; 1312 1313struct rtl8xxxu_rfregs { 1314 u16 hssiparm1; 1315 u16 hssiparm2; 1316 u16 lssiparm; 1317 u16 hspiread; 1318 u16 lssiread; 1319 u16 rf_sw_ctrl; 1320}; 1321 1322#define H2C_MAX_MBOX 4 1323#define H2C_EXT BIT(7) 1324#define H2C_JOIN_BSS_DISCONNECT 0 1325#define H2C_JOIN_BSS_CONNECT 1 1326 1327#define H2C_MACID_ROLE_STA 1 1328#define H2C_MACID_ROLE_AP 2 1329 1330/* 1331 * H2C (firmware) commands differ between the older generation chips 1332 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, 1333 * 8192[de]u, 8192eu, and 8812. 1334 */ 1335enum h2c_cmd_8723a { 1336 H2C_SET_POWER_MODE = 1, 1337 H2C_JOIN_BSS_REPORT = 2, 1338 H2C_SET_RSSI = 5, 1339 H2C_SET_RATE_MASK = (6 | H2C_EXT), 1340}; 1341 1342enum h2c_cmd_8723b { 1343 /* 1344 * Common Class: 000 1345 */ 1346 H2C_8723B_RSVD_PAGE = 0x00, 1347 H2C_8723B_MEDIA_STATUS_RPT = 0x01, 1348 H2C_8723B_SCAN_ENABLE = 0x02, 1349 H2C_8723B_KEEP_ALIVE = 0x03, 1350 H2C_8723B_DISCON_DECISION = 0x04, 1351 H2C_8723B_PSD_OFFLOAD = 0x05, 1352 H2C_8723B_AP_OFFLOAD = 0x08, 1353 H2C_8723B_BCN_RSVDPAGE = 0x09, 1354 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, 1355 H2C_8723B_FCS_RSVDPAGE = 0x10, 1356 H2C_8723B_FCS_INFO = 0x11, 1357 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, 1358 1359 /* 1360 * PoweSave Class: 001 1361 */ 1362 H2C_8723B_SET_PWR_MODE = 0x20, 1363 H2C_8723B_PS_TUNING_PARA = 0x21, 1364 H2C_8723B_PS_TUNING_PARA2 = 0x22, 1365 H2C_8723B_P2P_LPS_PARAM = 0x23, 1366 H2C_8723B_P2P_PS_OFFLOAD = 0x24, 1367 H2C_8723B_PS_SCAN_ENABLE = 0x25, 1368 H2C_8723B_SAP_PS_ = 0x26, 1369 H2C_8723B_INACTIVE_PS_ = 0x27, 1370 H2C_8723B_FWLPS_IN_IPS_ = 0x28, 1371 1372 /* 1373 * Dynamic Mechanism Class: 010 1374 */ 1375 H2C_8723B_MACID_CFG_RAID = 0x40, 1376 H2C_8723B_TXBF = 0x41, 1377 H2C_8723B_RSSI_SETTING = 0x42, 1378 H2C_8723B_AP_REQ_TXRPT = 0x43, 1379 H2C_8723B_INIT_RATE_COLLECT = 0x44, 1380 1381 /* 1382 * BT Class: 011 1383 */ 1384 H2C_8723B_B_TYPE_TDMA = 0x60, 1385 H2C_8723B_BT_INFO = 0x61, 1386 H2C_8723B_FORCE_BT_TXPWR = 0x62, 1387 H2C_8723B_BT_IGNORE_WLANACT = 0x63, 1388 H2C_8723B_DAC_SWING_VALUE = 0x64, 1389 H2C_8723B_ANT_SEL_RSV = 0x65, 1390 H2C_8723B_WL_OPMODE = 0x66, 1391 H2C_8723B_BT_MP_OPER = 0x67, 1392 H2C_8723B_BT_CONTROL = 0x68, 1393 H2C_8723B_BT_WIFI_CTRL = 0x69, 1394 H2C_8723B_BT_FW_PATCH = 0x6a, 1395 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, 1396 H2C_8723B_BT_GRANT = 0x6e, 1397 1398 /* 1399 * WOWLAN Class: 100 1400 */ 1401 H2C_8723B_WOWLAN = 0x80, 1402 H2C_8723B_REMOTE_WAKE_CTRL = 0x81, 1403 H2C_8723B_AOAC_GLOBAL_INFO = 0x82, 1404 H2C_8723B_AOAC_RSVD_PAGE = 0x83, 1405 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, 1406 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, 1407 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, 1408 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, 1409 1410 H2C_8723B_RESET_TSF = 0xC0, 1411}; 1412 1413 1414struct h2c_cmd { 1415 union { 1416 struct { 1417 u8 cmd; 1418 u8 data[7]; 1419 } __packed cmd; 1420 struct { 1421 __le32 data; 1422 __le16 ext; 1423 } __packed raw; 1424 struct { 1425 __le32 data; 1426 __le32 ext; 1427 } __packed raw_wide; 1428 struct { 1429 u8 cmd; 1430 u8 data; 1431 } __packed joinbss; 1432 struct { 1433 u8 cmd; 1434 __le16 mask_hi; 1435 u8 arg; 1436 __le16 mask_lo; 1437 } __packed ramask; 1438 struct { 1439 u8 cmd; 1440 u8 parm; 1441 u8 macid; 1442 u8 macid_end; 1443 } __packed media_status_rpt; 1444 struct { 1445 u8 cmd; 1446 u8 macid; 1447 /* 1448 * [0:4] - RAID 1449 * [7] - SGI 1450 */ 1451 u8 data1; 1452 /* 1453 * [0:1] - Bandwidth 1454 * [3] - No Update 1455 * [4:5] - VHT enable 1456 * [6] - DISPT 1457 * [7] - DISRA 1458 */ 1459 u8 data2; 1460 u8 ramask0; 1461 u8 ramask1; 1462 u8 ramask2; 1463 u8 ramask3; 1464 } __packed b_macid_cfg; 1465 struct { 1466 u8 cmd; 1467 u8 data1; 1468 u8 data2; 1469 u8 data3; 1470 u8 data4; 1471 u8 data5; 1472 } __packed b_type_dma; 1473 struct { 1474 u8 cmd; 1475 u8 data; 1476 } __packed bt_info; 1477 struct { 1478 u8 cmd; 1479 u8 operreq; 1480 u8 opcode; 1481 u8 data; 1482 u8 addr; 1483 } __packed bt_mp_oper; 1484 struct { 1485 u8 cmd; 1486 u8 data; 1487 } __packed bt_wlan_calibration; 1488 struct { 1489 u8 cmd; 1490 u8 data; 1491 } __packed ignore_wlan; 1492 struct { 1493 u8 cmd; 1494 u8 ant_inverse; 1495 u8 int_switch_type; 1496 } __packed ant_sel_rsv; 1497 struct { 1498 u8 cmd; 1499 u8 data; 1500 } __packed bt_grant; 1501 struct { 1502 u8 cmd; 1503 u8 macid; 1504 u8 unknown0; 1505 u8 rssi; 1506 /* 1507 * [0] - is_rx 1508 * [1] - stbc_en 1509 * [2] - noisy_decision 1510 * [6] - bf_en 1511 */ 1512 u8 data; 1513 /* 1514 * [0:6] - ra_th_offset 1515 * [7] - ra_offset_direction 1516 */ 1517 u8 ra_th_offset; 1518 u8 unknown1; 1519 u8 unknown2; 1520 } __packed rssi_report; 1521 }; 1522}; 1523 1524enum c2h_evt_8723b { 1525 C2H_8723B_DEBUG = 0, 1526 C2H_8723B_TSF = 1, 1527 C2H_8723B_AP_RPT_RSP = 2, 1528 C2H_8723B_CCX_TX_RPT = 3, 1529 C2H_8723B_BT_RSSI = 4, 1530 C2H_8723B_BT_OP_MODE = 5, 1531 C2H_8723B_EXT_RA_RPT = 6, 1532 C2H_8723B_BT_INFO = 9, 1533 C2H_8723B_HW_INFO_EXCH = 0x0a, 1534 C2H_8723B_BT_MP_INFO = 0x0b, 1535 C2H_8723B_RA_REPORT = 0x0c, 1536 C2H_8723B_FW_DEBUG = 0xff, 1537}; 1538 1539enum bt_info_src_8723b { 1540 BT_INFO_SRC_8723B_WIFI_FW = 0x0, 1541 BT_INFO_SRC_8723B_BT_RSP = 0x1, 1542 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, 1543}; 1544 1545enum bt_mp_oper_opcode_8723b { 1546 BT_MP_OP_GET_BT_VERSION = 0x00, 1547 BT_MP_OP_RESET = 0x01, 1548 BT_MP_OP_TEST_CTRL = 0x02, 1549 BT_MP_OP_SET_BT_MODE = 0x03, 1550 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, 1551 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, 1552 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, 1553 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, 1554 BT_MP_OP_SET_PKT_HEADER = 0x08, 1555 BT_MP_OP_SET_WHITENCOEFF = 0x09, 1556 BT_MP_OP_SET_BD_ADDR_L = 0x0a, 1557 BT_MP_OP_SET_BD_ADDR_H = 0x0b, 1558 BT_MP_OP_WRITE_REG_ADDR = 0x0c, 1559 BT_MP_OP_WRITE_REG_VALUE = 0x0d, 1560 BT_MP_OP_GET_BT_STATUS = 0x0e, 1561 BT_MP_OP_GET_BD_ADDR_L = 0x0f, 1562 BT_MP_OP_GET_BD_ADDR_H = 0x10, 1563 BT_MP_OP_READ_REG = 0x11, 1564 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, 1565 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, 1566 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, 1567 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, 1568 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, 1569 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, 1570 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, 1571 BT_MP_OP_GET_RSSI = 0x19, 1572 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, 1573 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, 1574 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, 1575 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, 1576 BT_MP_OP_GET_AFH_MAP_L = 0x1e, 1577 BT_MP_OP_GET_AFH_MAP_M = 0x1f, 1578 BT_MP_OP_GET_AFH_MAP_H = 0x20, 1579 BT_MP_OP_GET_AFH_STATUS = 0x21, 1580 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, 1581 BT_MP_OP_SET_THERMAL_METER = 0x23, 1582 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, 1583}; 1584 1585enum rtl8xxxu_bw_mode { 1586 RTL8XXXU_CHANNEL_WIDTH_20 = 0, 1587 RTL8XXXU_CHANNEL_WIDTH_40 = 1, 1588 RTL8XXXU_CHANNEL_WIDTH_80 = 2, 1589 RTL8XXXU_CHANNEL_WIDTH_160 = 3, 1590 RTL8XXXU_CHANNEL_WIDTH_80_80 = 4, 1591 RTL8XXXU_CHANNEL_WIDTH_MAX = 5, 1592}; 1593 1594struct rtl8723bu_c2h { 1595 u8 id; 1596 u8 seq; 1597 union { 1598 struct { 1599 u8 payload[0]; 1600 } __packed raw; 1601 struct { 1602 u8 ext_id; 1603 u8 status:4; 1604 u8 retlen:4; 1605 u8 opcode_ver:4; 1606 u8 req_num:4; 1607 u8 payload[2]; 1608 } __packed bt_mp_info; 1609 struct { 1610 u8 response_source:4; 1611 u8 dummy0_0:4; 1612 1613 u8 bt_info; 1614 1615 u8 retry_count:4; 1616 u8 dummy2_0:1; 1617 u8 bt_page:1; 1618 u8 tx_rx_mask:1; 1619 u8 dummy2_2:1; 1620 1621 u8 rssi; 1622 1623 u8 basic_rate:1; 1624 u8 bt_has_reset:1; 1625 u8 dummy4_1:1; 1626 u8 ignore_wlan:1; 1627 u8 auto_report:1; 1628 u8 dummy4_2:3; 1629 1630 u8 a4; 1631 u8 a5; 1632 } __packed bt_info; 1633 struct { 1634 u8 rate:7; 1635 u8 sgi:1; 1636 u8 macid; 1637 u8 ldpc:1; 1638 u8 txbf:1; 1639 u8 noisy_state:1; 1640 u8 dummy2_0:5; 1641 u8 dummy3_0; 1642 u8 dummy4_0; 1643 u8 dummy5_0; 1644 u8 bw; 1645 } __packed ra_report; 1646 }; 1647} __packed; 1648 1649struct rtl8xxxu_fileops; 1650 1651/*mlme related.*/ 1652enum wireless_mode { 1653 WIRELESS_MODE_UNKNOWN = 0, 1654 /* Sub-Element */ 1655 WIRELESS_MODE_B = BIT(0), 1656 WIRELESS_MODE_G = BIT(1), 1657 WIRELESS_MODE_A = BIT(2), 1658 WIRELESS_MODE_N_24G = BIT(3), 1659 WIRELESS_MODE_N_5G = BIT(4), 1660 WIRELESS_AUTO = BIT(5), 1661 WIRELESS_MODE_AC = BIT(6), 1662 WIRELESS_MODE_MAX = 0x7F, 1663}; 1664 1665/* from rtlwifi/wifi.h */ 1666enum ratr_table_mode_new { 1667 RATEID_IDX_BGN_40M_2SS = 0, 1668 RATEID_IDX_BGN_40M_1SS = 1, 1669 RATEID_IDX_BGN_20M_2SS_BN = 2, 1670 RATEID_IDX_BGN_20M_1SS_BN = 3, 1671 RATEID_IDX_GN_N2SS = 4, 1672 RATEID_IDX_GN_N1SS = 5, 1673 RATEID_IDX_BG = 6, 1674 RATEID_IDX_G = 7, 1675 RATEID_IDX_B = 8, 1676 RATEID_IDX_VHT_2SS = 9, 1677 RATEID_IDX_VHT_1SS = 10, 1678 RATEID_IDX_MIX1 = 11, 1679 RATEID_IDX_MIX2 = 12, 1680 RATEID_IDX_VHT_3SS = 13, 1681 RATEID_IDX_BGN_3SS = 14, 1682}; 1683 1684#define BT_INFO_8723B_1ANT_B_FTP BIT(7) 1685#define BT_INFO_8723B_1ANT_B_A2DP BIT(6) 1686#define BT_INFO_8723B_1ANT_B_HID BIT(5) 1687#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4) 1688#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3) 1689#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2) 1690#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1) 1691#define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0) 1692 1693enum _BT_8723B_1ANT_STATUS { 1694 BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE = 0x0, 1695 BT_8723B_1ANT_STATUS_CONNECTED_IDLE = 0x1, 1696 BT_8723B_1ANT_STATUS_INQ_PAGE = 0x2, 1697 BT_8723B_1ANT_STATUS_ACL_BUSY = 0x3, 1698 BT_8723B_1ANT_STATUS_SCO_BUSY = 0x4, 1699 BT_8723B_1ANT_STATUS_ACL_SCO_BUSY = 0x5, 1700 BT_8723B_1ANT_STATUS_MAX 1701}; 1702 1703struct rtl8xxxu_btcoex { 1704 u8 bt_status; 1705 bool bt_busy; 1706 bool has_sco; 1707 bool has_a2dp; 1708 bool has_hid; 1709 bool has_pan; 1710 bool hid_only; 1711 bool a2dp_only; 1712 bool c2h_bt_inquiry; 1713}; 1714 1715#define RTL8XXXU_RATR_STA_INIT 0 1716#define RTL8XXXU_RATR_STA_HIGH 1 1717#define RTL8XXXU_RATR_STA_MID 2 1718#define RTL8XXXU_RATR_STA_LOW 3 1719 1720#define RTL8XXXU_NOISE_FLOOR_MIN -100 1721#define RTL8XXXU_SNR_THRESH_HIGH 50 1722#define RTL8XXXU_SNR_THRESH_LOW 20 1723 1724struct rtl8xxxu_ra_report { 1725 struct rate_info txrate; 1726 u32 bit_rate; 1727 u8 desc_rate; 1728}; 1729 1730struct rtl8xxxu_ra_info { 1731 u8 rate_id; 1732 u32 rate_mask; 1733 u32 ra_use_rate; 1734 u8 rate_sgi; 1735 u8 rssi_sta_ra; /* Percentage */ 1736 u8 pre_rssi_sta_ra; 1737 u8 sgi_enable; 1738 u8 decision_rate; 1739 u8 pre_rate; 1740 u8 highest_rate; 1741 u8 lowest_rate; 1742 u32 nsc_up; 1743 u32 nsc_down; 1744 u32 total; 1745 u16 retry[5]; 1746 u16 drop; 1747 u16 rpt_time; 1748 u16 pre_min_rpt_time; 1749 u8 dynamic_tx_rpt_timing_counter; 1750 u8 ra_waiting_counter; 1751 u8 ra_pending_counter; 1752 u8 ra_drop_after_down; 1753 u8 pt_try_state; /* 0 trying state, 1 for decision state */ 1754 u8 pt_stage; /* 0~6 */ 1755 u8 pt_stop_count; /* Stop PT counter */ 1756 u8 pt_pre_rate; /* if rate change do PT */ 1757 u8 pt_pre_rssi; /* if RSSI change 5% do PT */ 1758 u8 pt_mode_ss; /* decide which rate should do PT */ 1759 u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ 1760 u8 pt_smooth_factor; 1761}; 1762 1763#define CFO_TH_XTAL_HIGH 20 /* kHz */ 1764#define CFO_TH_XTAL_LOW 10 /* kHz */ 1765#define CFO_TH_ATC 80 /* kHz */ 1766 1767struct rtl8xxxu_cfo_tracking { 1768 bool adjust; 1769 bool atc_status; 1770 int cfo_tail[2]; 1771 u8 crystal_cap; 1772 u32 packet_count; 1773 u32 packet_count_pre; 1774}; 1775 1776#define RTL8XXXU_HW_LED_CONTROL 2 1777#define RTL8XXXU_MAX_MAC_ID_NUM 128 1778#define RTL8XXXU_BC_MC_MACID 0 1779#define RTL8XXXU_BC_MC_MACID1 1 1780#define RTL8XXXU_MAX_SEC_CAM_NUM 64 1781 1782struct rtl8xxxu_priv { 1783 struct ieee80211_hw *hw; 1784 struct usb_device *udev; 1785 struct rtl8xxxu_fileops *fops; 1786 1787 spinlock_t tx_urb_lock; 1788 struct list_head tx_urb_free_list; 1789 int tx_urb_free_count; 1790 bool tx_stopped; 1791 1792 spinlock_t rx_urb_lock; 1793 struct list_head rx_urb_pending_list; 1794 int rx_urb_pending_count; 1795 bool shutdown; 1796 struct work_struct rx_urb_wq; 1797 1798 u8 mac_addr[ETH_ALEN]; 1799 char chip_name[8]; 1800 char chip_vendor[8]; 1801 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1802 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1803 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1804 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; 1805 /* 1806 * The following entries are half-bytes split as: 1807 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed 1808 */ 1809 struct rtl8723au_idx ht40_2s_tx_power_index_diff[ 1810 RTL8723A_CHANNEL_GROUPS]; 1811 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1812 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; 1813 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1814 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; 1815 /* 1816 * Newer generation chips only keep power diffs per TX count, 1817 * not per channel group. 1818 */ 1819 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; 1820 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; 1821 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; 1822 struct rtl8xxxu_power_base *power_base; 1823 u8 package_type; 1824 u32 chip_cut:4; 1825 u32 rom_rev:4; 1826 u32 is_multi_func:1; 1827 u32 has_wifi:1; 1828 u32 has_bluetooth:1; 1829 u32 enable_bluetooth:1; 1830 u32 has_gps:1; 1831 u32 hi_pa:1; 1832 u32 vendor_umc:1; 1833 u32 vendor_smic:1; 1834 u32 has_polarity_ctrl:1; 1835 u32 has_eeprom:1; 1836 u32 boot_eeprom:1; 1837 u32 usb_interrupts:1; 1838 u32 ep_tx_high_queue:1; 1839 u32 ep_tx_normal_queue:1; 1840 u32 ep_tx_low_queue:1; 1841 u32 rx_buf_aggregation:1; 1842 u32 cck_agc_report_type:1; 1843 u32 cck_new_agc:1; 1844 u8 default_crystal_cap; 1845 u8 rfe_type; 1846 unsigned int pipe_interrupt; 1847 unsigned int pipe_in; 1848 unsigned int pipe_out[TXDESC_QUEUE_MAX]; 1849 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; 1850 u8 ep_tx_count; 1851 u8 rf_paths; 1852 u8 rx_paths; 1853 u8 tx_paths; 1854 u32 rege94; 1855 u32 rege9c; 1856 u32 regeb4; 1857 u32 regebc; 1858 u32 regrcr; 1859 int next_mbox; 1860 int nr_out_eps; 1861 1862 /* Ensure no added or deleted stas while iterating */ 1863 struct mutex sta_mutex; 1864 struct mutex h2c_mutex; 1865 /* Protect the indirect register accesses of RTL8710BU. */ 1866 struct mutex syson_indirect_access_mutex; 1867 1868 struct usb_anchor rx_anchor; 1869 struct usb_anchor tx_anchor; 1870 struct usb_anchor int_anchor; 1871 struct rtl8xxxu_firmware_header *fw_data; 1872 size_t fw_size; 1873 struct mutex usb_buf_mutex; 1874 union { 1875 __le32 val32; 1876 __le16 val16; 1877 u8 val8; 1878 } usb_buf; 1879 union { 1880 u8 raw[EFUSE_MAP_LEN]; 1881 struct rtl8723au_efuse efuse8723; 1882 struct rtl8723bu_efuse efuse8723bu; 1883 struct rtl8192cu_efuse efuse8192; 1884 struct rtl8192eu_efuse efuse8192eu; 1885 struct rtl8188fu_efuse efuse8188fu; 1886 struct rtl8188eu_efuse efuse8188eu; 1887 struct rtl8710bu_efuse efuse8710bu; 1888 struct rtl8192fu_efuse efuse8192fu; 1889 } efuse_wifi; 1890 u32 adda_backup[RTL8XXXU_ADDA_REGS]; 1891 u32 mac_backup[RTL8XXXU_MAC_REGS]; 1892 u32 bb_backup[RTL8XXXU_BB_REGS]; 1893 u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; 1894 enum rtl8xxxu_rtl_chip rtl_chip; 1895 u8 pi_enabled:1; 1896 u8 no_pape:1; 1897 u8 int_buf[USB_INTR_CONTENT_LENGTH]; 1898 DECLARE_BITMAP(tx_aggr_started, IEEE80211_NUM_TIDS); 1899 DECLARE_BITMAP(tid_tx_operational, IEEE80211_NUM_TIDS); 1900 1901 struct ieee80211_vif *vifs[2]; 1902 struct delayed_work ra_watchdog; 1903 struct work_struct c2hcmd_work; 1904 struct sk_buff_head c2hcmd_queue; 1905 struct delayed_work update_beacon_work; 1906 struct rtl8xxxu_btcoex bt_coex; 1907 struct rtl8xxxu_ra_report ra_report; 1908 struct rtl8xxxu_cfo_tracking cfo_tracking; 1909 struct rtl8xxxu_ra_info ra_info; 1910 1911 bool led_registered; 1912 char led_name[32]; 1913 struct led_classdev led_cdev; 1914 DECLARE_BITMAP(mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); 1915 DECLARE_BITMAP(cam_map, RTL8XXXU_MAX_SEC_CAM_NUM); 1916}; 1917 1918DECLARE_EWMA(rssi, 10, 16); 1919 1920struct rtl8xxxu_sta_info { 1921 struct ieee80211_sta *sta; 1922 struct ieee80211_vif *vif; 1923 1924 u8 macid; 1925 struct ewma_rssi avg_rssi; 1926 u8 rssi_level; 1927}; 1928 1929struct rtl8xxxu_vif { 1930 int port_num; 1931 u8 hw_key_idx; 1932}; 1933 1934struct rtl8xxxu_rx_urb { 1935 struct urb urb; 1936 struct ieee80211_hw *hw; 1937 struct list_head list; 1938}; 1939 1940struct rtl8xxxu_tx_urb { 1941 struct urb urb; 1942 struct ieee80211_hw *hw; 1943 struct list_head list; 1944}; 1945 1946struct rtl8xxxu_fileops { 1947 int (*identify_chip) (struct rtl8xxxu_priv *priv); 1948 int (*read_efuse) (struct rtl8xxxu_priv *priv); 1949 int (*parse_efuse) (struct rtl8xxxu_priv *priv); 1950 int (*load_firmware) (struct rtl8xxxu_priv *priv); 1951 int (*power_on) (struct rtl8xxxu_priv *priv); 1952 void (*power_off) (struct rtl8xxxu_priv *priv); 1953 void (*reset_8051) (struct rtl8xxxu_priv *priv); 1954 int (*llt_init) (struct rtl8xxxu_priv *priv); 1955 void (*init_phy_bb) (struct rtl8xxxu_priv *priv); 1956 int (*init_phy_rf) (struct rtl8xxxu_priv *priv); 1957 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); 1958 void (*phy_lc_calibrate) (struct rtl8xxxu_priv *priv); 1959 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); 1960 void (*config_channel) (struct ieee80211_hw *hw); 1961 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); 1962 void (*parse_phystats) (struct rtl8xxxu_priv *priv, 1963 struct ieee80211_rx_status *rx_status, 1964 struct rtl8723au_phy_stats *phy_stats, 1965 u32 rxmcs, struct ieee80211_hdr *hdr, 1966 bool crc_icv_err); 1967 void (*init_aggregation) (struct rtl8xxxu_priv *priv); 1968 void (*init_statistics) (struct rtl8xxxu_priv *priv); 1969 void (*init_burst) (struct rtl8xxxu_priv *priv); 1970 void (*enable_rf) (struct rtl8xxxu_priv *priv); 1971 void (*disable_rf) (struct rtl8xxxu_priv *priv); 1972 void (*usb_quirks) (struct rtl8xxxu_priv *priv); 1973 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, 1974 bool ht40); 1975 void (*update_rate_mask) (struct rtl8xxxu_priv *priv, 1976 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, 1977 u8 macid); 1978 void (*report_connect) (struct rtl8xxxu_priv *priv, 1979 u8 macid, u8 role, bool connect); 1980 void (*report_rssi) (struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 1981 void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 1982 struct ieee80211_tx_info *tx_info, 1983 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 1984 bool short_preamble, bool ampdu_enable, 1985 u32 rts_rate, u8 macid); 1986 void (*set_crystal_cap) (struct rtl8xxxu_priv *priv, u8 crystal_cap); 1987 s8 (*cck_rssi) (struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 1988 int (*led_classdev_brightness_set) (struct led_classdev *led_cdev, 1989 enum led_brightness brightness); 1990 int writeN_block_size; 1991 int rx_agg_buf_size; 1992 char tx_desc_size; 1993 char rx_desc_size; 1994 u8 has_s0s1:1; 1995 u8 has_tx_report:1; 1996 u8 gen2_thermal_meter:1; 1997 u8 needs_full_init:1; 1998 u8 init_reg_rxfltmap:1; 1999 u8 init_reg_pkt_life_time:1; 2000 u8 init_reg_hmtfr:1; 2001 u8 supports_concurrent:1; 2002 u8 ampdu_max_time; 2003 u8 ustime_tsf_edca; 2004 u16 max_aggr_num; 2005 u8 supports_ap:1; 2006 u16 max_macid_num; 2007 u16 max_sec_cam_num; 2008 u32 adda_1t_init; 2009 u32 adda_1t_path_on; 2010 u32 adda_2t_path_on_a; 2011 u32 adda_2t_path_on_b; 2012 u16 trxff_boundary; 2013 u8 pbp_rx; 2014 u8 pbp_tx; 2015 const struct rtl8xxxu_reg8val *mactable; 2016 u8 total_page_num; 2017 u8 page_num_hi; 2018 u8 page_num_lo; 2019 u8 page_num_norm; 2020 u8 last_llt_entry; 2021}; 2022 2023extern int rtl8xxxu_debug; 2024 2025extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; 2026extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; 2027u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); 2028u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); 2029u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); 2030int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); 2031int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); 2032int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); 2033int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 2034int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); 2035int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 2036int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); 2037int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 2038int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); 2039int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, 2040 u32 mask, u32 val); 2041 2042u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, 2043 enum rtl8xxxu_rfpath path, u8 reg); 2044int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, 2045 enum rtl8xxxu_rfpath path, u8 reg, u32 data); 2046int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, 2047 enum rtl8xxxu_rfpath path, u8 reg, 2048 u32 mask, u32 val); 2049void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2050 u32 *backup, int count); 2051void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, 2052 u32 *backup, int count); 2053void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, 2054 const u32 *reg, u32 *backup); 2055void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, 2056 const u32 *reg, u32 *backup); 2057void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, 2058 bool path_a_on); 2059void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, 2060 const u32 *regs, u32 *backup); 2061void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, 2062 int result[][8], int candidate, bool tx_only); 2063void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, 2064 int result[][8], int candidate, bool tx_only); 2065int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, 2066 const struct rtl8xxxu_rfregval *table, 2067 enum rtl8xxxu_rfpath path); 2068int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, 2069 const struct rtl8xxxu_reg32val *array); 2070int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); 2071void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); 2072void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); 2073void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); 2074void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); 2075void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); 2076int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); 2077int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); 2078int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv); 2079void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); 2080int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); 2081void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); 2082void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2083void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv); 2084int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); 2085int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, 2086 struct h2c_cmd *h2c, int len); 2087int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); 2088void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); 2089int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); 2090void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); 2091void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); 2092void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, 2093 int channel, bool ht40); 2094void rtl8188f_channel_to_group(int channel, int *group, int *cck_group); 2095void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, 2096 int channel, bool ht40); 2097void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); 2098void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); 2099void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); 2100void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); 2101void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, 2102 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2103void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, 2104 u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); 2105void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, 2106 u8 macid, u8 role, bool connect); 2107void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, 2108 u8 macid, u8 role, bool connect); 2109void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2110void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); 2111void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); 2112void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); 2113void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); 2114void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); 2115void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); 2116int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2117int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2118void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2119 struct ieee80211_rx_status *rx_status, 2120 struct rtl8723au_phy_stats *phy_stats, 2121 u32 rxmcs, struct ieee80211_hdr *hdr, 2122 bool crc_icv_err); 2123void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, 2124 struct ieee80211_rx_status *rx_status, 2125 struct rtl8723au_phy_stats *phy_stats, 2126 u32 rxmcs, struct ieee80211_hdr *hdr, 2127 bool crc_icv_err); 2128int rtl8xxxu_gen2_channel_to_group(int channel); 2129bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, 2130 int result[][8], int c1, int c2); 2131bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, 2132 int result[][8], int c1, int c2); 2133void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2134 struct ieee80211_tx_info *tx_info, 2135 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, 2136 bool short_preamble, bool ampdu_enable, 2137 u32 rts_rate, u8 macid); 2138void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2139 struct ieee80211_tx_info *tx_info, 2140 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2141 bool short_preamble, bool ampdu_enable, 2142 u32 rts_rate, u8 macid); 2143void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, 2144 struct ieee80211_tx_info *tx_info, 2145 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, 2146 bool short_preamble, bool ampdu_enable, 2147 u32 rts_rate, u8 macid); 2148void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, 2149 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); 2150void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); 2151void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2152void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); 2153s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); 2154void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, 2155 u8 rate, u8 sgi, u8 bw); 2156void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); 2157void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); 2158 2159extern struct rtl8xxxu_fileops rtl8192fu_fops; 2160extern struct rtl8xxxu_fileops rtl8710bu_fops; 2161extern struct rtl8xxxu_fileops rtl8188fu_fops; 2162extern struct rtl8xxxu_fileops rtl8188eu_fops; 2163extern struct rtl8xxxu_fileops rtl8192cu_fops; 2164extern struct rtl8xxxu_fileops rtl8192eu_fops; 2165extern struct rtl8xxxu_fileops rtl8723au_fops; 2166extern struct rtl8xxxu_fileops rtl8723bu_fops; 2167