1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 4 * 5 * Register definitions taken from original Realtek rtl8723au driver 6 */ 7 8/* 0x0000 ~ 0x00FF System Configuration */ 9#define REG_SYS_ISO_CTRL 0x0000 10#define SYS_ISO_MD2PP BIT(0) 11#define SYS_ISO_ANALOG_IPS BIT(5) 12#define SYS_ISO_DIOR BIT(9) 13#define SYS_ISO_PWC_EV25V BIT(14) 14#define SYS_ISO_PWC_EV12V BIT(15) 15 16#define REG_SYS_FUNC 0x0002 17#define SYS_FUNC_BBRSTB BIT(0) 18#define SYS_FUNC_BB_GLB_RSTN BIT(1) 19#define SYS_FUNC_USBA BIT(2) 20#define SYS_FUNC_UPLL BIT(3) 21#define SYS_FUNC_USBD BIT(4) 22#define SYS_FUNC_DIO_PCIE BIT(5) 23#define SYS_FUNC_PCIEA BIT(6) 24#define SYS_FUNC_PPLL BIT(7) 25#define SYS_FUNC_PCIED BIT(8) 26#define SYS_FUNC_DIOE BIT(9) 27#define SYS_FUNC_CPU_ENABLE BIT(10) 28#define SYS_FUNC_DCORE BIT(11) 29#define SYS_FUNC_ELDR BIT(12) 30#define SYS_FUNC_DIO_RF BIT(13) 31#define SYS_FUNC_HWPDN BIT(14) 32#define SYS_FUNC_MREGEN BIT(15) 33 34#define REG_APS_FSMCO 0x0004 35#define APS_FSMCO_PFM_ALDN BIT(1) 36#define APS_FSMCO_PFM_WOWL BIT(3) 37#define APS_FSMCO_ENABLE_POWERDOWN BIT(4) 38#define APS_FSMCO_MAC_ENABLE BIT(8) 39#define APS_FSMCO_MAC_OFF BIT(9) 40#define APS_FSMCO_SW_LPS BIT(10) 41#define APS_FSMCO_HW_SUSPEND BIT(11) 42#define APS_FSMCO_PCIE BIT(12) 43#define APS_FSMCO_HW_POWERDOWN BIT(15) 44#define APS_FSMCO_WLON_RESET BIT(16) 45 46#define REG_SYS_CLKR 0x0008 47#define SYS_CLK_ANAD16V_ENABLE BIT(0) 48#define SYS_CLK_ANA8M BIT(1) 49#define SYS_CLK_MACSLP BIT(4) 50#define SYS_CLK_LOADER_ENABLE BIT(5) 51#define SYS_CLK_80M_SSC_DISABLE BIT(7) 52#define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) 53#define SYS_CLK_PHY_SSC_RSTB BIT(9) 54#define SYS_CLK_SEC_CLK_ENABLE BIT(10) 55#define SYS_CLK_MAC_CLK_ENABLE BIT(11) 56#define SYS_CLK_ENABLE BIT(12) 57#define SYS_CLK_RING_CLK_ENABLE BIT(13) 58 59#define REG_9346CR 0x000a 60#define EEPROM_BOOT BIT(4) 61#define EEPROM_ENABLE BIT(5) 62 63#define REG_EE_VPD 0x000c 64#define REG_AFE_MISC 0x0010 65#define AFE_MISC_WL_XTAL_CTRL BIT(6) 66 67#define REG_SPS0_CTRL 0x0011 68#define REG_SPS_OCP_CFG 0x0018 69#define REG_8192E_LDOV12_CTRL 0x0014 70#define REG_SYS_SWR_CTRL2 0x0014 71#define REG_RSV_CTRL 0x001c 72#define RSV_CTRL_WLOCK_1C BIT(5) 73#define RSV_CTRL_DIS_PRST BIT(6) 74 75#define REG_RF_CTRL 0x001f 76#define RF_ENABLE BIT(0) 77#define RF_RSTB BIT(1) 78#define RF_SDMRSTB BIT(2) 79 80#define REG_LDOA15_CTRL 0x0020 81#define LDOA15_ENABLE BIT(0) 82#define LDOA15_STANDBY BIT(1) 83#define LDOA15_OBUF BIT(2) 84#define LDOA15_REG_VOS BIT(3) 85#define LDOA15_VOADJ_SHIFT 4 86 87#define REG_LDOV12D_CTRL 0x0021 88#define LDOV12D_ENABLE BIT(0) 89#define LDOV12D_STANDBY BIT(1) 90#define LDOV12D_VADJ_SHIFT 4 91 92#define REG_LDOHCI12_CTRL 0x0022 93 94#define REG_LPLDO_CTRL 0x0023 95#define LPLDO_HSM BIT(2) 96#define LPLDO_LSM_DIS BIT(3) 97 98#define REG_AFE_XTAL_CTRL 0x0024 99#define AFE_XTAL_ENABLE BIT(0) 100#define AFE_XTAL_B_SELECT BIT(1) 101#define AFE_XTAL_GATE_USB BIT(8) 102#define AFE_XTAL_GATE_AFE BIT(11) 103#define AFE_XTAL_RF_GATE BIT(14) 104#define AFE_XTAL_GATE_DIG BIT(17) 105#define AFE_XTAL_BT_GATE BIT(20) 106 107/* 108 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu 109 */ 110#define REG_AFE_PLL_CTRL 0x0028 111#define AFE_PLL_ENABLE BIT(0) 112#define AFE_PLL_320_ENABLE BIT(1) 113#define APE_PLL_FREF_SELECT BIT(2) 114#define AFE_PLL_EDGE_SELECT BIT(3) 115#define AFE_PLL_WDOGB BIT(4) 116#define AFE_PLL_LPF_ENABLE BIT(5) 117 118#define REG_MAC_PHY_CTRL 0x002c 119 120#define REG_EFUSE_CTRL 0x0030 121#define REG_EFUSE_TEST 0x0034 122#define EFUSE_TRPT BIT(7) 123 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 124#define EFUSE_CELL_SEL (BIT(8) | BIT(9)) 125#define EFUSE_LDOE25_ENABLE BIT(31) 126#define EFUSE_SELECT_MASK 0x0300 127#define EFUSE_WIFI_SELECT 0x0000 128#define EFUSE_BT0_SELECT 0x0100 129#define EFUSE_BT1_SELECT 0x0200 130#define EFUSE_BT2_SELECT 0x0300 131 132#define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ 133#define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ 134 135#define REG_PWR_DATA 0x0038 136#define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) 137 138#define REG_CAL_TIMER 0x003c 139#define REG_ACLK_MON 0x003e 140#define REG_GPIO_MUXCFG 0x0040 141#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5) 142#define REG_GPIO_IO_SEL 0x0042 143#define REG_MAC_PINMUX_CFG 0x0043 144#define REG_GPIO_PIN_CTRL 0x0044 145#define REG_GPIO_INTM 0x0048 146#define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) 147 148#define REG_LEDCFG0 0x004c 149#define LEDCFG0_LED0CM GENMASK(2, 0) 150#define LEDCFG0_LED1CM GENMASK(10, 8) 151#define LED_MODE_SW_CTRL 0x0 152#define LED_MODE_TX_OR_RX_EVENTS 0x3 153#define LEDCFG0_LED0SV BIT(3) 154#define LEDCFG0_LED1SV BIT(11) 155#define LED_SW_OFF 0x0 156#define LED_SW_ON 0x1 157#define LEDCFG0_LED0_IO_MODE BIT(7) 158#define LEDCFG0_LED1_IO_MODE BIT(15) 159#define LED_IO_MODE_OUTPUT 0x0 160#define LED_IO_MODE_INPUT 0x1 161#define LEDCFG0_LED2EN BIT(21) 162#define LED_GPIO_DISABLE 0x0 163#define LED_GPIO_ENABLE 0x1 164#define LEDCFG0_DPDT_SELECT BIT(23) 165#define REG_LEDCFG1 0x004d 166#define LEDCFG1_HW_LED_CONTROL BIT(1) 167#define LEDCFG1_LED_DISABLE BIT(7) 168#define REG_LEDCFG2 0x004e 169#define LEDCFG2_HW_LED_CONTROL BIT(1) 170#define LEDCFG2_HW_LED_ENABLE BIT(5) 171#define LEDCFG2_SW_LED_DISABLE BIT(3) 172#define LEDCFG2_SW_LED_CONTROL BIT(5) 173#define LEDCFG2_DPDT_SELECT BIT(7) 174#define REG_LEDCFG3 0x004f 175#define REG_LEDCFG REG_LEDCFG2 176#define REG_FSIMR 0x0050 177#define REG_FSISR 0x0054 178#define REG_HSIMR 0x0058 179#define REG_HSISR 0x005c 180/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 181#define REG_GPIO_PIN_CTRL_2 0x0060 182/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 183#define REG_GPIO_IO_SEL_2 0x0062 184#define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) 185#define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) 186 187/* RTL8723B */ 188#define REG_PAD_CTRL1 0x0064 189#define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) 190 191/* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ 192#define REG_MULTI_FUNC_CTRL 0x0068 193 194#define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW 195 powerdown source */ 196#define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity 197 control */ 198#define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ 199 200#define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW 201 powerdown source */ 202#define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW 203 powerdown source */ 204#define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity 205 control */ 206#define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ 207#define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS 208 RF HW powerdown source */ 209#define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW 210 powerdown source */ 211#define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity 212 control */ 213#define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ 214 215#define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ 216#define REG_LDO_SW_CTRL 0x007c /* 8192eu */ 217 218#define REG_MCU_FW_DL 0x0080 219#define MCU_FW_DL_ENABLE BIT(0) 220#define MCU_FW_DL_READY BIT(1) 221#define MCU_FW_DL_CSUM_REPORT BIT(2) 222#define MCU_MAC_INIT_READY BIT(3) 223#define MCU_BB_INIT_READY BIT(4) 224#define MCU_RF_INIT_READY BIT(5) 225#define MCU_WINT_INIT_READY BIT(6) 226#define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ 227#define MCU_CP_RESET BIT(23) 228 229#define REG_HMBOX_EXT_0 0x0088 230#define REG_HMBOX_EXT_1 0x008a 231#define REG_HMBOX_EXT_2 0x008c 232#define REG_HMBOX_EXT_3 0x008e 233 234#define REG_RSVD_1 0x0097 235 236/* Interrupt registers for 8192e/8723bu/8812 */ 237#define REG_HIMR0 0x00b0 238#define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit 239 of the packet is set */ 240#define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ 241#define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ 242#define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ 243#define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ 244#define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ 245#define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle 246 indication interrupt */ 247#define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ 248#define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ 249#define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & 250 HSISR is true) */ 251#define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt 252 Extension for Win7 */ 253#define IMR0_ATIMEND BIT(12) /* CTWidnow End or 254 ATIM Window End */ 255#define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator 256 (HISR1 & HIMR1 is true) */ 257#define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT 258 Status, Write 1 to clear */ 259#define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT 260 Status, Write 1 to clear */ 261#define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT 262 Status, Write 1 to clear */ 263#define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ 264#define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ 265#define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ 266#define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ 267#define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ 268#define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ 269#define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ 270#define IMR0_ROK BIT(0) /* Receive DMA OK */ 271#define REG_HISR0 0x00b4 272#define REG_HIMR1 0x00b8 273#define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ 274#define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ 275#define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ 276#define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ 277#define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ 278#define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ 279#define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ 280#define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ 281#define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ 282#define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ 283#define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ 284#define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ 285#define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ 286#define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ 287#define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension 288 for Win7 */ 289#define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, 290 write 1 to clear */ 291#define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, 292 write 1 to clear */ 293#define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ 294#define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ 295#define REG_HISR1 0x00bc 296 297/* Host suspend counter on FPGA platform */ 298#define REG_HOST_SUSP_CNT 0x00bc 299/* Efuse access protection for RTL8723 */ 300#define REG_EFUSE_ACCESS 0x00cf 301#define REG_BIST_SCAN 0x00d0 302#define REG_BIST_RPT 0x00d4 303#define REG_BIST_ROM_RPT 0x00d8 304#define REG_RSVD_4 0x00dc 305#define REG_USB_SIE_INTF 0x00e0 306#define REG_PCIE_MIO_INTF 0x00e4 307#define REG_PCIE_MIO_INTD 0x00e8 308#define REG_HPON_FSM 0x00ec 309#define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) 310#define HPON_FSM_BONDING_1T2R BIT(22) 311#define REG_SYS_CFG 0x00f0 312#define SYS_CFG_XCLK_VLD BIT(0) 313#define SYS_CFG_ACLK_VLD BIT(1) 314#define SYS_CFG_UCLK_VLD BIT(2) 315#define SYS_CFG_PCLK_VLD BIT(3) 316#define SYS_CFG_PCIRSTB BIT(4) 317#define SYS_CFG_V15_VLD BIT(5) 318#define SYS_CFG_TRP_B15V_EN BIT(7) 319#define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ 320#define SYS_CFG_SIC_IDLE BIT(8) 321#define SYS_CFG_BD_MAC2 BIT(9) 322#define SYS_CFG_BD_MAC1 BIT(10) 323#define SYS_CFG_IC_MACPHY_MODE BIT(11) 324#define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) 325#define SYS_CFG_BT_FUNC BIT(16) 326#define SYS_CFG_VENDOR_ID BIT(19) 327#define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) 328#define SYS_CFG_VENDOR_ID_TSMC 0 329#define SYS_CFG_VENDOR_ID_SMIC BIT(18) 330#define SYS_CFG_VENDOR_ID_UMC BIT(19) 331#define SYS_CFG_PAD_HWPD_IDN BIT(22) 332#define SYS_CFG_TRP_VAUX_EN BIT(23) 333#define SYS_CFG_TRP_BT_EN BIT(24) 334#define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ 335#define SYS_CFG_BD_PKG_SEL BIT(25) 336#define SYS_CFG_BD_HCI_SEL BIT(26) 337#define SYS_CFG_TYPE_ID BIT(27) 338#define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, 339 1:Test(RLE); 0:MP(RL) */ 340#define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; 341 0:Switching regulator mode*/ 342#define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ 343 344#define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ 345#define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) 346#define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) 347#define GPIO_HCI_SEL (BIT(4) | BIT(5)) 348#define GPIO_PKG_SEL_HCI BIT(6) 349#define GPIO_FEN_GPS BIT(7) 350#define GPIO_FEN_BT BIT(8) 351#define GPIO_FEN_WL BIT(9) 352#define GPIO_FEN_PCI BIT(10) 353#define GPIO_FEN_USB BIT(11) 354#define GPIO_BTRF_HWPDN_N BIT(12) 355#define GPIO_WLRF_HWPDN_N BIT(13) 356#define GPIO_PDN_BT_N BIT(14) 357#define GPIO_PDN_GPS_N BIT(15) 358#define GPIO_BT_CTL_HWPDN BIT(16) 359#define GPIO_GPS_CTL_HWPDN BIT(17) 360#define GPIO_PPHY_SUSB BIT(20) 361#define GPIO_UPHY_SUSB BIT(21) 362#define GPIO_PCI_SUSEN BIT(22) 363#define GPIO_USB_SUSEN BIT(23) 364#define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 365 366#define REG_SYS_CFG2 0x00fc /* 8192eu */ 367 368/* 0x0100 ~ 0x01FF MACTOP General Configuration */ 369#define REG_CR 0x0100 370#define CR_HCI_TXDMA_ENABLE BIT(0) 371#define CR_HCI_RXDMA_ENABLE BIT(1) 372#define CR_TXDMA_ENABLE BIT(2) 373#define CR_RXDMA_ENABLE BIT(3) 374#define CR_PROTOCOL_ENABLE BIT(4) 375#define CR_SCHEDULE_ENABLE BIT(5) 376#define CR_MAC_TX_ENABLE BIT(6) 377#define CR_MAC_RX_ENABLE BIT(7) 378#define CR_SW_BEACON_ENABLE BIT(8) 379#define CR_SECURITY_ENABLE BIT(9) 380#define CR_CALTIMER_ENABLE BIT(10) 381 382/* Media Status Register */ 383#define REG_MSR 0x0102 384#define MSR_LINKTYPE_MASK 0x3 385#define MSR_LINKTYPE_NONE 0x0 386#define MSR_LINKTYPE_ADHOC 0x1 387#define MSR_LINKTYPE_STATION 0x2 388#define MSR_LINKTYPE_AP 0x3 389 390#define REG_PBP 0x0104 391#define PBP_PAGE_SIZE_RX_SHIFT 0 392#define PBP_PAGE_SIZE_TX_SHIFT 4 393#define PBP_PAGE_SIZE_64 0x0 394#define PBP_PAGE_SIZE_128 0x1 395#define PBP_PAGE_SIZE_256 0x2 396#define PBP_PAGE_SIZE_512 0x3 397#define PBP_PAGE_SIZE_1024 0x4 398 399/* 8188eu IOL magic */ 400#define REG_PKT_BUF_ACCESS_CTRL 0x0106 401#define PKT_BUF_ACCESS_CTRL_TX 0x69 402#define PKT_BUF_ACCESS_CTRL_RX 0xa5 403 404#define REG_TRXDMA_CTRL 0x010c 405#define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) 406#define TRXDMA_CTRL_VOQ_SHIFT 4 407#define TRXDMA_CTRL_VIQ_SHIFT 6 408#define TRXDMA_CTRL_BEQ_SHIFT 8 409#define TRXDMA_CTRL_BKQ_SHIFT 10 410#define TRXDMA_CTRL_MGQ_SHIFT 12 411#define TRXDMA_CTRL_HIQ_SHIFT 14 412#define TRXDMA_CTRL_VOQ_SHIFT_8192F 4 413#define TRXDMA_CTRL_VIQ_SHIFT_8192F 7 414#define TRXDMA_CTRL_BEQ_SHIFT_8192F 10 415#define TRXDMA_CTRL_BKQ_SHIFT_8192F 13 416#define TRXDMA_CTRL_MGQ_SHIFT_8192F 16 417#define TRXDMA_CTRL_HIQ_SHIFT_8192F 19 418#define TRXDMA_QUEUE_LOW 1 419#define TRXDMA_QUEUE_NORMAL 2 420#define TRXDMA_QUEUE_HIGH 3 421 422#define REG_TRXFF_BNDY 0x0114 423#define REG_TRXFF_STATUS 0x0118 424#define REG_RXFF_PTR 0x011c 425#define REG_HIMR 0x0120 426#define REG_HISR 0x0124 427#define REG_HIMRE 0x0128 428#define REG_HISRE 0x012c 429#define REG_CPWM 0x012f 430#define REG_FWIMR 0x0130 431#define REG_FWISR 0x0134 432#define REG_FTIMR 0x0138 433#define REG_PKTBUF_DBG_CTRL 0x0140 434#define REG_PKTBUF_DBG_DATA_L 0x0144 435#define REG_PKTBUF_DBG_DATA_H 0x0148 436 437#define REG_TC0_CTRL 0x0150 438#define REG_TC1_CTRL 0x0154 439#define REG_TC2_CTRL 0x0158 440#define REG_TC3_CTRL 0x015c 441#define REG_TC4_CTRL 0x0160 442#define REG_TCUNIT_BASE 0x0164 443#define REG_MBIST_START 0x0174 444#define REG_MBIST_DONE 0x0178 445#define REG_MBIST_FAIL 0x017c 446/* 8188EU */ 447#define REG_32K_CTRL 0x0194 448#define REG_C2HEVT_MSG_NORMAL 0x01a0 449/* 8192EU/8723BU/8812 */ 450#define REG_C2HEVT_CMD_ID_8723B 0x01ae 451#define REG_C2HEVT_CLEAR 0x01af 452#define REG_C2HEVT_MSG_TEST 0x01b8 453#define REG_MCUTST_1 0x01c0 454#define REG_FMTHR 0x01c8 455#define REG_HMTFR 0x01cc 456#define REG_HMBOX_0 0x01d0 457#define REG_HMBOX_1 0x01d4 458#define REG_HMBOX_2 0x01d8 459#define REG_HMBOX_3 0x01dc 460 461#define REG_LLT_INIT 0x01e0 462#define LLT_OP_INACTIVE 0x0 463#define LLT_OP_WRITE (0x1 << 30) 464#define LLT_OP_READ (0x2 << 30) 465#define LLT_OP_MASK (0x3 << 30) 466 467#define REG_BB_ACCESS_CTRL 0x01e8 468#define REG_BB_ACCESS_DATA 0x01ec 469 470#define REG_HMBOX_EXT0_8723B 0x01f0 471#define REG_HMBOX_EXT1_8723B 0x01f4 472#define REG_HMBOX_EXT2_8723B 0x01f8 473#define REG_HMBOX_EXT3_8723B 0x01fc 474 475/* 0x0200 ~ 0x027F TXDMA Configuration */ 476#define REG_RQPN 0x0200 477#define RQPN_HI_PQ_SHIFT 0 478#define RQPN_LO_PQ_SHIFT 8 479#define RQPN_PUB_PQ_SHIFT 16 480#define RQPN_LOAD BIT(31) 481 482#define REG_FIFOPAGE 0x0204 483#define REG_TDECTRL 0x0208 484#define BIT_BCN_VALID BIT(16) 485 486#define REG_DWBCN0_CTRL_8188F REG_TDECTRL 487 488#define REG_TXDMA_OFFSET_CHK 0x020c 489#define TXDMA_OFFSET_DROP_DATA_EN BIT(9) 490#define REG_TXDMA_STATUS 0x0210 491#define REG_RQPN_NPQ 0x0214 492#define RQPN_NPQ_SHIFT 0 493#define RQPN_EPQ_SHIFT 16 494 495#define REG_AUTO_LLT 0x0224 496#define AUTO_LLT_INIT_LLT BIT(16) 497 498#define REG_DWBCN1_CTRL_8723B 0x0228 499#define BIT_SW_BCN_SEL BIT(20) 500 501/* 0x0280 ~ 0x02FF RXDMA Configuration */ 502#define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits 503 8-14: USB DMA timeout 504 15 : Aggregation enable 505 Only seems to be used 506 on 8723bu/8192eu */ 507#define RXDMA_USB_AGG_ENABLE BIT(31) 508#define REG_RXPKT_NUM 0x0284 509#define RXPKT_NUM_RXDMA_IDLE BIT(17) 510#define RXPKT_NUM_RW_RELEASE_EN BIT(18) 511#define REG_RXDMA_STATUS 0x0288 512 513/* Presumably only found on newer chips such as 8723bu */ 514#define REG_RX_DMA_CTRL_8723B 0x0286 515#define REG_RXDMA_PRO_8723B 0x0290 516#define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */ 517#define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */ 518#define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */ 519 520#define REG_EARLY_MODE_CONTROL_8710B 0x02bc 521 522#define REG_RF_BB_CMD_ADDR 0x02c0 523#define REG_RF_BB_CMD_DATA 0x02c4 524 525/* spec version 11 */ 526/* 0x0400 ~ 0x047F Protocol Configuration */ 527/* 8192c, 8192d */ 528#define REG_VOQ_INFO 0x0400 529#define REG_VIQ_INFO 0x0404 530#define REG_BEQ_INFO 0x0408 531#define REG_BKQ_INFO 0x040c 532/* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ 533#define REG_Q0_INFO 0x400 534#define REG_Q1_INFO 0x404 535#define REG_Q2_INFO 0x408 536#define REG_Q3_INFO 0x40c 537 538#define REG_MGQ_INFO 0x0410 539#define REG_HGQ_INFO 0x0414 540#define REG_BCNQ_INFO 0x0418 541 542#define REG_CPU_MGQ_INFORMATION 0x041c 543#define REG_FWHW_TXQ_CTRL 0x0420 544#define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) 545#define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) 546#define EN_BCNQ_DL BIT(22) 547 548#define REG_HWSEQ_CTRL 0x0423 549#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 550#define REG_TXPKTBUF_MGQ_BDNY 0x0425 551#define REG_LIFETIME_EN 0x0426 552#define REG_MULTI_BCNQ_OFFSET 0x0427 553 554#define REG_SPEC_SIFS 0x0428 555#define SPEC_SIFS_CCK_MASK 0x00ff 556#define SPEC_SIFS_CCK_SHIFT 0 557#define SPEC_SIFS_OFDM_MASK 0xff00 558#define SPEC_SIFS_OFDM_SHIFT 8 559 560#define REG_RETRY_LIMIT 0x042a 561#define RETRY_LIMIT_LONG_SHIFT 0 562#define RETRY_LIMIT_LONG_MASK 0x003f 563#define RETRY_LIMIT_SHORT_SHIFT 8 564#define RETRY_LIMIT_SHORT_MASK 0x3f00 565 566#define REG_DARFRC 0x0430 567#define REG_RARFRC 0x0438 568#define REG_RESPONSE_RATE_SET 0x0440 569#define RESPONSE_RATE_BITMAP_ALL 0xfffff 570#define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 571#define RESPONSE_RATE_RRSR_INIT_2G 0x15f 572#define RESPONSE_RATE_RRSR_INIT_5G 0x150 573#define RSR_1M BIT(0) 574#define RSR_2M BIT(1) 575#define RSR_5_5M BIT(2) 576#define RSR_11M BIT(3) 577#define RSR_6M BIT(4) 578#define RSR_9M BIT(5) 579#define RSR_12M BIT(6) 580#define RSR_18M BIT(7) 581#define RSR_24M BIT(8) 582#define RSR_36M BIT(9) 583#define RSR_48M BIT(10) 584#define RSR_54M BIT(11) 585#define RSR_MCS0 BIT(12) 586#define RSR_MCS1 BIT(13) 587#define RSR_MCS2 BIT(14) 588#define RSR_MCS3 BIT(15) 589#define RSR_MCS4 BIT(16) 590#define RSR_MCS5 BIT(17) 591#define RSR_MCS6 BIT(18) 592#define RSR_MCS7 BIT(19) 593#define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ 594#define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ 595#define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ 596 RSR_RSC_LOWER_SUB_CHANNEL) 597#define RSR_ACK_SHORT_PREAMBLE BIT(23) 598 599#define REG_ARFR0 0x0444 600#define REG_ARFR1 0x0448 601#define REG_ARFR2 0x044c 602#define REG_ARFR3 0x0450 603#define REG_CCK_CHECK 0x0454 604#define BIT_BCN_PORT_SEL BIT(5) 605#define REG_AMPDU_MAX_TIME_8723B 0x0456 606#define REG_AGGLEN_LMT 0x0458 607#define REG_AMPDU_MIN_SPACE 0x045c 608#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d 609#define REG_FAST_EDCA_CTRL 0x0460 610#define REG_RD_RESP_PKT_TH 0x0463 611#define REG_INIRTS_RATE_SEL 0x0480 612/* 8723bu */ 613#define REG_DATA_SUBCHANNEL 0x0483 614/* 8723au */ 615#define REG_INIDATA_RATE_SEL 0x0484 616/* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ 617#define REG_MACID_SLEEP_3_8732B 0x0484 618#define REG_MACID_SLEEP_1_8732B 0x0488 619 620#define REG_POWER_STATUS 0x04a4 621#define REG_POWER_STAGE1 0x04b4 622#define REG_POWER_STAGE2 0x04b8 623#define REG_AMPDU_BURST_MODE_8723B 0x04bc 624#define REG_PKT_VO_VI_LIFE_TIME 0x04c0 625#define REG_PKT_BE_BK_LIFE_TIME 0x04c2 626#define REG_STBC_SETTING 0x04c4 627#define REG_QUEUE_CTRL 0x04c6 628#define REG_HT_SINGLE_AMPDU_8723B 0x04c7 629#define HT_SINGLE_AMPDU_ENABLE BIT(7) 630#define REG_PROT_MODE_CTRL 0x04c8 631#define REG_MAX_AGGR_NUM 0x04ca 632#define REG_RTS_MAX_AGGR_NUM 0x04cb 633#define REG_BAR_MODE_CTRL 0x04cc 634#define REG_RA_TRY_RATE_AGG_LMT 0x04cf 635/* MACID_DROP for 8723a */ 636#define REG_MACID_DROP_8732A 0x04d0 637/* EARLY_MODE_CONTROL 8188e */ 638#define REG_EARLY_MODE_CONTROL_8188E 0x04d0 639/* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ 640#define REG_MACID_SLEEP_2_8732B 0x04d0 641#define REG_MACID_SLEEP 0x04d4 642#define REG_NQOS_SEQ 0x04dc 643#define REG_QOS_SEQ 0x04de 644#define REG_NEED_CPU_HANDLE 0x04e0 645#define REG_PKT_LOSE_RPT 0x04e1 646#define REG_PTCL_ERR_STATUS 0x04e2 647#define REG_TX_REPORT_CTRL 0x04ec 648#define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) 649 650#define REG_TX_REPORT_TIME 0x04f0 651#define REG_DUMMY 0x04fc 652 653/* 0x0500 ~ 0x05FF EDCA Configuration */ 654#define REG_EDCA_VO_PARAM 0x0500 655#define REG_EDCA_VI_PARAM 0x0504 656#define REG_EDCA_BE_PARAM 0x0508 657#define REG_EDCA_BK_PARAM 0x050c 658#define EDCA_PARAM_ECW_MIN_SHIFT 8 659#define EDCA_PARAM_ECW_MAX_SHIFT 12 660#define EDCA_PARAM_TXOP_SHIFT 16 661#define REG_BEACON_TCFG 0x0510 662#define REG_PIFS 0x0512 663#define REG_RDG_PIFS 0x0513 664#define REG_SIFS_CCK 0x0514 665#define REG_SIFS_OFDM 0x0516 666#define REG_TSFTR_SYN_OFFSET 0x0518 667#define REG_AGGR_BREAK_TIME 0x051a 668#define REG_SLOT 0x051b 669#define REG_TX_PTCL_CTRL 0x0520 670#define REG_TXPAUSE 0x0522 671#define REG_DIS_TXREQ_CLR 0x0523 672#define REG_RD_CTRL 0x0524 673#define REG_TBTT_PROHIBIT 0x0540 674#define REG_RD_NAV_NXT 0x0544 675#define REG_NAV_PROT_LEN 0x0546 676 677#define REG_BEACON_CTRL 0x0550 678#define REG_BEACON_CTRL_1 0x0551 679#define BEACON_ATIM BIT(0) 680#define BEACON_CTRL_MBSSID BIT(1) 681#define BEACON_CTRL_TX_BEACON_RPT BIT(2) 682#define BEACON_FUNCTION_ENABLE BIT(3) 683#define BEACON_DISABLE_TSF_UPDATE BIT(4) 684 685#define REG_MBID_NUM 0x0552 686#define REG_DUAL_TSF_RST 0x0553 687#define DUAL_TSF_RESET_TSF0 BIT(0) 688#define DUAL_TSF_RESET_TSF1 BIT(1) 689#define DUAL_TSF_RESET_P2P BIT(4) 690#define DUAL_TSF_TX_OK BIT(5) 691 692/* The same as REG_MBSSID_BCN_SPACE */ 693#define REG_BCN_INTERVAL 0x0554 694#define REG_MBSSID_BCN_SPACE 0x0554 695 696#define REG_DRIVER_EARLY_INT 0x0558 697#define DRIVER_EARLY_INT_TIME 5 698 699#define REG_BEACON_DMA_TIME 0x0559 700#define BEACON_DMA_ATIME_INT_TIME 2 701 702#define REG_ATIMWND 0x055a 703#define REG_USTIME_TSF_8723B 0x055c 704#define REG_BCN_MAX_ERR 0x055d 705#define REG_RXTSF_OFFSET_CCK 0x055e 706#define REG_RXTSF_OFFSET_OFDM 0x055f 707#define REG_TSFTR 0x0560 708#define REG_TSFTR1 0x0568 709#define REG_INIT_TSFTR 0x0564 710#define REG_ATIMWND_1 0x0570 711#define REG_PSTIMER 0x0580 712#define REG_TIMER0 0x0584 713#define REG_TIMER1 0x0588 714#define REG_ACM_HW_CTRL 0x05c0 715#define ACM_HW_CTRL_BK BIT(0) 716#define ACM_HW_CTRL_BE BIT(1) 717#define ACM_HW_CTRL_VI BIT(2) 718#define ACM_HW_CTRL_VO BIT(3) 719#define REG_ACM_RST_CTRL 0x05c1 720#define REG_ACMAVG 0x05c2 721#define REG_VO_ADMTIME 0x05c4 722#define REG_VI_ADMTIME 0x05c6 723#define REG_BE_ADMTIME 0x05c8 724#define REG_EDCA_RANDOM_GEN 0x05cc 725#define REG_SCH_TXCMD 0x05d0 726 727/* define REG_FW_TSF_SYNC_CNT 0x04a0 */ 728#define REG_SCH_TX_CMD 0x05f8 729#define REG_FW_RESET_TSF_CNT_1 0x05fc 730#define REG_FW_RESET_TSF_CNT_0 0x05fd 731#define REG_FW_BCN_DIS_CNT 0x05fe 732 733/* 0x0600 ~ 0x07FF WMAC Configuration */ 734#define REG_APSD_CTRL 0x0600 735#define APSD_CTRL_OFF BIT(6) 736#define APSD_CTRL_OFF_STATUS BIT(7) 737#define REG_BW_OPMODE 0x0603 738#define BW_OPMODE_20MHZ BIT(2) 739#define BW_OPMODE_5G BIT(1) 740#define BW_OPMODE_11J BIT(0) 741 742#define REG_TCR 0x0604 743 744/* Receive Configuration Register */ 745#define REG_RCR 0x0608 746#define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ 747#define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ 748#define RCR_ACCEPT_MCAST BIT(2) 749#define RCR_ACCEPT_BCAST BIT(3) 750#define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match 751 packet */ 752#define RCR_ACCEPT_PM BIT(5) /* Accept power management 753 packet */ 754#define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ 755#define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet 756 (Rx beacon, probe rsp) */ 757#define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ 758#define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ 759#define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use 760 REG_RXFLTMAP2 */ 761#define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use 762 REG_RXFLTMAP1 */ 763#define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use 764 REG_RXFLTMAP0 */ 765#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ 766#define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet 767 interrupt */ 768#define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet 769 interrupt */ 770#define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ 771#define RCR_MFBEN BIT(22) 772#define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection 773 function. Search KEYCAM for 774 each rx packet to check if 775 LSIGEN bit is set. */ 776#define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ 777#define RCR_FORCE_ACK BIT(26) 778#define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ 779#define RCR_APPEND_PHYSTAT BIT(28) 780#define RCR_APPEND_ICV BIT(29) 781#define RCR_APPEND_MIC BIT(30) 782#define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ 783 784#define REG_RX_PKT_LIMIT 0x060c 785#define REG_RX_DLK_TIME 0x060d 786#define REG_RX_DRVINFO_SZ 0x060f 787 788#define REG_MACID 0x0610 789#define REG_BSSID 0x0618 790#define REG_MAR 0x0620 791#define REG_MBIDCAMCFG 0x0628 792 793#define REG_USTIME_EDCA 0x0638 794#define REG_MAC_SPEC_SIFS 0x063a 795 796/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 797 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 798#define REG_R2T_SIFS 0x063c 799 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 800#define REG_T2T_SIFS 0x063e 801#define REG_ACKTO 0x0640 802#define REG_CTS2TO 0x0641 803#define REG_EIFS 0x0642 804 805/* WMA, BA, CCX */ 806#define REG_NAV_CTRL 0x0650 807/* In units of 128us */ 808#define REG_NAV_UPPER 0x0652 809#define NAV_UPPER_UNIT 128 810 811#define REG_BACAMCMD 0x0654 812#define REG_BACAMCONTENT 0x0658 813#define REG_LBDLY 0x0660 814#define REG_FWDLY 0x0661 815#define REG_RXERR_RPT 0x0664 816#define REG_WMAC_TRXPTCL_CTL 0x0668 817#define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) 818#define WMAC_TRXPTCL_CTL_BW_20 0 819#define WMAC_TRXPTCL_CTL_BW_40 BIT(7) 820#define WMAC_TRXPTCL_CTL_BW_80 BIT(8) 821 822/* Security */ 823#define REG_CAM_CMD 0x0670 824#define CAM_CMD_POLLING BIT(31) 825#define CAM_CMD_WRITE BIT(16) 826#define CAM_CMD_KEY_SHIFT 3 827#define REG_CAM_WRITE 0x0674 828#define CAM_WRITE_VALID BIT(15) 829#define REG_CAM_READ 0x0678 830#define REG_CAM_DEBUG 0x067c 831#define REG_SECURITY_CFG 0x0680 832#define SEC_CFG_TX_USE_DEFKEY BIT(0) 833#define SEC_CFG_RX_USE_DEFKEY BIT(1) 834#define SEC_CFG_TX_SEC_ENABLE BIT(2) 835#define SEC_CFG_RX_SEC_ENABLE BIT(3) 836#define SEC_CFG_SKBYA2 BIT(4) 837#define SEC_CFG_NO_SKMC BIT(5) 838#define SEC_CFG_TXBC_USE_DEFKEY BIT(6) 839#define SEC_CFG_RXBC_USE_DEFKEY BIT(7) 840 841/* Power */ 842#define REG_WOW_CTRL 0x0690 843#define REG_PSSTATUS 0x0691 844#define REG_PS_RX_INFO 0x0692 845#define REG_LPNAV_CTRL 0x0694 846#define REG_WKFMCAM_CMD 0x0698 847#define REG_WKFMCAM_RWD 0x069c 848 849/* 850 * RX Filters: each bit corresponds to the numerical value of the subtype. 851 * If it is set the subtype frame type is passed. The filter is only used when 852 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit 853 * in the RCR are low. 854 * 855 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set 856 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. 857 */ 858#define REG_RXFLTMAP0 0x06a0 /* Management frames */ 859#define REG_RXFLTMAP1 0x06a2 /* Control frames */ 860#define REG_RXFLTMAP2 0x06a4 /* Data frames */ 861 862#define REG_BCN_PSR_RPT 0x06a8 863#define REG_CALB32K_CTRL 0x06ac 864#define REG_PKT_MON_CTRL 0x06b4 865#define REG_BT_COEX_TABLE1 0x06c0 866#define REG_BT_COEX_TABLE2 0x06c4 867#define REG_BT_COEX_TABLE3 0x06c8 868#define REG_BT_COEX_TABLE4 0x06cc 869#define REG_WMAC_RESP_TXINFO 0x06d8 870 871#define REG_MACID1 0x0700 872#define REG_BSSID1 0x0708 873 874/* 875 * This seems to be 8723bu specific 876 */ 877#define REG_BT_CONTROL_8723BU 0x0764 878#define BT_CONTROL_BT_GRANT BIT(12) 879 880#define REG_PORT_CONTROL_8710B 0x076d 881#define REG_WLAN_ACT_CONTROL_8723B 0x076e 882 883#define REG_FPGA0_RF_MODE 0x0800 884#define FPGA_RF_MODE BIT(0) 885#define FPGA_RF_MODE_JAPAN BIT(1) 886#define FPGA_RF_MODE_CCK BIT(24) 887#define FPGA_RF_MODE_OFDM BIT(25) 888 889#define REG_FPGA0_TX_INFO 0x0804 890#define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) 891#define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) 892#define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) 893#define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) 894#define REG_FPGA0_PSD_FUNC 0x0808 895#define REG_FPGA0_TX_GAIN 0x080c 896#define REG_FPGA0_RF_TIMING1 0x0810 897#define REG_FPGA0_RF_TIMING2 0x0814 898#define REG_FPGA0_POWER_SAVE 0x0818 899#define FPGA0_PS_LOWER_CHANNEL BIT(26) 900#define FPGA0_PS_UPPER_CHANNEL BIT(27) 901 902#define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ 903#define FPGA0_HSSI_PARM1_PI BIT(8) 904#define REG_FPGA0_XA_HSSI_PARM2 0x0824 905#define REG_FPGA0_XB_HSSI_PARM1 0x0828 906#define REG_FPGA0_XB_HSSI_PARM2 0x082c 907#define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 908#define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 909#define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 910#define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ 911#define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) 912#define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) 913 914#define REG_TX_AGC_B_RATE18_06 0x0830 915#define REG_TX_AGC_B_RATE54_24 0x0834 916#define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 917#define REG_TX_AGC_B_MCS03_MCS00 0x083c 918 919#define REG_FPGA0_XA_LSSI_PARM 0x0840 920#define REG_FPGA0_XB_LSSI_PARM 0x0844 921#define FPGA0_LSSI_PARM_ADDR_SHIFT 20 922#define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 923#define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff 924 925#define REG_TX_AGC_B_MCS07_MCS04 0x0848 926#define REG_TX_AGC_B_MCS11_MCS08 0x084c 927 928#define REG_FPGA0_XCD_SWITCH_CTRL 0x085c 929 930#define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ 931#define REG_FPGA0_XB_RF_INT_OE 0x0864 932#define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 933#define FPGA0_INT_OE_ANTENNA_A BIT(8) 934#define FPGA0_INT_OE_ANTENNA_B BIT(9) 935#define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ 936 FPGA0_INT_OE_ANTENNA_B) 937 938#define REG_TX_AGC_B_MCS15_MCS12 0x0868 939#define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c 940 941#define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 942#define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ 943#define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ 944#define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 945#define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ 946#define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ 947#define FPGA0_RF_3WIRE_DATA BIT(0) 948#define FPGA0_RF_3WIRE_CLOC BIT(1) 949#define FPGA0_RF_3WIRE_LOAD BIT(2) 950#define FPGA0_RF_3WIRE_RW BIT(3) 951#define FPGA0_RF_3WIRE_MASK 0xf 952#define FPGA0_RF_RFENV BIT(4) 953#define FPGA0_RF_TRSW BIT(5) /* Useless now */ 954#define FPGA0_RF_TRSWB BIT(6) 955#define FPGA0_RF_ANTSW BIT(8) 956#define FPGA0_RF_ANTSWB BIT(9) 957#define FPGA0_RF_PAPE BIT(10) 958#define FPGA0_RF_PAPE5G BIT(11) 959#define FPGA0_RF_BD_CTRL_SHIFT 16 960 961#define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ 962#define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ 963#define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ 964#define REG_FPGA0_XCD_RF_PARM 0x087c 965#define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ 966#define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ 967#define FPGA0_RF_PARM_RFA_ENABLE BIT(1) 968#define FPGA0_RF_PARM_RFB_ENABLE BIT(17) 969#define FPGA0_RF_PARM_CLK_GATE BIT(31) 970 971#define REG_FPGA0_ANALOG1 0x0880 972#define REG_FPGA0_ANALOG2 0x0884 973#define FPGA0_ANALOG2_20MHZ BIT(10) 974#define REG_FPGA0_ANALOG3 0x0888 975#define REG_FPGA0_ANALOG4 0x088c 976 977#define REG_NHM_TH9_TH10_8723B 0x0890 978#define REG_NHM_TIMER_8723B 0x0894 979#define REG_NHM_TH3_TO_TH0_8723B 0x0898 980#define REG_NHM_TH7_TO_TH4_8723B 0x089c 981 982#define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ 983#define REG_FPGA0_XB_LSSI_READBACK 0x08a4 984#define REG_FPGA0_PSD_REPORT 0x08b4 985#define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ 986#define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ 987 988#define REG_FPGA1_RF_MODE 0x0900 989 990#define REG_FPGA1_TX_INFO 0x090c 991#define FPGA1_TX_ANT_MASK 0x0000000f 992#define FPGA1_TX_ANT_L_MASK 0x000000f0 993#define FPGA1_TX_ANT_NON_HT_MASK 0x00000f00 994#define FPGA1_TX_ANT_HT1_MASK 0x0000f000 995#define FPGA1_TX_ANT_HT2_MASK 0x000f0000 996#define FPGA1_TX_ANT_HT_S1_MASK 0x00f00000 997#define FPGA1_TX_ANT_NON_HT_S1_MASK 0x0f000000 998#define FPGA1_TX_OFDM_TXSC_MASK 0x30000000 999 1000#define REG_ANT_MAPPING1 0x0914 1001#define REG_RFE_OPT 0x0920 1002#define REG_DPDT_CTRL 0x092c /* 8723BU */ 1003#define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ 1004#define REG_RFE_CTRL_ANT_SRC1 0x0934 1005#define REG_RFE_CTRL_ANT_SRC2 0x0938 1006#define REG_RFE_CTRL_ANT_SRC3 0x093c 1007#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ 1008#define REG_RFE_BUFFER 0x0944 /* 8723BU */ 1009#define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ 1010#define REG_RX_DFIR_MOD_97F 0x0948 1011#define REG_OFDM_RX_DFIR 0x954 1012#define REG_RFE_OPT62 0x0968 1013 1014#define REG_CCK0_SYSTEM 0x0a00 1015#define CCK0_SIDEBAND BIT(4) 1016 1017#define REG_CCK0_AFE_SETTING 0x0a04 1018#define CCK0_AFE_RX_MASK 0x0f000000 1019#define CCK0_AFE_TX_MASK 0xf0000000 1020#define CCK0_AFE_RX_ANT_A 0 1021#define CCK0_AFE_RX_ANT_B BIT(26) 1022#define CCK0_AFE_RX_ANT_C BIT(27) 1023#define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27)) 1024#define CCK0_AFE_RX_ANT_OPTION_A 0 1025#define CCK0_AFE_RX_ANT_OPTION_B BIT(24) 1026#define CCK0_AFE_RX_ANT_OPTION_C BIT(25) 1027#define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25)) 1028#define CCK0_AFE_TX_ANT_A BIT(31) 1029#define CCK0_AFE_TX_ANT_B BIT(30) 1030 1031#define REG_CCK_ANTDIV_PARA2 0x0a04 1032#define REG_BB_POWER_SAVE4 0x0a74 1033 1034/* 8188eu */ 1035#define REG_LNA_SWITCH 0x0b2c 1036#define LNA_SWITCH_DISABLE_CSCG BIT(22) 1037#define LNA_SWITCH_OUTPUT_CG BIT(31) 1038 1039#define REG_CCK_PD_THRESH 0x0a0a 1040#define CCK_PD_TYPE1_LV0_TH 0x40 1041#define CCK_PD_TYPE1_LV1_TH 0x83 1042#define CCK_PD_TYPE1_LV2_TH 0xcd 1043#define CCK_PD_TYPE1_LV3_TH 0xdd 1044#define CCK_PD_TYPE1_LV4_TH 0xed 1045 1046#define REG_CCK0_TX_FILTER1 0x0a20 1047#define REG_CCK0_TX_FILTER2 0x0a24 1048#define REG_CCK0_DEBUG_PORT 0x0a28 /* debug port and Tx filter3 */ 1049#define REG_AGC_RPT 0xa80 1050#define AGC_RPT_CCK BIT(7) 1051#define REG_CCK0_TX_FILTER3 0x0aac 1052 1053#define REG_CONFIG_ANT_A 0x0b68 1054#define REG_CONFIG_ANT_B 0x0b6c 1055 1056#define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 1057#define OFDM_RF_PATH_RX_MASK 0x0f 1058#define OFDM_RF_PATH_RX_A BIT(0) 1059#define OFDM_RF_PATH_RX_B BIT(1) 1060#define OFDM_RF_PATH_RX_C BIT(2) 1061#define OFDM_RF_PATH_RX_D BIT(3) 1062#define OFDM_RF_PATH_TX_MASK 0xf0 1063#define OFDM_RF_PATH_TX_A BIT(4) 1064#define OFDM_RF_PATH_TX_B BIT(5) 1065#define OFDM_RF_PATH_TX_C BIT(6) 1066#define OFDM_RF_PATH_TX_D BIT(7) 1067 1068#define REG_OFDM0_TR_MUX_PAR 0x0c08 1069 1070#define REG_OFDM0_FA_RSTC 0x0c0c 1071 1072#define REG_DOWNSAM_FACTOR 0x0c10 1073 1074#define REG_OFDM0_XA_RX_AFE 0x0c10 1075#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 1076#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c 1077 1078#define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c 1079 1080#define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 1081#define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) 1082 1083#define REG_OFDM0_XA_AGC_CORE1 0x0c50 1084#define REG_OFDM0_XA_AGC_CORE2 0x0c54 1085#define REG_OFDM0_XB_AGC_CORE1 0x0c58 1086#define REG_OFDM0_XB_AGC_CORE2 0x0c5c 1087#define REG_OFDM0_XC_AGC_CORE1 0x0c60 1088#define REG_OFDM0_XC_AGC_CORE2 0x0c64 1089#define REG_OFDM0_XD_AGC_CORE1 0x0c68 1090#define REG_OFDM0_XD_AGC_CORE2 0x0c6c 1091#define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F 1092 1093#define REG_OFDM0_AGC_PARM1 0x0c70 1094 1095#define REG_OFDM0_AGC_RSSI_TABLE 0x0c78 1096 1097#define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 1098#define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 1099#define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 1100#define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 1101 1102#define REG_OFDM0_XC_TX_AFE 0x0c94 1103#define REG_OFDM0_XD_TX_AFE 0x0c9c 1104 1105#define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 1106 1107/* 8188eu */ 1108#define REG_ANTDIV_PARA1 0x0ca4 1109 1110#define REG_RXIQB_EXT 0x0ca8 1111 1112/* 8723bu */ 1113#define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 1114 1115#define REG_OFDM1_LSTF 0x0d00 1116#define OFDM_LSTF_PRIME_CH_LOW BIT(10) 1117#define OFDM_LSTF_PRIME_CH_HIGH BIT(11) 1118#define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ 1119 OFDM_LSTF_PRIME_CH_HIGH) 1120#define OFDM_LSTF_CONTINUE_TX BIT(28) 1121#define OFDM_LSTF_SINGLE_CARRIER BIT(29) 1122#define OFDM_LSTF_SINGLE_TONE BIT(30) 1123#define OFDM_LSTF_MASK 0x70000000 1124 1125#define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 1126#define REG_OFDM1_CFO_TRACKING 0x0d2c 1127#define CFO_TRACKING_ATC_STATUS BIT(11) 1128#define REG_OFDM1_CSI_FIX_MASK1 0x0d40 1129#define REG_OFDM1_CSI_FIX_MASK2 0x0d44 1130 1131#define REG_ANAPWR1 0x0d94 1132 1133#define REG_TX_AGC_A_RATE18_06 0x0e00 1134#define REG_TX_AGC_A_RATE54_24 0x0e04 1135#define REG_TX_AGC_A_CCK1_MCS32 0x0e08 1136#define REG_TX_AGC_A_MCS03_MCS00 0x0e10 1137#define REG_TX_AGC_A_MCS07_MCS04 0x0e14 1138#define REG_TX_AGC_A_MCS11_MCS08 0x0e18 1139#define REG_TX_AGC_A_MCS15_MCS12 0x0e1c 1140 1141#define REG_NP_ANTA 0x0e20 1142 1143#define REG_TAP_UPD_97F 0x0e24 1144 1145#define REG_FPGA0_IQK 0x0e28 1146 1147#define REG_TX_IQK_TONE_A 0x0e30 1148#define REG_RX_IQK_TONE_A 0x0e34 1149#define REG_TX_IQK_PI_A 0x0e38 1150#define REG_RX_IQK_PI_A 0x0e3c 1151 1152#define REG_TX_IQK 0x0e40 1153#define REG_RX_IQK 0x0e44 1154#define REG_IQK_AGC_PTS 0x0e48 1155#define REG_IQK_AGC_RSP 0x0e4c 1156#define REG_TX_IQK_TONE_B 0x0e50 1157#define REG_RX_IQK_TONE_B 0x0e54 1158#define REG_TX_IQK_PI_B 0x0e58 1159#define REG_RX_IQK_PI_B 0x0e5c 1160#define REG_IQK_AGC_CONT 0x0e60 1161 1162#define REG_BLUETOOTH 0x0e6c 1163#define REG_RX_WAIT_CCA 0x0e70 1164#define REG_TX_CCK_RFON 0x0e74 1165#define REG_TX_CCK_BBON 0x0e78 1166#define REG_TX_OFDM_RFON 0x0e7c 1167#define REG_TX_OFDM_BBON 0x0e80 1168#define REG_TX_TO_RX 0x0e84 1169#define REG_TX_TO_TX 0x0e88 1170#define REG_RX_CCK 0x0e8c 1171 1172#define REG_TX_POWER_BEFORE_IQK_A 0x0e94 1173#define REG_IQK_RPT_TXA 0x0e98 1174#define REG_TX_POWER_AFTER_IQK_A 0x0e9c 1175 1176#define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 1177#define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 1178#define REG_RX_POWER_AFTER_IQK_A 0x0ea8 1179#define REG_IQK_RPT_RXA 0x0ea8 1180#define REG_RX_POWER_AFTER_IQK_A_2 0x0eac 1181 1182#define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 1183#define REG_IQK_RPT_TXB 0x0eb8 1184#define REG_TX_POWER_AFTER_IQK_B 0x0ebc 1185 1186#define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 1187#define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 1188#define REG_RX_POWER_AFTER_IQK_B 0x0ec8 1189#define REG_IQK_RPT_RXB 0x0ec8 1190#define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc 1191 1192#define REG_RX_OFDM 0x0ed0 1193#define REG_RX_WAIT_RIFS 0x0ed4 1194#define REG_RX_TO_RX 0x0ed8 1195#define REG_STANDBY 0x0edc 1196#define REG_SLEEP 0x0ee0 1197#define REG_PMPD_ANAEN 0x0eec 1198 1199#define REG_FW_START_ADDRESS 0x1000 1200#define REG_FW_START_ADDRESS_8192F 0x4000 1201 1202#define REG_SW_GPIO_SHARE_CTRL_0 0x1038 1203#define REG_SW_GPIO_SHARE_CTRL_1 0x103c 1204#define REG_GPIO_A0 0x1050 1205#define REG_GPIO_B0 0x105b 1206 1207#define REG_USB_INFO 0xfe17 1208#define REG_USB_HIMR 0xfe38 1209#define USB_HIMR_TIMEOUT2 BIT(31) 1210#define USB_HIMR_TIMEOUT1 BIT(30) 1211#define USB_HIMR_PSTIMEOUT BIT(29) 1212#define USB_HIMR_GTINT4 BIT(28) 1213#define USB_HIMR_GTINT3 BIT(27) 1214#define USB_HIMR_TXBCNERR BIT(26) 1215#define USB_HIMR_TXBCNOK BIT(25) 1216#define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) 1217#define USB_HIMR_BCNDMAINT3 BIT(23) 1218#define USB_HIMR_BCNDMAINT2 BIT(22) 1219#define USB_HIMR_BCNDMAINT1 BIT(21) 1220#define USB_HIMR_BCNDMAINT0 BIT(20) 1221#define USB_HIMR_BCNDOK3 BIT(19) 1222#define USB_HIMR_BCNDOK2 BIT(18) 1223#define USB_HIMR_BCNDOK1 BIT(17) 1224#define USB_HIMR_BCNDOK0 BIT(16) 1225#define USB_HIMR_HSISR_IND BIT(15) 1226#define USB_HIMR_BCNDMAINT_E BIT(14) 1227/* RSVD BIT(13) */ 1228#define USB_HIMR_CTW_END BIT(12) 1229/* RSVD BIT(11) */ 1230#define USB_HIMR_C2HCMD BIT(10) 1231#define USB_HIMR_CPWM2 BIT(9) 1232#define USB_HIMR_CPWM BIT(8) 1233#define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK 1234 Interrupt */ 1235#define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK 1236 Interrupt */ 1237#define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ 1238#define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ 1239#define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ 1240#define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ 1241#define USB_HIMR_RDU BIT(1) /* Receive Descriptor 1242 Unavailable */ 1243#define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ 1244 1245#define REG_USB_ACCESS_TIMEOUT 0xfe4c 1246 1247#define REG_USB_SPECIAL_OPTION 0xfe55 1248#define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ 1249#define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to 1250 deliver interrupt packet. 1251 0: Use int, 1: use bulk */ 1252#define REG_USB_HRPWM 0xfe58 1253#define REG_USB_DMA_AGG_TO 0xfe5b 1254#define REG_USB_AGG_TIMEOUT 0xfe5c 1255#define REG_USB_AGG_THRESH 0xfe5d 1256 1257#define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ 1258#define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ 1259#define REG_NORMAL_SIE_OPTIONAL 0xfe64 1260#define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ 1261#define REG_NORMAL_SIE_EP_TX 0xfe66 1262#define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f 1263#define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 1264#define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 1265 1266#define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ 1267#define REG_NORMAL_SIE_OPTIONAL2 0xfe6c 1268#define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ 1269#define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ 1270#define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ 1271 1272/* 1273 * 8710B register addresses between 0x00 and 0xff must have 0x8000 1274 * added to them. We take care of that in the rtl8xxxu_read{8,16,32} 1275 * and rtl8xxxu_write{8,16,32} functions. 1276 */ 1277#define REG_SYS_FUNC_8710B 0x0004 1278#define REG_AFE_CTRL_8710B 0x0050 1279#define REG_WL_RF_PSS_8710B 0x005c 1280#define REG_EFUSE_INDIRECT_CTRL_8710B 0x006c 1281#define NORMAL_REG_READ_OFFSET 0x83000000 1282#define NORMAL_REG_WRITE_OFFSET 0x84000000 1283#define EFUSE_READ_OFFSET 0x85000000 1284#define EFUSE_WRITE_OFFSET 0x86000000 1285#define REG_HIMR0_8710B 0x0080 1286#define REG_HISR0_8710B 0x0084 1287/* 1288 * 8710B uses this instead of REG_MCU_FW_DL, but at least bits 1289 * 0-7 have the same meaning. 1290 */ 1291#define REG_8051FW_CTRL_V1_8710B 0x0090 1292#define REG_USB_HOST_INDIRECT_DATA_8710B 0x009c 1293#define REG_WL_STATUS_8710B 0x00f0 1294#define REG_USB_HOST_INDIRECT_ADDR_8710B 0x00f8 1295 1296/* 1297 * 8710B registers which must be accessed through rtl8710b_read_syson_reg 1298 * and rtl8710b_write_syson_reg. 1299 */ 1300#define SYSON_REG_BASE_ADDR_8710B 0x40000000 1301#define REG_SYS_XTAL_CTRL0_8710B 0x060 1302#define REG_SYS_EEPROM_CTRL0_8710B 0x0e0 1303#define REG_SYS_SYSTEM_CFG0_8710B 0x1f0 1304#define REG_SYS_SYSTEM_CFG1_8710B 0x1f4 1305#define REG_SYS_SYSTEM_CFG2_8710B 0x1f8 1306 1307/* RF6052 registers */ 1308#define RF6052_REG_AC 0x00 1309#define RF6052_REG_IQADJ_G1 0x01 1310#define RF6052_REG_IQADJ_G2 0x02 1311#define RF6052_REG_BS_PA_APSET_G1_G4 0x03 1312#define RF6052_REG_BS_PA_APSET_G5_G8 0x04 1313#define RF6052_REG_POW_TRSW 0x05 1314#define RF6052_REG_GAIN_RX 0x06 1315#define RF6052_REG_GAIN_TX 0x07 1316#define RF6052_REG_TXM_IDAC 0x08 1317#define RF6052_REG_IPA_G 0x09 1318#define RF6052_REG_TXBIAS_G 0x0a 1319#define RF6052_REG_TXPA_AG 0x0b 1320#define RF6052_REG_IPA_A 0x0c 1321#define RF6052_REG_TXBIAS_A 0x0d 1322#define RF6052_REG_BS_PA_APSET_G9_G11 0x0e 1323#define RF6052_REG_BS_IQGEN 0x0f 1324#define RF6052_REG_MODE1 0x10 1325#define RF6052_REG_MODE2 0x11 1326#define RF6052_REG_RX_AGC_HP 0x12 1327#define RF6052_REG_TX_AGC 0x13 1328#define RF6052_REG_BIAS 0x14 1329#define RF6052_REG_IPA 0x15 1330#define RF6052_REG_TXBIAS 0x16 1331#define RF6052_REG_POW_ABILITY 0x17 1332#define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ 1333#define MODE_AG_CHANNEL_MASK 0x3ff 1334#define MODE_AG_CHANNEL_20MHZ BIT(10) 1335#define MODE_AG_BW_MASK (BIT(10) | BIT(11)) 1336#define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) 1337#define MODE_AG_BW_40MHZ_8723B BIT(10) 1338#define MODE_AG_BW_80MHZ_8723B 0 1339 1340#define RF6052_REG_TOP 0x19 1341#define RF6052_REG_RX_G1 0x1a 1342#define RF6052_REG_RX_G2 0x1b 1343#define RF6052_REG_RX_BB2 0x1c 1344#define RF6052_REG_RX_BB1 0x1d 1345#define RF6052_REG_RCK1 0x1e 1346#define RF6052_REG_RCK2 0x1f 1347#define RF6052_REG_TX_G1 0x20 1348#define RF6052_REG_TX_G2 0x21 1349#define RF6052_REG_TX_G3 0x22 1350#define RF6052_REG_TX_BB1 0x23 1351#define RF6052_REG_T_METER 0x24 1352#define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ 1353#define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ 1354#define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ 1355#define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ 1356#define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ 1357#define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ 1358#define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ 1359#define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ 1360 1361#define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ 1362 1363#define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ 1364#define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ 1365#define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ 1366 1367/* 1368 * NextGen regs: 8723BU 1369 */ 1370#define RF6052_REG_GAIN_P1 0x35 1371#define RF6052_REG_T_METER_8723B 0x42 1372#define RF6052_REG_UNKNOWN_43 0x43 1373#define RF6052_REG_UNKNOWN_55 0x55 1374#define RF6052_REG_PAD_TXG 0x56 1375#define RF6052_REG_TXMOD 0x58 1376#define RF6052_REG_RXG_MIX_SWBW 0x87 1377#define RF6052_REG_S0S1 0xb0 1378#define RF6052_REG_GAIN_CCA 0xdf 1379#define RF6052_REG_UNKNOWN_ED 0xed 1380#define RF6052_REG_WE_LUT 0xef 1381#define RF6052_REG_GAIN_CTRL 0xf5 1382