1305100Scy// SPDX-License-Identifier: GPL-2.0-only 2305100Scy/* 3305100Scy * RTL8XXXU mac80211 USB driver - 8723a specific subdriver 4305100Scy * 5305100Scy * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 6305100Scy * 7305100Scy * Portions, notably calibration code: 8305100Scy * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 9305100Scy * 10305100Scy * This driver was written as a replacement for the vendor provided 11305100Scy * rtl8723au driver. As the Realtek 8xxx chips are very similar in 12305100Scy * their programming interface, I have started adding support for 13305100Scy * additional 8xxx chips like the 8192cu, 8188cus, etc. 14305100Scy */ 15305100Scy 16305100Scy#include "regs.h" 17305100Scy#include "rtl8xxxu.h" 18305100Scy 19305100Scystatic struct rtl8xxxu_power_base rtl8723a_power_base = { 20305100Scy .reg_0e00 = 0x0a0c0c0c, 21305100Scy .reg_0e04 = 0x02040608, 22305100Scy .reg_0e08 = 0x00000000, 23305100Scy .reg_086c = 0x00000000, 24305100Scy 25305100Scy .reg_0e10 = 0x0a0c0d0e, 26305100Scy .reg_0e14 = 0x02040608, 27305100Scy .reg_0e18 = 0x0a0c0d0e, 28305100Scy .reg_0e1c = 0x02040608, 29305100Scy 30305100Scy .reg_0830 = 0x0a0c0c0c, 31305100Scy .reg_0834 = 0x02040608, 32305100Scy .reg_0838 = 0x00000000, 33305100Scy .reg_086c_2 = 0x00000000, 34305100Scy 35305100Scy .reg_083c = 0x0a0c0d0e, 36305100Scy .reg_0848 = 0x02040608, 37305100Scy .reg_084c = 0x0a0c0d0e, 38305100Scy .reg_0868 = 0x02040608, 39305100Scy}; 40305100Scy 41305100Scystatic const struct rtl8xxxu_reg8val rtl8723au_mac_init_table[] = { 42305100Scy {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, 43305100Scy {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, 44305100Scy {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, 45305100Scy {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, 46305100Scy {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, 47305100Scy {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, 48305100Scy {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, 49305100Scy {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, 50305100Scy {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, 51305100Scy {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, 52305100Scy {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, 53305100Scy {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, 54305100Scy {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, 55305100Scy {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, 56305100Scy {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, 57305100Scy {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, 58305100Scy {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, 59305100Scy {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, 60305100Scy {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, 61305100Scy {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, 62305100Scy {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, 63305100Scy {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, 64305100Scy}; 65305100Scy 66305100Scystatic const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { 67305100Scy {0x00, 0x00030159}, {0x01, 0x00031284}, 68305100Scy {0x02, 0x00098000}, {0x03, 0x00039c63}, 69305100Scy {0x04, 0x000210e7}, {0x09, 0x0002044f}, 70305100Scy {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, 71305100Scy {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, 72305100Scy {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, 73305100Scy {0x19, 0x00000000}, {0x1a, 0x00030355}, 74305100Scy {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, 75305100Scy {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, 76305100Scy {0x1f, 0x00000000}, {0x20, 0x0000b614}, 77305100Scy {0x21, 0x0006c000}, {0x22, 0x00000000}, 78305100Scy {0x23, 0x00001558}, {0x24, 0x00000060}, 79305100Scy {0x25, 0x00000483}, {0x26, 0x0004f000}, 80305100Scy {0x27, 0x000ec7d9}, {0x28, 0x00057730}, 81305100Scy {0x29, 0x00004783}, {0x2a, 0x00000001}, 82305100Scy {0x2b, 0x00021334}, {0x2a, 0x00000000}, 83305100Scy {0x2b, 0x00000054}, {0x2a, 0x00000001}, 84305100Scy {0x2b, 0x00000808}, {0x2b, 0x00053333}, 85305100Scy {0x2c, 0x0000000c}, {0x2a, 0x00000002}, 86305100Scy {0x2b, 0x00000808}, {0x2b, 0x0005b333}, 87305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000003}, 88305100Scy {0x2b, 0x00000808}, {0x2b, 0x00063333}, 89305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000004}, 90305100Scy {0x2b, 0x00000808}, {0x2b, 0x0006b333}, 91305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000005}, 92305100Scy {0x2b, 0x00000808}, {0x2b, 0x00073333}, 93305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000006}, 94305100Scy {0x2b, 0x00000709}, {0x2b, 0x0005b333}, 95305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000007}, 96305100Scy {0x2b, 0x00000709}, {0x2b, 0x00063333}, 97305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000008}, 98305100Scy {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, 99305100Scy {0x2c, 0x0000000d}, {0x2a, 0x00000009}, 100305100Scy {0x2b, 0x0000060a}, {0x2b, 0x00053333}, 101305100Scy {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, 102305100Scy {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, 103305100Scy {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, 104305100Scy {0x2b, 0x0000060a}, {0x2b, 0x00063333}, 105305100Scy {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, 106305100Scy {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, 107305100Scy {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, 108305100Scy {0x2b, 0x0000060a}, {0x2b, 0x00073333}, 109305100Scy {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, 110305100Scy {0x2b, 0x0000050b}, {0x2b, 0x00066666}, 111305100Scy {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, 112305100Scy {0x10, 0x0004000f}, {0x11, 0x000e31fc}, 113305100Scy {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, 114305100Scy {0x10, 0x0002000f}, {0x11, 0x000203f9}, 115305100Scy {0x10, 0x0003000f}, {0x11, 0x000ff500}, 116305100Scy {0x10, 0x00000000}, {0x11, 0x00000000}, 117305100Scy {0x10, 0x0008000f}, {0x11, 0x0003f100}, 118305100Scy {0x10, 0x0009000f}, {0x11, 0x00023100}, 119305100Scy {0x12, 0x00032000}, {0x12, 0x00071000}, 120305100Scy {0x12, 0x000b0000}, {0x12, 0x000fc000}, 121305100Scy {0x13, 0x000287b3}, {0x13, 0x000244b7}, 122305100Scy {0x13, 0x000204ab}, {0x13, 0x0001c49f}, 123305100Scy {0x13, 0x00018493}, {0x13, 0x0001429b}, 124305100Scy {0x13, 0x00010299}, {0x13, 0x0000c29c}, 125305100Scy {0x13, 0x000081a0}, {0x13, 0x000040ac}, 126305100Scy {0x13, 0x00000020}, {0x14, 0x0001944c}, 127305100Scy {0x14, 0x00059444}, {0x14, 0x0009944c}, 128305100Scy {0x14, 0x000d9444}, {0x15, 0x0000f474}, 129305100Scy {0x15, 0x0004f477}, {0x15, 0x0008f455}, 130305100Scy {0x15, 0x000cf455}, {0x16, 0x00000339}, 131305100Scy {0x16, 0x00040339}, {0x16, 0x00080339}, 132305100Scy {0x16, 0x000c0366}, {0x00, 0x00010159}, 133305100Scy {0x18, 0x0000f401}, {0xfe, 0x00000000}, 134305100Scy {0xfe, 0x00000000}, {0x1f, 0x00000003}, 135305100Scy {0xfe, 0x00000000}, {0xfe, 0x00000000}, 136305100Scy {0x1e, 0x00000247}, {0x1f, 0x00000000}, 137305100Scy {0x00, 0x00030159}, 138305100Scy {0xff, 0xffffffff} 139305100Scy}; 140305100Scy 141305100Scystatic int rtl8723au_identify_chip(struct rtl8xxxu_priv *priv) 142305100Scy{ 143305100Scy struct device *dev = &priv->udev->dev; 144305100Scy u32 val32, sys_cfg, vendor; 145305100Scy int ret = 0; 146305100Scy 147305100Scy sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 148305100Scy priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 149305100Scy if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 150305100Scy dev_info(dev, "Unsupported test chip\n"); 151305100Scy ret = -ENOTSUPP; 152305100Scy goto out; 153305100Scy } 154305100Scy 155305100Scy strscpy(priv->chip_name, "8723AU", sizeof(priv->chip_name)); 156305100Scy priv->usb_interrupts = 1; 157305100Scy priv->rtl_chip = RTL8723A; 158305100Scy 159305100Scy priv->rf_paths = 1; 160305100Scy priv->rx_paths = 1; 161305100Scy priv->tx_paths = 1; 162305100Scy 163305100Scy val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 164305100Scy if (val32 & MULTI_WIFI_FUNC_EN) 165305100Scy priv->has_wifi = 1; 166305100Scy if (val32 & MULTI_BT_FUNC_EN) 167305100Scy priv->has_bluetooth = 1; 168305100Scy if (val32 & MULTI_GPS_FUNC_EN) 169305100Scy priv->has_gps = 1; 170305100Scy priv->is_multi_func = 1; 171305100Scy 172305100Scy vendor = sys_cfg & SYS_CFG_VENDOR_ID; 173305100Scy rtl8xxxu_identify_vendor_1bit(priv, vendor); 174305100Scy 175305100Scy val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 176305100Scy priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 177305100Scy 178305100Scy rtl8xxxu_config_endpoints_sie(priv); 179305100Scy 180305100Scy /* 181305100Scy * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX 182305100Scy */ 183305100Scy if (!priv->ep_tx_count) 184305100Scy ret = rtl8xxxu_config_endpoints_no_sie(priv); 185305100Scy 186305100Scyout: 187305100Scy return ret; 188305100Scy} 189305100Scy 190305100Scystatic int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) 191305100Scy{ 192305100Scy struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723; 193305100Scy 194305100Scy if (efuse->rtl_id != cpu_to_le16(0x8129)) 195305100Scy return -EINVAL; 196305100Scy 197305100Scy ether_addr_copy(priv->mac_addr, efuse->mac_addr); 198305100Scy 199305100Scy memcpy(priv->cck_tx_power_index_A, 200305100Scy efuse->cck_tx_power_index_A, 201305100Scy sizeof(efuse->cck_tx_power_index_A)); 202305100Scy memcpy(priv->cck_tx_power_index_B, 203305100Scy efuse->cck_tx_power_index_B, 204305100Scy sizeof(efuse->cck_tx_power_index_B)); 205305100Scy 206305100Scy memcpy(priv->ht40_1s_tx_power_index_A, 207305100Scy efuse->ht40_1s_tx_power_index_A, 208305100Scy sizeof(efuse->ht40_1s_tx_power_index_A)); 209305100Scy memcpy(priv->ht40_1s_tx_power_index_B, 210305100Scy efuse->ht40_1s_tx_power_index_B, 211305100Scy sizeof(efuse->ht40_1s_tx_power_index_B)); 212305100Scy 213305100Scy memcpy(priv->ht20_tx_power_index_diff, 214305100Scy efuse->ht20_tx_power_index_diff, 215305100Scy sizeof(efuse->ht20_tx_power_index_diff)); 216305100Scy memcpy(priv->ofdm_tx_power_index_diff, 217305100Scy efuse->ofdm_tx_power_index_diff, 218305100Scy sizeof(efuse->ofdm_tx_power_index_diff)); 219305100Scy 220305100Scy memcpy(priv->ht40_max_power_offset, 221305100Scy efuse->ht40_max_power_offset, 222305100Scy sizeof(efuse->ht40_max_power_offset)); 223305100Scy memcpy(priv->ht20_max_power_offset, 224305100Scy efuse->ht20_max_power_offset, 225305100Scy sizeof(efuse->ht20_max_power_offset)); 226305100Scy 227305100Scy if (priv->efuse_wifi.efuse8723.version >= 0x01) 228305100Scy priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; 229305100Scy else 230305100Scy priv->fops->set_crystal_cap = NULL; 231305100Scy 232305100Scy priv->power_base = &rtl8723a_power_base; 233305100Scy 234305100Scy return 0; 235305100Scy} 236305100Scy 237305100Scystatic int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) 238305100Scy{ 239305100Scy const char *fw_name; 240305100Scy int ret; 241305100Scy 242305100Scy switch (priv->chip_cut) { 243305100Scy case 0: 244305100Scy fw_name = "rtlwifi/rtl8723aufw_A.bin"; 245305100Scy break; 246305100Scy case 1: 247305100Scy if (priv->enable_bluetooth) 248305100Scy fw_name = "rtlwifi/rtl8723aufw_B.bin"; 249305100Scy else 250305100Scy fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; 251305100Scy 252305100Scy break; 253305100Scy default: 254305100Scy return -EINVAL; 255305100Scy } 256305100Scy 257305100Scy ret = rtl8xxxu_load_firmware(priv, fw_name); 258305100Scy return ret; 259305100Scy} 260305100Scy 261305100Scystatic int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv) 262305100Scy{ 263305100Scy int ret; 264305100Scy 265305100Scy ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A); 266305100Scy 267305100Scy /* Reduce 80M spur */ 268305100Scy rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); 269305100Scy rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); 270305100Scy rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); 271305100Scy rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); 272305100Scy 273305100Scy return ret; 274305100Scy} 275305100Scy 276305100Scystatic int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv) 277305100Scy{ 278305100Scy u8 val8; 279305100Scy u32 val32; 280305100Scy int count, ret = 0; 281305100Scy 282305100Scy /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ 283305100Scy val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); 284305100Scy val8 |= LDOA15_ENABLE; 285305100Scy rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); 286305100Scy 287305100Scy /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ 288305100Scy val8 = rtl8xxxu_read8(priv, 0x0067); 289305100Scy val8 &= ~BIT(4); 290305100Scy rtl8xxxu_write8(priv, 0x0067, val8); 291305100Scy 292305100Scy mdelay(1); 293305100Scy 294305100Scy /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ 295305100Scy val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); 296305100Scy val8 &= ~SYS_ISO_ANALOG_IPS; 297305100Scy rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); 298305100Scy 299305100Scy /* disable SW LPS 0x04[10]= 0 */ 300305100Scy val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 301305100Scy val8 &= ~BIT(2); 302305100Scy rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 303305100Scy 304305100Scy /* wait till 0x04[17] = 1 power ready*/ 305305100Scy for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 306305100Scy val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 307305100Scy if (val32 & BIT(17)) 308305100Scy break; 309305100Scy 310305100Scy udelay(10); 311305100Scy } 312305100Scy 313305100Scy if (!count) { 314305100Scy ret = -EBUSY; 315305100Scy goto exit; 316305100Scy } 317305100Scy 318305100Scy /* We should be able to optimize the following three entries into one */ 319305100Scy 320305100Scy /* release WLON reset 0x04[16]= 1*/ 321305100Scy val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); 322305100Scy val8 |= BIT(0); 323305100Scy rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); 324305100Scy 325305100Scy /* disable HWPDN 0x04[15]= 0*/ 326305100Scy val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 327305100Scy val8 &= ~BIT(7); 328305100Scy rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 329305100Scy 330305100Scy /* disable WL suspend*/ 331305100Scy val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); 332305100Scy val8 &= ~(BIT(3) | BIT(4)); 333305100Scy rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); 334305100Scy 335305100Scy /* set, then poll until 0 */ 336305100Scy val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 337305100Scy val32 |= APS_FSMCO_MAC_ENABLE; 338305100Scy rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); 339305100Scy 340305100Scy for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 341305100Scy val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 342305100Scy if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { 343305100Scy ret = 0; 344305100Scy break; 345305100Scy } 346305100Scy udelay(10); 347305100Scy } 348305100Scy 349305100Scy if (!count) { 350305100Scy ret = -EBUSY; 351305100Scy goto exit; 352305100Scy } 353305100Scy 354305100Scy /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ 355305100Scy /* 356305100Scy * Note: Vendor driver actually clears this bit, despite the 357305100Scy * documentation claims it's being set! 358305100Scy */ 359305100Scy val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); 360305100Scy val8 |= LEDCFG2_DPDT_SELECT; 361305100Scy val8 &= ~LEDCFG2_DPDT_SELECT; 362305100Scy rtl8xxxu_write8(priv, REG_LEDCFG2, val8); 363305100Scy 364305100Scyexit: 365305100Scy return ret; 366305100Scy} 367305100Scy 368305100Scystatic int rtl8723au_power_on(struct rtl8xxxu_priv *priv) 369305100Scy{ 370305100Scy u8 val8; 371305100Scy u16 val16; 372305100Scy u32 val32; 373305100Scy int ret; 374305100Scy 375305100Scy /* 376305100Scy * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register 377305100Scy */ 378305100Scy rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); 379305100Scy 380305100Scy rtl8xxxu_disabled_to_emu(priv); 381305100Scy 382305100Scy ret = rtl8723a_emu_to_active(priv); 383305100Scy if (ret) 384305100Scy goto exit; 385305100Scy 386305100Scy /* 387305100Scy * 0x0004[19] = 1, reset 8051 388305100Scy */ 389305100Scy val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); 390305100Scy val8 |= BIT(3); 391305100Scy rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); 392305100Scy 393305100Scy /* 394305100Scy * Enable MAC DMA/WMAC/SCHEDULE/SEC block 395305100Scy * Set CR bit10 to enable 32k calibration. 396305100Scy */ 397305100Scy val16 = rtl8xxxu_read16(priv, REG_CR); 398305100Scy val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 399305100Scy CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 400305100Scy CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 401305100Scy CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | 402305100Scy CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); 403305100Scy rtl8xxxu_write16(priv, REG_CR, val16); 404305100Scy 405305100Scy /* For EFuse PG */ 406305100Scy val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); 407305100Scy val32 &= ~(BIT(28) | BIT(29) | BIT(30)); 408305100Scy val32 |= (0x06 << 28); 409305100Scy rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); 410305100Scyexit: 411305100Scy return ret; 412305100Scy} 413305100Scy 414305100Scy#define XTAL1 GENMASK(23, 18) 415305100Scy#define XTAL0 GENMASK(17, 12) 416305100Scy 417305100Scyvoid rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) 418305100Scy{ 419305100Scy struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 420305100Scy u32 val32; 421305100Scy 422305100Scy if (crystal_cap == cfo->crystal_cap) 423305100Scy return; 424305100Scy 425305100Scy val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); 426305100Scy 427305100Scy dev_dbg(&priv->udev->dev, 428305100Scy "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", 429305100Scy __func__, 430305100Scy cfo->crystal_cap, 431305100Scy FIELD_GET(XTAL1, val32), 432305100Scy FIELD_GET(XTAL0, val32), 433305100Scy crystal_cap); 434305100Scy 435305100Scy val32 &= ~(XTAL1 | XTAL0); 436305100Scy val32 |= FIELD_PREP(XTAL1, crystal_cap) | 437305100Scy FIELD_PREP(XTAL0, crystal_cap); 438305100Scy rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); 439305100Scy 440305100Scy cfo->crystal_cap = crystal_cap; 441305100Scy} 442305100Scy 443305100Scys8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) 444305100Scy{ 445305100Scy u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; 446305100Scy s8 rx_pwr_all = 0x00; 447305100Scy 448305100Scy switch (cck_agc_rpt & 0xc0) { 449305100Scy case 0xc0: 450305100Scy rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); 451305100Scy break; 452305100Scy case 0x80: 453305100Scy rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); 454305100Scy break; 455305100Scy case 0x40: 456305100Scy rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); 457305100Scy break; 458305100Scy case 0x00: 459305100Scy rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); 460305100Scy break; 461305100Scy } 462305100Scy 463305100Scy return rx_pwr_all; 464305100Scy} 465305100Scy 466305100Scystatic int rtl8723au_led_brightness_set(struct led_classdev *led_cdev, 467305100Scy enum led_brightness brightness) 468305100Scy{ 469305100Scy struct rtl8xxxu_priv *priv = container_of(led_cdev, 470305100Scy struct rtl8xxxu_priv, 471305100Scy led_cdev); 472305100Scy u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); 473305100Scy 474305100Scy if (brightness == LED_OFF) { 475305100Scy ledcfg &= ~LEDCFG2_HW_LED_CONTROL; 476305100Scy ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; 477305100Scy } else if (brightness == LED_ON) { 478305100Scy ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); 479305100Scy ledcfg |= LEDCFG2_SW_LED_CONTROL; 480305100Scy } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { 481305100Scy ledcfg &= ~LEDCFG2_SW_LED_DISABLE; 482305100Scy ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; 483305100Scy } 484305100Scy 485305100Scy rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); 486305100Scy 487305100Scy return 0; 488305100Scy} 489305100Scy 490305100Scystruct rtl8xxxu_fileops rtl8723au_fops = { 491305100Scy .identify_chip = rtl8723au_identify_chip, 492305100Scy .parse_efuse = rtl8723au_parse_efuse, 493 .load_firmware = rtl8723au_load_firmware, 494 .power_on = rtl8723au_power_on, 495 .power_off = rtl8xxxu_power_off, 496 .read_efuse = rtl8xxxu_read_efuse, 497 .reset_8051 = rtl8xxxu_reset_8051, 498 .llt_init = rtl8xxxu_init_llt_table, 499 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, 500 .init_phy_rf = rtl8723au_init_phy_rf, 501 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, 502 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, 503 .config_channel = rtl8xxxu_gen1_config_channel, 504 .parse_rx_desc = rtl8xxxu_parse_rxdesc16, 505 .parse_phystats = rtl8723au_rx_parse_phystats, 506 .init_aggregation = rtl8xxxu_gen1_init_aggregation, 507 .enable_rf = rtl8xxxu_gen1_enable_rf, 508 .disable_rf = rtl8xxxu_gen1_disable_rf, 509 .usb_quirks = rtl8xxxu_gen1_usb_quirks, 510 .set_tx_power = rtl8xxxu_gen1_set_tx_power, 511 .update_rate_mask = rtl8xxxu_update_rate_mask, 512 .report_connect = rtl8xxxu_gen1_report_connect, 513 .report_rssi = rtl8xxxu_gen1_report_rssi, 514 .fill_txdesc = rtl8xxxu_fill_txdesc_v1, 515 .set_crystal_cap = rtl8723a_set_crystal_cap, 516 .cck_rssi = rtl8723a_cck_rssi, 517 .led_classdev_brightness_set = rtl8723au_led_brightness_set, 518 .writeN_block_size = 1024, 519 .rx_agg_buf_size = 16000, 520 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), 521 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), 522 .max_sec_cam_num = 32, 523 .adda_1t_init = 0x0b1b25a0, 524 .adda_1t_path_on = 0x0bdb25a0, 525 .adda_2t_path_on_a = 0x04db25a4, 526 .adda_2t_path_on_b = 0x0b1b25a4, 527 .trxff_boundary = 0x27ff, 528 .pbp_rx = PBP_PAGE_SIZE_128, 529 .pbp_tx = PBP_PAGE_SIZE_128, 530 .mactable = rtl8723au_mac_init_table, 531 .total_page_num = TX_TOTAL_PAGE_NUM, 532 .page_num_hi = TX_PAGE_NUM_HI_PQ, 533 .page_num_lo = TX_PAGE_NUM_LO_PQ, 534 .page_num_norm = TX_PAGE_NUM_NORM_PQ, 535}; 536