1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * RTL8XXXU mac80211 USB driver - 8192fu specific subdriver 4 * 5 * Copyright (c) 2023 Bitterblue Smith <rtl8821cerfe2@gmail.com> 6 * 7 * Portions copied from existing rtl8xxxu code: 8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com> 9 * 10 * Portions, notably calibration code: 11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 12 */ 13 14#include "regs.h" 15#include "rtl8xxxu.h" 16 17static const struct rtl8xxxu_reg8val rtl8192f_mac_init_table[] = { 18 {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10}, 19 {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, 20 {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, 21 {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08}, 22 {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, 23 {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00}, 24 {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10}, 25 {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00}, 26 {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20}, 27 {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e}, 28 {0x4a0, 0x00}, {0x4a1, 0x00}, {0x4a2, 0x00}, {0x4a3, 0x00}, 29 {0x4a4, 0x15}, {0x4a5, 0xf0}, {0x4a6, 0x01}, {0x4a7, 0x0e}, 30 {0x4a8, 0xe0}, {0x4a9, 0x00}, {0x4aa, 0x00}, {0x4ab, 0x00}, 31 {0x2448, 0x06}, {0x244a, 0x06}, {0x244c, 0x06}, {0x244e, 0x06}, 32 {0x4c7, 0x80}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4ca, 0x3c}, 33 {0x4cb, 0x3c}, {0x4cc, 0xff}, {0x4cd, 0xff}, {0x4ce, 0x01}, 34 {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, {0x503, 0x00}, 35 {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, {0x507, 0x00}, 36 {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, {0x50b, 0x00}, 37 {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, {0x50f, 0x00}, 38 {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, {0x521, 0x2f}, 39 {0x525, 0x0f}, {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, 40 {0x55c, 0x50}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, 41 {0x609, 0x2a}, {0x60c, 0x18}, {0x620, 0xff}, {0x621, 0xff}, 42 {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, 43 {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, {0x63c, 0x0a}, 44 {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, {0x640, 0x40}, 45 {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, {0x66e, 0x05}, 46 {0x6a0, 0xff}, {0x6a1, 0xff}, {0x6a2, 0xff}, {0x6a3, 0xff}, 47 {0x6a4, 0xff}, {0x6a5, 0xff}, {0x6de, 0x84}, {0x700, 0x21}, 48 {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, 49 {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, {0x718, 0x40}, 50 {0x7c0, 0x38}, {0x7c2, 0x0f}, {0x7c3, 0xc0}, {0x073, 0x04}, 51 {0x7c4, 0x77}, {0x024, 0xc7}, {0x7ec, 0xff}, {0x7ed, 0xff}, 52 {0x7ee, 0xff}, {0x7ef, 0xff}, 53 {0xffff, 0xff}, 54}; 55 56/* If updating the phy init table, also update rtl8192f_revise_cck_tx_psf(). */ 57static const struct rtl8xxxu_reg32val rtl8192fu_phy_init_table[] = { 58 {0x800, 0x80006C00}, {0x804, 0x00004001}, 59 {0x808, 0x0000FC00}, {0x80C, 0x00000000}, 60 {0x810, 0x20200322}, {0x814, 0x020C3910}, 61 {0x818, 0x00000385}, {0x81C, 0x07000000}, 62 {0x820, 0x01000100}, {0x824, 0x00390204}, 63 {0x828, 0x01000100}, {0x82C, 0x00390204}, 64 {0x830, 0x25252525}, {0x834, 0x25252525}, 65 {0x838, 0x25252525}, {0x83C, 0x25252525}, 66 {0x840, 0x00010000}, {0x844, 0x00010000}, 67 {0x848, 0x25252525}, {0x84C, 0x25252525}, 68 {0x850, 0x00031FE0}, {0x854, 0x00000000}, 69 {0x858, 0x569A569A}, {0x85C, 0x00400040}, 70 {0x860, 0x66F60000}, {0x864, 0x061F0000}, 71 {0x868, 0x25252525}, {0x86C, 0x25252525}, 72 {0x870, 0x00000300}, {0x874, 0x04003400}, 73 {0x878, 0x08080808}, {0x87C, 0x004F0201}, 74 {0x880, 0xD8001402}, {0x884, 0xC0000120}, 75 {0x888, 0x00000000}, {0x88C, 0xCC0000C0}, 76 {0x890, 0x00000000}, {0x894, 0xFFFFFFFE}, 77 {0x898, 0x40302010}, {0x89C, 0x00706050}, 78 {0x900, 0x00000000}, {0x904, 0x00000023}, 79 {0x908, 0x00000F00}, {0x90C, 0x81121313}, 80 {0x910, 0x024C0000}, {0x914, 0x00000000}, 81 {0x918, 0x00000000}, {0x91C, 0x00000000}, 82 {0x920, 0x00000000}, {0x924, 0x00000000}, 83 {0x928, 0x00000000}, {0x92C, 0x00000000}, 84 {0x930, 0x88000000}, {0x934, 0x00000245}, 85 {0x938, 0x00024588}, {0x93C, 0x00000000}, 86 {0x940, 0x000007FF}, {0x944, 0x3F3F0000}, 87 {0x948, 0x000001A3}, {0x94C, 0x20200008}, 88 {0x950, 0x00338A98}, {0x954, 0x00000000}, 89 {0x958, 0xCBCAD87A}, {0x95C, 0x06EB5735}, 90 {0x960, 0x00000000}, {0x964, 0x00000000}, 91 {0x968, 0x00000000}, {0x96C, 0x00000003}, 92 {0x970, 0x00000000}, {0x974, 0x00000000}, 93 {0x978, 0x00000000}, {0x97C, 0x10030000}, 94 {0x980, 0x00000000}, {0x984, 0x02800280}, 95 {0x988, 0x020A5704}, {0x98C, 0x1461C826}, 96 {0x990, 0x0001469E}, {0x994, 0x008858D1}, 97 {0x998, 0x400086C9}, {0x99C, 0x44444242}, 98 {0x9A0, 0x00000000}, {0x9A4, 0x00000000}, 99 {0x9A8, 0x00000000}, {0x9AC, 0xC0000000}, 100 {0xA00, 0x00D047C8}, {0xA04, 0xC1FF0008}, 101 {0xA08, 0x88838300}, {0xA0C, 0x2E20100F}, 102 {0xA10, 0x9500BB78}, {0xA14, 0x11144028}, 103 {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, 104 {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, 105 {0xA28, 0x00158810}, {0xA2C, 0x10BB8000}, 106 {0xA70, 0x00008000}, {0xA74, 0x80800100}, 107 {0xA78, 0x000089F0}, {0xA7C, 0x225B0606}, 108 {0xA80, 0x20803210}, {0xA84, 0x00200200}, 109 {0xA88, 0x00000000}, {0xA8C, 0x00000000}, 110 {0xA90, 0x00000000}, {0xA94, 0x00000000}, 111 {0xA98, 0x00000000}, {0xA9C, 0x00460000}, 112 {0xAA0, 0x00000000}, {0xAA4, 0x00020014}, 113 {0xAA8, 0xBA0A0008}, {0xAAC, 0x01235667}, 114 {0xAB0, 0x00000000}, {0xAB4, 0x00201402}, 115 {0xAB8, 0x0000001C}, {0xABC, 0x0000F7FF}, 116 {0xAC0, 0xD4C0A742}, {0xAC4, 0x00000000}, 117 {0xAC8, 0x00000F08}, {0xACC, 0x00000F07}, 118 {0xAD0, 0xA1052A10}, {0xAD4, 0x0D9D8452}, 119 {0xAD8, 0x9E024024}, {0xADC, 0x0023C001}, 120 {0xAE0, 0x00000391}, {0xB2C, 0x00000000}, 121 {0xC00, 0x00000080}, {0xC04, 0x6F005433}, 122 {0xC08, 0x000004E4}, {0xC0C, 0x6C6C6C6C}, 123 {0xC10, 0x22000000}, {0xC14, 0x40000100}, 124 {0xC18, 0x22000000}, {0xC1C, 0x40000100}, 125 {0xC20, 0x00000000}, {0xC24, 0x40000100}, 126 {0xC28, 0x00000000}, {0xC2C, 0x40000100}, 127 {0xC30, 0x0401E809}, {0xC34, 0x30000020}, 128 {0xC38, 0x23808080}, {0xC3C, 0x00002F44}, 129 {0xC40, 0x1CF8403F}, {0xC44, 0x000100C7}, 130 {0xC48, 0xEC060106}, {0xC4C, 0x007F037F}, 131 {0xC50, 0x00E48020}, {0xC54, 0x04008017}, 132 {0xC58, 0x00000020}, {0xC5C, 0x00708492}, 133 {0xC60, 0x09280200}, {0xC64, 0x5014838B}, 134 {0xC68, 0x47C006C7}, {0xC6C, 0x00000035}, 135 {0xC70, 0x00001007}, {0xC74, 0x02815269}, 136 {0xC78, 0x0FE07F1F}, {0xC7C, 0x00B91612}, 137 {0xC80, 0x40000100}, {0xC84, 0x32000000}, 138 {0xC88, 0x40000100}, {0xC8C, 0xA0240000}, 139 {0xC90, 0x400E161E}, {0xC94, 0x00000F00}, 140 {0xC98, 0x400E161E}, {0xC9C, 0x0000BDC8}, 141 {0xCA0, 0x00000000}, {0xCA4, 0x098300A0}, 142 {0xCA8, 0x00006B00}, {0xCAC, 0x87F45B1A}, 143 {0xCB0, 0x0000002D}, {0xCB4, 0x00000000}, 144 {0xCB8, 0x00000000}, {0xCBC, 0x28100200}, 145 {0xCC0, 0x0010A3D0}, {0xCC4, 0x00000F7D}, 146 {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, 147 {0xCD0, 0x593659AD}, {0xCD4, 0xB7545121}, 148 {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, 149 {0xCE0, 0x40201000}, {0xCE4, 0x00000000}, 150 {0xCE8, 0x40E04407}, {0xCEC, 0x2E572000}, 151 {0xD00, 0x000D8780}, {0xD04, 0x40020403}, 152 {0xD08, 0x0002907F}, {0xD0C, 0x20010201}, 153 {0xD10, 0x06288888}, {0xD14, 0x8888367B}, 154 {0xD18, 0x7D806DB3}, {0xD1C, 0x0000007F}, 155 {0xD20, 0x567600B8}, {0xD24, 0x0000018B}, 156 {0xD28, 0xD513FF7D}, {0xD2C, 0xCC979975}, 157 {0xD30, 0x04928000}, {0xD34, 0x40608000}, 158 {0xD38, 0x88DDA000}, {0xD3C, 0x00026EE2}, 159 {0xD50, 0x67270001}, {0xD54, 0x20500000}, 160 {0xD58, 0x16161616}, {0xD5C, 0x71F20064}, 161 {0xD60, 0x4653DA60}, {0xD64, 0x3E718A3C}, 162 {0xD68, 0x00000183}, {0xD7C, 0x00000000}, 163 {0xD80, 0x50000000}, {0xD84, 0x31310400}, 164 {0xD88, 0xF5B50000}, {0xD8C, 0x00000000}, 165 {0xD90, 0x00000000}, {0xD94, 0x44BBBB44}, 166 {0xD98, 0x44BB44FF}, {0xD9C, 0x06033688}, 167 {0xE00, 0x25252525}, {0xE04, 0x25252525}, 168 {0xE08, 0x25252525}, {0xE10, 0x25252525}, 169 {0xE14, 0x25252525}, {0xE18, 0x25252525}, 170 {0xE1C, 0x25252525}, {0xE20, 0x00000000}, 171 {0xE24, 0x00200000}, {0xE28, 0x00000000}, 172 {0xE2C, 0x00000000}, {0xE30, 0x01007C00}, 173 {0xE34, 0x01004800}, {0xE38, 0x10008C0F}, 174 {0xE3C, 0x3C008C0F}, {0xE40, 0x01007C00}, 175 {0xE44, 0x00000000}, {0xE48, 0x00000000}, 176 {0xE4C, 0x00000000}, {0xE50, 0x01007C00}, 177 {0xE54, 0x01004800}, {0xE58, 0x10008C0F}, 178 {0xE5C, 0x3C008C0F}, {0xE60, 0x02100000}, 179 {0xE64, 0xBBBBBBBB}, {0xE68, 0x40404040}, 180 {0xE6C, 0x80408040}, {0xE70, 0x80408040}, 181 {0xE74, 0x40404040}, {0xE78, 0x00400040}, 182 {0xE7C, 0x40404040}, {0xE80, 0x00FF0000}, 183 {0xE84, 0x80408040}, {0xE88, 0x40404040}, 184 {0xE8C, 0x80408040}, {0xED0, 0x80408040}, 185 {0xED4, 0x80408040}, {0xED8, 0x80408040}, 186 {0xEDC, 0xC040C040}, {0xEE0, 0xC040C040}, 187 {0xEE4, 0x00400040}, {0xEE8, 0xD8001402}, 188 {0xEEC, 0xC0000120}, {0xEF0, 0x02000B09}, 189 {0xEF4, 0x00000001}, {0xEF8, 0x00000000}, 190 {0xF00, 0x00000300}, {0xF04, 0x00000002}, 191 {0xF08, 0x00007D0C}, {0xF0C, 0x0000A907}, 192 {0xF10, 0x00005807}, {0xF14, 0x00000003}, 193 {0xF18, 0x07D003E8}, {0xF1C, 0x8000001F}, 194 {0xF20, 0x00000000}, {0xF24, 0x00000000}, 195 {0xF28, 0x00000000}, {0xF2C, 0x00000000}, 196 {0xF30, 0x00000000}, {0xF34, 0x00000000}, 197 {0xF38, 0x00030055}, {0xF3C, 0x0000003A}, 198 {0xF40, 0x00000002}, {0xF44, 0x00000000}, 199 {0xF48, 0x00000000}, {0xF4C, 0x0B000000}, 200 {0xF50, 0x00000000}, 201 {0xffff, 0xffffffff}, 202}; 203 204static const struct rtl8xxxu_reg32val rtl8192f_agc_table[] = { 205 {0xC78, 0x0FA0001F}, {0xC78, 0x0FA0011F}, 206 {0xC78, 0x0FA0021F}, {0xC78, 0x0FA0031F}, 207 {0xC78, 0x0FA0041F}, {0xC78, 0x0FA0051F}, 208 {0xC78, 0x0F90061F}, {0xC78, 0x0F80071F}, 209 {0xC78, 0x0F70081F}, {0xC78, 0x0F60091F}, 210 {0xC78, 0x0F500A1F}, {0xC78, 0x0F400B1F}, 211 {0xC78, 0x0F300C1F}, {0xC78, 0x0F200D1F}, 212 {0xC78, 0x0F100E1F}, {0xC78, 0x0F000F1F}, 213 {0xC78, 0x0EF0101F}, {0xC78, 0x0EE0111F}, 214 {0xC78, 0x0ED0121F}, {0xC78, 0x0EC0131F}, 215 {0xC78, 0x0EB0141F}, {0xC78, 0x0EA0151F}, 216 {0xC78, 0x0E90161F}, {0xC78, 0x0E80171F}, 217 {0xC78, 0x0E70181F}, {0xC78, 0x0E60191F}, 218 {0xC78, 0x0E501A1F}, {0xC78, 0x0E401B1F}, 219 {0xC78, 0x0E301C1F}, {0xC78, 0x0C701D1F}, 220 {0xC78, 0x0C601E1F}, {0xC78, 0x0C501F1F}, 221 {0xC78, 0x0C40201F}, {0xC78, 0x0C30211F}, 222 {0xC78, 0x0A60221F}, {0xC78, 0x0A50231F}, 223 {0xC78, 0x0A40241F}, {0xC78, 0x0A30251F}, 224 {0xC78, 0x0860261F}, {0xC78, 0x0850271F}, 225 {0xC78, 0x0840281F}, {0xC78, 0x0830291F}, 226 {0xC78, 0x06702A1F}, {0xC78, 0x06602B1F}, 227 {0xC78, 0x06502C1F}, {0xC78, 0x06402D1F}, 228 {0xC78, 0x06302E1F}, {0xC78, 0x04602F1F}, 229 {0xC78, 0x0450301F}, {0xC78, 0x0440311F}, 230 {0xC78, 0x0430321F}, {0xC78, 0x0260331F}, 231 {0xC78, 0x0250341F}, {0xC78, 0x0240351F}, 232 {0xC78, 0x0230361F}, {0xC78, 0x0050371F}, 233 {0xC78, 0x0040381F}, {0xC78, 0x0030391F}, 234 {0xC78, 0x00203A1F}, {0xC78, 0x00103B1F}, 235 {0xC78, 0x00003C1F}, {0xC78, 0x00003D1F}, 236 {0xC78, 0x00003E1F}, {0xC78, 0x00003F1F}, 237 238 {0xC78, 0x0FA0401F}, {0xC78, 0x0FA0411F}, 239 {0xC78, 0x0FA0421F}, {0xC78, 0x0FA0431F}, 240 {0xC78, 0x0F90441F}, {0xC78, 0x0F80451F}, 241 {0xC78, 0x0F70461F}, {0xC78, 0x0F60471F}, 242 {0xC78, 0x0F50481F}, {0xC78, 0x0F40491F}, 243 {0xC78, 0x0F304A1F}, {0xC78, 0x0F204B1F}, 244 {0xC78, 0x0F104C1F}, {0xC78, 0x0F004D1F}, 245 {0xC78, 0x0EF04E1F}, {0xC78, 0x0EE04F1F}, 246 {0xC78, 0x0ED0501F}, {0xC78, 0x0EC0511F}, 247 {0xC78, 0x0EB0521F}, {0xC78, 0x0EA0531F}, 248 {0xC78, 0x0E90541F}, {0xC78, 0x0E80551F}, 249 {0xC78, 0x0E70561F}, {0xC78, 0x0E60571F}, 250 {0xC78, 0x0E50581F}, {0xC78, 0x0E40591F}, 251 {0xC78, 0x0E305A1F}, {0xC78, 0x0E205B1F}, 252 {0xC78, 0x0E105C1F}, {0xC78, 0x0C505D1F}, 253 {0xC78, 0x0C405E1F}, {0xC78, 0x0C305F1F}, 254 {0xC78, 0x0C20601F}, {0xC78, 0x0C10611F}, 255 {0xC78, 0x0A40621F}, {0xC78, 0x0A30631F}, 256 {0xC78, 0x0A20641F}, {0xC78, 0x0A10651F}, 257 {0xC78, 0x0840661F}, {0xC78, 0x0830671F}, 258 {0xC78, 0x0820681F}, {0xC78, 0x0810691F}, 259 {0xC78, 0x06506A1F}, {0xC78, 0x06406B1F}, 260 {0xC78, 0x06306C1F}, {0xC78, 0x06206D1F}, 261 {0xC78, 0x06106E1F}, {0xC78, 0x04406F1F}, 262 {0xC78, 0x0430701F}, {0xC78, 0x0420711F}, 263 {0xC78, 0x0410721F}, {0xC78, 0x0240731F}, 264 {0xC78, 0x0230741F}, {0xC78, 0x0220751F}, 265 {0xC78, 0x0210761F}, {0xC78, 0x0030771F}, 266 {0xC78, 0x0020781F}, {0xC78, 0x0010791F}, 267 {0xC78, 0x00007A1F}, {0xC78, 0x00007B1F}, 268 {0xC78, 0x00007C1F}, {0xC78, 0x00007D1F}, 269 {0xC78, 0x00007E1F}, {0xC78, 0x00007F1F}, 270 271 {0xC78, 0x0FA0801F}, {0xC78, 0x0FA0811F}, 272 {0xC78, 0x0FA0821F}, {0xC78, 0x0FA0831F}, 273 {0xC78, 0x0FA0841F}, {0xC78, 0x0FA0851F}, 274 {0xC78, 0x0F90861F}, {0xC78, 0x0F80871F}, 275 {0xC78, 0x0F70881F}, {0xC78, 0x0F60891F}, 276 {0xC78, 0x0F508A1F}, {0xC78, 0x0F408B1F}, 277 {0xC78, 0x0F308C1F}, {0xC78, 0x0F208D1F}, 278 {0xC78, 0x0F108E1F}, {0xC78, 0x0B908F1F}, 279 {0xC78, 0x0B80901F}, {0xC78, 0x0B70911F}, 280 {0xC78, 0x0B60921F}, {0xC78, 0x0B50931F}, 281 {0xC78, 0x0B40941F}, {0xC78, 0x0B30951F}, 282 {0xC78, 0x0B20961F}, {0xC78, 0x0B10971F}, 283 {0xC78, 0x0B00981F}, {0xC78, 0x0AF0991F}, 284 {0xC78, 0x0AE09A1F}, {0xC78, 0x0AD09B1F}, 285 {0xC78, 0x0AC09C1F}, {0xC78, 0x0AB09D1F}, 286 {0xC78, 0x0AA09E1F}, {0xC78, 0x0A909F1F}, 287 {0xC78, 0x0A80A01F}, {0xC78, 0x0A70A11F}, 288 {0xC78, 0x0A60A21F}, {0xC78, 0x0A50A31F}, 289 {0xC78, 0x0A40A41F}, {0xC78, 0x0A30A51F}, 290 {0xC78, 0x0A20A61F}, {0xC78, 0x0A10A71F}, 291 {0xC78, 0x0A00A81F}, {0xC78, 0x0830A91F}, 292 {0xC78, 0x0820AA1F}, {0xC78, 0x0810AB1F}, 293 {0xC78, 0x0800AC1F}, {0xC78, 0x0640AD1F}, 294 {0xC78, 0x0630AE1F}, {0xC78, 0x0620AF1F}, 295 {0xC78, 0x0610B01F}, {0xC78, 0x0600B11F}, 296 {0xC78, 0x0430B21F}, {0xC78, 0x0420B31F}, 297 {0xC78, 0x0410B41F}, {0xC78, 0x0400B51F}, 298 {0xC78, 0x0230B61F}, {0xC78, 0x0220B71F}, 299 {0xC78, 0x0210B81F}, {0xC78, 0x0200B91F}, 300 {0xC78, 0x0000BA1F}, {0xC78, 0x0000BB1F}, 301 {0xC78, 0x0000BC1F}, {0xC78, 0x0000BD1F}, 302 {0xC78, 0x0000BE1F}, {0xC78, 0x0000BF1F}, 303 {0xC50, 0x00E48024}, {0xC50, 0x00E48020}, 304 {0xffff, 0xffffffff} 305}; 306 307static const struct rtl8xxxu_rfregval rtl8192fu_radioa_init_table[] = { 308 {0x00, 0x30000}, {0x18, 0x0FC07}, {0x81, 0x0FC00}, {0x82, 0x003C0}, 309 {0x84, 0x00005}, {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, 310 {0x8E, 0x64540}, {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, 311 {0x53, 0x10061}, {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, 312 {0x57, 0x2CC00}, {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, 313 {0x5C, 0x00015}, {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, 314 {0xEF, 0x00002}, {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, 315 {0xEF, 0x00000}, {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, 316 {0xEF, 0x00800}, {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, 317 {0x33, 0x0C84B}, {0x33, 0x1088A}, {0x33, 0x14C50}, {0x33, 0x18C8E}, 318 {0x33, 0x1CCCD}, {0x33, 0x20CD0}, {0x33, 0x24CD3}, {0x33, 0x28CD6}, 319 {0x33, 0x4002B}, {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, 320 {0x33, 0x50888}, {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, 321 {0x33, 0x60CCF}, {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, 322 {0xEF, 0x00400}, {0x33, 0x01C23}, {0x33, 0x05C23}, {0x33, 0x09D23}, 323 {0x33, 0x0DD23}, {0x33, 0x11FA3}, {0x33, 0x15FA3}, {0x33, 0x19FAB}, 324 {0x33, 0x1DFAB}, {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, 325 {0x33, 0x04030}, {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, 326 {0x33, 0x14030}, {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, 327 {0x33, 0x24030}, {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, 328 {0x33, 0x34030}, {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, 329 {0xEF, 0x00100}, {0x33, 0x44001}, {0x33, 0x48001}, {0x33, 0x4C001}, 330 {0x33, 0x50001}, {0x33, 0x54001}, {0x33, 0x58001}, {0x33, 0x5C001}, 331 {0x33, 0x60001}, {0x33, 0x64001}, {0x33, 0x68001}, {0x33, 0x6C001}, 332 {0x33, 0x70001}, {0x33, 0x74001}, {0x33, 0x78001}, {0x33, 0x04000}, 333 {0x33, 0x08000}, {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, 334 {0x33, 0x18001}, {0x33, 0x1C002}, {0x33, 0x20002}, {0x33, 0x24002}, 335 {0x33, 0x28002}, {0x33, 0x2C002}, {0x33, 0x30002}, {0x33, 0x34002}, 336 {0x33, 0x38002}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, 337 {0x30, 0x20000}, {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, 338 {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, 339 {0x32, 0xF1DF3}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, 340 {0x30, 0x38000}, {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, 341 {0x1B, 0x746CE}, {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, 342 {0x33, 0x70000}, {0x33, 0x78000}, {0xEF, 0x00000}, {0xDF, 0x08000}, 343 {0xB0, 0xFFBCB}, {0xB3, 0x06000}, {0xB7, 0x18DF0}, {0xB8, 0x38FF0}, 344 {0xC9, 0x00600}, {0xDF, 0x00000}, {0xB1, 0x33B8F}, {0xB2, 0x33762}, 345 {0xB4, 0x141F0}, {0xB5, 0x14080}, {0xB6, 0x12425}, {0xB9, 0xC0008}, 346 {0xBA, 0x40005}, {0xC2, 0x02C01}, {0xC3, 0x0000B}, {0xC4, 0x81E2F}, 347 {0xC5, 0x5C28F}, {0xC6, 0x000A0}, {0xCA, 0x02000}, {0xFE, 0x00000}, 348 {0x18, 0x08C07}, {0xFE, 0x00000}, {0xFE, 0x00000}, {0xFE, 0x00000}, 349 {0x00, 0x31DD5}, 350 {0xff, 0xffffffff} 351}; 352 353static const struct rtl8xxxu_rfregval rtl8192fu_radiob_init_table[] = { 354 {0x00, 0x30000}, {0x81, 0x0FC00}, {0x82, 0x003C0}, {0x84, 0x00005}, 355 {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, {0x8E, 0x64540}, 356 {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, {0x53, 0x10061}, 357 {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, {0x57, 0x2CC00}, 358 {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, {0x5C, 0x00015}, 359 {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, {0xEF, 0x00002}, 360 {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, {0xEF, 0x00000}, 361 {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, {0xEF, 0x00800}, 362 {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, {0x33, 0x0C84B}, 363 {0x33, 0x1088A}, {0x33, 0x14CC8}, {0x33, 0x18CCB}, {0x33, 0x1CCCE}, 364 {0x33, 0x20CD1}, {0x33, 0x24CD4}, {0x33, 0x28CD7}, {0x33, 0x4002B}, 365 {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, {0x33, 0x50888}, 366 {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, {0x33, 0x60CCF}, 367 {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, {0xEF, 0x00400}, 368 {0x33, 0x01D23}, {0x33, 0x05D23}, {0x33, 0x09FA3}, {0x33, 0x0DFA3}, 369 {0x33, 0x11D2B}, {0x33, 0x15D2B}, {0x33, 0x19FAB}, {0x33, 0x1DFAB}, 370 {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, {0x33, 0x04030}, 371 {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, {0x33, 0x14030}, 372 {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, {0x33, 0x24030}, 373 {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, {0x33, 0x34030}, 374 {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, {0xEF, 0x00100}, 375 {0x33, 0x44000}, {0x33, 0x48000}, {0x33, 0x4C000}, {0x33, 0x50000}, 376 {0x33, 0x54000}, {0x33, 0x58000}, {0x33, 0x5C000}, {0x33, 0x60000}, 377 {0x33, 0x64000}, {0x33, 0x68000}, {0x33, 0x6C000}, {0x33, 0x70000}, 378 {0x33, 0x74000}, {0x33, 0x78000}, {0x33, 0x04000}, {0x33, 0x08000}, 379 {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, {0x33, 0x18000}, 380 {0x33, 0x1C001}, {0x33, 0x20001}, {0x33, 0x24001}, {0x33, 0x28001}, 381 {0x33, 0x2C001}, {0x33, 0x30001}, {0x33, 0x34001}, {0x33, 0x38001}, 382 {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, {0x30, 0x20000}, 383 {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, {0x84, 0x00000}, 384 {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, {0x32, 0xF1DF3}, 385 {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x38000}, 386 {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, {0x1B, 0x746CE}, 387 {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, {0x33, 0x70000}, 388 {0x33, 0x78000}, {0xEF, 0x00000}, {0x00, 0x31DD5}, 389 {0xff, 0xffffffff} 390}; 391 392static int rtl8192fu_identify_chip(struct rtl8xxxu_priv *priv) 393{ 394 struct device *dev = &priv->udev->dev; 395 u32 sys_cfg, vendor, val32; 396 397 strscpy(priv->chip_name, "8192FU", sizeof(priv->chip_name)); 398 priv->rtl_chip = RTL8192F; 399 priv->rf_paths = 2; 400 priv->rx_paths = 2; 401 priv->tx_paths = 2; 402 403 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); 404 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); 405 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { 406 dev_info(dev, "Unsupported test chip\n"); 407 return -EOPNOTSUPP; 408 } 409 410 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); 411 priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN); 412 priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN); 413 priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN); 414 priv->is_multi_func = 1; 415 416 vendor = sys_cfg & SYS_CFG_VENDOR_ID; 417 rtl8xxxu_identify_vendor_1bit(priv, vendor); 418 419 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); 420 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); 421 422 return rtl8xxxu_config_endpoints_no_sie(priv); 423} 424 425static void 426rtl8192f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) 427{ 428 u8 cck, ofdmbase, mcsbase; 429 u32 val32, ofdm, mcs; 430 int group, cck_group; 431 432 rtl8188f_channel_to_group(channel, &group, &cck_group); 433 434 cck = priv->cck_tx_power_index_A[cck_group]; 435 436 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, 0x00007f00, cck); 437 438 val32 = (cck << 16) | (cck << 8) | cck; 439 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, 440 0x7f7f7f00, val32); 441 442 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; 443 ofdmbase += priv->ofdm_tx_power_diff[RF_A].a; 444 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 445 446 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, 0x7f7f7f7f, ofdm); 447 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, 0x7f7f7f7f, ofdm); 448 449 mcsbase = priv->ht40_1s_tx_power_index_A[group]; 450 if (ht40) 451 mcsbase += priv->ht40_tx_power_diff[RF_A].a; 452 else 453 mcsbase += priv->ht20_tx_power_diff[RF_A].a; 454 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 455 456 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, 0x7f7f7f7f, mcs); 457 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, 0x7f7f7f7f, mcs); 458 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, 0x7f7f7f7f, mcs); 459 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, 0x7f7f7f7f, mcs); 460 461 if (priv->tx_paths == 1) 462 return; 463 464 cck = priv->cck_tx_power_index_B[cck_group]; 465 466 val32 = (cck << 16) | (cck << 8) | cck; 467 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK1_55_MCS32, 468 0x7f7f7f00, val32); 469 470 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, 471 0x0000007f, cck); 472 473 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; 474 ofdmbase += priv->ofdm_tx_power_diff[RF_B].b; 475 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; 476 477 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, 0x7f7f7f7f, ofdm); 478 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, 0x7f7f7f7f, ofdm); 479 480 mcsbase = priv->ht40_1s_tx_power_index_B[group]; 481 if (ht40) 482 mcsbase += priv->ht40_tx_power_diff[RF_B].b; 483 else 484 mcsbase += priv->ht20_tx_power_diff[RF_B].b; 485 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; 486 487 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, 0x7f7f7f7f, mcs); 488 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, 0x7f7f7f7f, mcs); 489 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, 0x7f7f7f7f, mcs); 490 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, 0x7f7f7f7f, mcs); 491} 492 493static void rtl8192f_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) 494{ 495 if (channel == 13) { 496 /* Special value for channel 13 */ 497 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001); 498 /* Normal values */ 499 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); 500 rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); 501 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); 502 } else if (channel == 14) { 503 /* Normal value */ 504 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); 505 /* Special values for channel 14 */ 506 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); 507 rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x0000); 508 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); 509 } else { 510 /* Restore normal values from the phy init table */ 511 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); 512 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); 513 rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); 514 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); 515 } 516} 517 518static void rtl8192fu_config_kfree(struct rtl8xxxu_priv *priv, u8 channel) 519{ 520 u8 bb_gain[3] = { EFUSE_UNDEFINED, EFUSE_UNDEFINED, EFUSE_UNDEFINED }; 521 u8 bb_gain_path_mask[2] = { 0x0f, 0xf0 }; 522 enum rtl8xxxu_rfpath rfpath; 523 u8 bb_gain_for_path; 524 u8 channel_idx = 0; 525 526 if (channel >= 1 && channel <= 3) 527 channel_idx = 0; 528 if (channel >= 4 && channel <= 9) 529 channel_idx = 1; 530 if (channel >= 10 && channel <= 14) 531 channel_idx = 2; 532 533 rtl8xxxu_read_efuse8(priv, 0x1ee, &bb_gain[1]); 534 rtl8xxxu_read_efuse8(priv, 0x1ec, &bb_gain[0]); 535 rtl8xxxu_read_efuse8(priv, 0x1ea, &bb_gain[2]); 536 537 if (bb_gain[1] == EFUSE_UNDEFINED) 538 return; 539 540 if (bb_gain[0] == EFUSE_UNDEFINED) 541 bb_gain[0] = bb_gain[1]; 542 543 if (bb_gain[2] == EFUSE_UNDEFINED) 544 bb_gain[2] = bb_gain[1]; 545 546 for (rfpath = RF_A; rfpath < priv->rf_paths; rfpath++) { 547 /* power_trim based on 55[19:14] */ 548 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_UNKNOWN_55, 549 BIT(5), 1); 550 551 /* enable 55[14] for 0.5db step */ 552 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CTRL, 553 BIT(18), 1); 554 555 /* enter power_trim debug mode */ 556 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, 557 BIT(7), 1); 558 559 /* write enable */ 560 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 1); 561 562 bb_gain_for_path = (bb_gain[channel_idx] & bb_gain_path_mask[rfpath]); 563 bb_gain_for_path >>= __ffs(bb_gain_path_mask[rfpath]); 564 565 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, 566 0x70000, channel_idx * 2); 567 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, 568 0x3f, bb_gain_for_path); 569 570 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, 571 0x70000, channel_idx * 2 + 1); 572 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, 573 0x3f, bb_gain_for_path); 574 575 /* leave power_trim debug mode */ 576 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, 577 BIT(7), 0); 578 579 /* write disable */ 580 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 0); 581 } 582} 583 584static void rtl8192fu_config_channel(struct ieee80211_hw *hw) 585{ 586 struct rtl8xxxu_priv *priv = hw->priv; 587 bool ht40 = conf_is_ht40(&hw->conf); 588 u8 channel, subchannel = 0; 589 bool sec_ch_above = 0; 590 u32 val32; 591 592 channel = (u8)hw->conf.chandef.chan->hw_value; 593 594 if (conf_is_ht40_plus(&hw->conf)) { 595 sec_ch_above = 1; 596 channel += 2; 597 subchannel = 2; 598 } else if (conf_is_ht40_minus(&hw->conf)) { 599 sec_ch_above = 0; 600 channel -= 2; 601 subchannel = 1; 602 } 603 604 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 605 606 rtl8192f_revise_cck_tx_psf(priv, channel); 607 608 /* Set channel */ 609 val32 &= ~(BIT(18) | BIT(17)); /* select the 2.4G band(?) */ 610 u32p_replace_bits(&val32, channel, 0xff); 611 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 612 if (priv->rf_paths > 1) 613 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); 614 615 rtl8192fu_config_kfree(priv, channel); 616 617 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); 618 619 /* small BW */ 620 rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30)); 621 622 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, ht40); 623 rtl8xxxu_write32_mask(priv, REG_FPGA1_RF_MODE, FPGA_RF_MODE, ht40); 624 625 /* ADC clock = 160M */ 626 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4); 627 628 /* DAC clock = 80M */ 629 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), 2); 630 631 /* ADC buffer clk */ 632 rtl8xxxu_write32_mask(priv, REG_ANTDIV_PARA1, BIT(27) | BIT(26), 2); 633 634 if (ht40) 635 /* Set Control channel to upper or lower. */ 636 rtl8xxxu_write32_mask(priv, REG_CCK0_SYSTEM, 637 CCK0_SIDEBAND, !sec_ch_above); 638 639 /* Enable CCK */ 640 rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK); 641 642 /* RF TRX_BW */ 643 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); 644 val32 &= ~MODE_AG_BW_MASK; 645 if (ht40) 646 val32 |= MODE_AG_BW_40MHZ_8723B; 647 else 648 val32 |= MODE_AG_BW_20MHZ_8723B; 649 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); 650 if (priv->rf_paths > 1) 651 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); 652 653 /* Modify RX DFIR parameters */ 654 rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, BIT(21) | BIT(20), 2); 655 656 rtl8xxxu_write32_mask(priv, REG_DOWNSAM_FACTOR, BIT(29) | BIT(28), 2); 657 658 if (ht40) 659 val32 = 0x3; 660 else 661 val32 = 0x1a3; 662 rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32); 663} 664 665static void rtl8192fu_init_aggregation(struct rtl8xxxu_priv *priv) 666{ 667 u32 agg_rx; 668 u8 agg_ctrl; 669 670 /* RX aggregation */ 671 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); 672 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; 673 674 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); 675 agg_rx &= ~RXDMA_USB_AGG_ENABLE; 676 agg_rx &= ~0xFF0F; /* reset agg size and timeout */ 677 678 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); 679 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); 680} 681 682static int rtl8192fu_parse_efuse(struct rtl8xxxu_priv *priv) 683{ 684 struct rtl8192fu_efuse *efuse = &priv->efuse_wifi.efuse8192fu; 685 int i; 686 687 if (efuse->rtl_id != cpu_to_le16(0x8129)) 688 return -EINVAL; 689 690 ether_addr_copy(priv->mac_addr, efuse->mac_addr); 691 692 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, 693 sizeof(efuse->tx_power_index_A.cck_base)); 694 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, 695 sizeof(efuse->tx_power_index_B.cck_base)); 696 697 memcpy(priv->ht40_1s_tx_power_index_A, 698 efuse->tx_power_index_A.ht40_base, 699 sizeof(efuse->tx_power_index_A.ht40_base)); 700 memcpy(priv->ht40_1s_tx_power_index_B, 701 efuse->tx_power_index_B.ht40_base, 702 sizeof(efuse->tx_power_index_B.ht40_base)); 703 704 priv->ht20_tx_power_diff[0].a = 705 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; 706 priv->ht20_tx_power_diff[0].b = 707 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; 708 709 priv->ht40_tx_power_diff[0].a = 0; 710 priv->ht40_tx_power_diff[0].b = 0; 711 712 for (i = 1; i < RTL8723B_TX_COUNT; i++) { 713 priv->ofdm_tx_power_diff[i].a = 714 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; 715 priv->ofdm_tx_power_diff[i].b = 716 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; 717 718 priv->ht20_tx_power_diff[i].a = 719 efuse->tx_power_index_A.pwr_diff[i - 1].ht20; 720 priv->ht20_tx_power_diff[i].b = 721 efuse->tx_power_index_B.pwr_diff[i - 1].ht20; 722 723 priv->ht40_tx_power_diff[i].a = 724 efuse->tx_power_index_A.pwr_diff[i - 1].ht40; 725 priv->ht40_tx_power_diff[i].b = 726 efuse->tx_power_index_B.pwr_diff[i - 1].ht40; 727 } 728 729 priv->default_crystal_cap = efuse->xtal_k & 0x3f; 730 731 priv->rfe_type = efuse->rfe_option & 0x1f; 732 733 if (priv->rfe_type != 5 && priv->rfe_type != 1) 734 dev_warn(&priv->udev->dev, 735 "%s: RFE type %d was not tested. Please send an email to linux-wireless@vger.kernel.org about this.\n", 736 __func__, priv->rfe_type); 737 738 return 0; 739} 740 741static int rtl8192fu_load_firmware(struct rtl8xxxu_priv *priv) 742{ 743 return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8192fufw.bin"); 744} 745 746static void rtl8192fu_init_phy_bb(struct rtl8xxxu_priv *priv) 747{ 748 /* Enable BB and RF */ 749 rtl8xxxu_write16_set(priv, REG_SYS_FUNC, 750 SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); 751 752 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 753 754 /* To Fix MAC loopback mode fail. */ 755 rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, 0xf); 756 rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, 0xe9); 757 758 rtl8xxxu_init_phy_regs(priv, rtl8192fu_phy_init_table); 759 760 rtl8xxxu_init_phy_regs(priv, rtl8192f_agc_table); 761} 762 763static int rtl8192fu_init_phy_rf(struct rtl8xxxu_priv *priv) 764{ 765 int ret; 766 767 ret = rtl8xxxu_init_phy_rf(priv, rtl8192fu_radioa_init_table, RF_A); 768 if (ret) 769 return ret; 770 771 return rtl8xxxu_init_phy_rf(priv, rtl8192fu_radiob_init_table, RF_B); 772} 773 774static void rtl8192f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) 775{ 776 u32 backup_mask = BIT(31) | BIT(30); 777 u32 backup; 778 u32 val32; 779 780 /* Aries's NarrowBand */ 781 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 782 backup = u32_get_bits(val32, backup_mask); 783 784 u32p_replace_bits(&val32, 0, backup_mask); 785 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 786 787 rtl8188f_phy_lc_calibrate(priv); 788 789 /* Aries's NarrowBand */ 790 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); 791 u32p_replace_bits(&val32, backup, backup_mask); 792 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); 793 794 /* reset OFDM state */ 795 rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); 796 rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); 797} 798 799static int rtl8192fu_iqk_path_a(struct rtl8xxxu_priv *priv) 800{ 801 u32 reg_eac, reg_e94, reg_e9c, val32; 802 u32 rf_0x58_i, rf_0x58_q; 803 u8 rfe = priv->rfe_type; 804 int result = 0; 805 int ktime, i; 806 807 /* Leave IQK mode */ 808 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 809 810 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 811 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); 812 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); 813 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); 814 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); 815 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); 816 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 817 818 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(4), 1); 819 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); 820 if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) 821 val32 = 0x30; 822 else 823 val32 = 0xe9; 824 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32); 825 826 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 827 828 /* path-A IQK setting */ 829 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 830 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 831 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 832 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 833 834 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214000f); 835 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28140000); 836 837 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 838 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 839 840 /* LO calibration setting */ 841 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); 842 843 /* One shot, path A LOK & IQK */ 844 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); 845 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); 846 847 mdelay(15); 848 849 ktime = 0; 850 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { 851 mdelay(5); 852 ktime += 5; 853 } 854 855 /* Check failed */ 856 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 857 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 858 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 859 860 /* reload 0xdf and CCK_IND off */ 861 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 862 863 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 1); 864 865 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXMOD); 866 rf_0x58_i = u32_get_bits(val32, 0xfc000); 867 rf_0x58_q = u32_get_bits(val32, 0x003f0); 868 869 for (i = 0; i < 8; i++) { 870 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, 871 0x1c000, i); 872 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, 873 0x00fc0, rf_0x58_i); 874 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, 875 0x0003f, rf_0x58_q); 876 } 877 878 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, BIT(14), 0); 879 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 0); 880 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00810, 0); 881 882 if (!(reg_eac & BIT(28)) && 883 ((reg_e94 & 0x03ff0000) != 0x01420000) && 884 ((reg_e9c & 0x03ff0000) != 0x00420000)) 885 result |= 0x01; 886 887 return result; 888} 889 890static int rtl8192fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) 891{ 892 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; 893 int result = 0; 894 int ktime; 895 896 /* Leave IQK mode */ 897 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 898 899 /* PA/PAD control by 0x56, and set = 0x0 */ 900 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); 901 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); 902 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); 903 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x27); 904 905 /* Enter IQK mode */ 906 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 907 908 /* path-A IQK setting */ 909 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); 910 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 911 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 912 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 913 914 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160027); 915 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); 916 917 /* Tx IQK setting */ 918 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 919 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 920 921 /* LO calibration setting */ 922 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); 923 924 /* One shot, path A LOK & IQK */ 925 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); 926 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); 927 928 mdelay(15); 929 930 ktime = 0; 931 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { 932 mdelay(5); 933 ktime += 5; 934 } 935 936 /* Check failed */ 937 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 938 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 939 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 940 941 if (!(reg_eac & BIT(28)) && 942 ((reg_e94 & 0x03ff0000) != 0x01420000) && 943 ((reg_e9c & 0x03ff0000) != 0x00420000)) { 944 result |= 0x01; 945 } else { /* If TX not OK, ignore RX */ 946 /* PA/PAD controlled by 0x0 */ 947 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 948 949 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 950 BIT(11), 0); 951 952 return result; 953 } 954 955 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); 956 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 957 958 /* Modify RX IQK mode table */ 959 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 960 961 /* PA/PAD control by 0x56, and set = 0x0 */ 962 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); 963 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); 964 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); 965 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); 966 967 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 968 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); 969 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); 970 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); 971 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); 972 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); 973 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 974 975 /* Enter IQK mode */ 976 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 977 978 /* path-A IQK setting */ 979 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 980 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); 981 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 982 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 983 984 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82170000); 985 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28170000); 986 987 /* RX IQK setting */ 988 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 989 990 /* LO calibration setting */ 991 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); 992 993 /* One shot, path A LOK & IQK */ 994 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); 995 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); 996 997 mdelay(15); 998 999 ktime = 0; 1000 while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) { 1001 mdelay(5); 1002 ktime += 5; 1003 } 1004 1005 /* Check failed */ 1006 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1007 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 1008 1009 /* Leave IQK mode */ 1010 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1011 1012 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 0); 1013 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0x02000); 1014 1015 if (!(reg_eac & BIT(27)) && 1016 ((reg_ea4 & 0x03ff0000) != 0x01320000) && 1017 ((reg_eac & 0x03ff0000) != 0x00360000)) 1018 result |= 0x02; 1019 1020 return result; 1021} 1022 1023static int rtl8192fu_iqk_path_b(struct rtl8xxxu_priv *priv) 1024{ 1025 u32 reg_eac, reg_eb4, reg_ebc, val32; 1026 u32 rf_0x58_i, rf_0x58_q; 1027 u8 rfe = priv->rfe_type; 1028 int result = 0; 1029 int ktime, i; 1030 1031 /* PA/PAD controlled by 0x0 */ 1032 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1033 1034 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 1035 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); 1036 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); 1037 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); 1038 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); 1039 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); 1040 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); 1041 1042 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(4), 1); 1043 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); 1044 if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) 1045 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 1046 0x003ff, 0x30); 1047 else 1048 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 1049 0x00fff, 0xe9); 1050 1051 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 1052 1053 /* Path B IQK setting */ 1054 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 1055 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 1056 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); 1057 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 1058 1059 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8214000F); 1060 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28140000); 1061 1062 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); 1063 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1064 1065 /* LO calibration setting */ 1066 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); 1067 1068 /* One shot, path B LOK & IQK */ 1069 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); 1070 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); 1071 1072 mdelay(15); 1073 1074 ktime = 0; 1075 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { 1076 mdelay(5); 1077 ktime += 5; 1078 } 1079 1080 /* Check failed */ 1081 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1082 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 1083 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 1084 1085 /* reload 0xdf and CCK_IND off */ 1086 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1087 1088 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 1); 1089 1090 val32 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_TXMOD); 1091 rf_0x58_i = u32_get_bits(val32, 0xfc000); 1092 rf_0x58_q = u32_get_bits(val32, 0x003f0); 1093 1094 for (i = 0; i < 8; i++) { 1095 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, 1096 0x1c000, i); 1097 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, 1098 0x00fc0, rf_0x58_i); 1099 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, 1100 0x0003f, rf_0x58_q); 1101 } 1102 1103 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_AC, BIT(14), 0); 1104 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 0); 1105 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00810, 0); 1106 1107 if (!(reg_eac & BIT(31)) && 1108 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 1109 ((reg_ebc & 0x03ff0000) != 0x00420000)) 1110 result |= 0x01; 1111 else 1112 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", 1113 __func__); 1114 1115 return result; 1116} 1117 1118static int rtl8192fu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) 1119{ 1120 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; 1121 int result = 0; 1122 int ktime; 1123 1124 /* Leave IQK mode */ 1125 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1126 1127 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); 1128 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); 1129 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); 1130 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x67); 1131 1132 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 1133 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); 1134 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); 1135 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); 1136 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); 1137 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); 1138 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); 1139 1140 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 1141 1142 /* path-B IQK setting */ 1143 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 1144 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 1145 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); 1146 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); 1147 1148 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160027); 1149 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160000); 1150 1151 /* LO calibration setting */ 1152 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); 1153 1154 /* One shot, path A LOK & IQK */ 1155 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); 1156 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); 1157 1158 mdelay(15); 1159 1160 ktime = 0; 1161 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { 1162 mdelay(5); 1163 ktime += 5; 1164 } 1165 1166 /* Check failed */ 1167 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1168 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 1169 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 1170 1171 if (!(reg_eac & BIT(31)) && 1172 ((reg_eb4 & 0x03ff0000) != 0x01420000) && 1173 ((reg_ebc & 0x03ff0000) != 0x00420000)) { 1174 result |= 0x01; 1175 } else { 1176 /* PA/PAD controlled by 0x0 */ 1177 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1178 1179 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 1180 BIT(11), 0); 1181 1182 return result; 1183 } 1184 1185 val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); 1186 rtl8xxxu_write32(priv, REG_TX_IQK, val32); 1187 1188 /* Modify RX IQK mode table */ 1189 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1190 1191 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); 1192 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); 1193 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); 1194 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); 1195 1196 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); 1197 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); 1198 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); 1199 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); 1200 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); 1201 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); 1202 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); 1203 1204 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 1205 1206 /* Path B IQK setting */ 1207 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); 1208 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); 1209 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); 1210 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); 1211 1212 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82170000); 1213 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28170000); 1214 1215 /* IQK setting */ 1216 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); 1217 1218 /* LO calibration setting */ 1219 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); 1220 1221 /* One shot, path A LOK & IQK */ 1222 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); 1223 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); 1224 1225 mdelay(15); 1226 1227 ktime = 0; 1228 while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) { 1229 mdelay(5); 1230 ktime += 5; 1231 } 1232 1233 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1234 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 1235 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 1236 1237 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1238 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 1239 1240 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 0); 1241 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 0); 1242 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0x02000); 1243 1244 if (!(reg_eac & BIT(30)) && 1245 ((reg_ec4 & 0x03ff0000) != 0x01320000) && 1246 ((reg_ecc & 0x03ff0000) != 0x00360000)) 1247 result |= 0x02; 1248 else 1249 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", 1250 __func__); 1251 1252 return result; 1253} 1254 1255static void rtl8192fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, 1256 int result[][8], int t) 1257{ 1258 static const u32 adda_regs[2] = { 1259 REG_ANAPWR1, REG_RX_WAIT_CCA 1260 }; 1261 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { 1262 REG_TXPAUSE, REG_BEACON_CTRL, 1263 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG 1264 }; 1265 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { 1266 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, 1267 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, 1268 REG_DPDT_CTRL, REG_RFE_CTRL_ANTA_SRC, 1269 REG_RFE_CTRL_ANT_SRC2, REG_CCK0_AFE_SETTING 1270 }; 1271 u32 rx_initial_gain_a, rx_initial_gain_b; 1272 struct device *dev = &priv->udev->dev; 1273 int path_a_ok, path_b_ok; 1274 u8 rfe = priv->rfe_type; 1275 int retry = 2; 1276 u32 i, val32; 1277 1278 /* 1279 * Note: IQ calibration must be performed after loading 1280 * PHY_REG.txt , and radio_a, radio_b.txt 1281 */ 1282 1283 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1284 1285 rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); 1286 rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); 1287 1288 if (t == 0) { 1289 /* Save ADDA parameters, turn Path A ADDA on */ 1290 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, 1291 ARRAY_SIZE(adda_regs)); 1292 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1293 rtl8xxxu_save_regs(priv, iqk_bb_regs, 1294 priv->bb_backup, RTL8XXXU_BB_REGS); 1295 } 1296 1297 /* Instead of rtl8xxxu_path_adda_on */ 1298 rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); 1299 1300 /* MAC settings */ 1301 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1302 rtl8xxxu_write8_clear(priv, REG_GPIO_MUXCFG, GPIO_MUXCFG_IO_SEL_ENBT); 1303 1304 if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { 1305 /* in ePA IQK, rfe_func_config & SW both pull down */ 1306 /* path A */ 1307 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF, 0x7); 1308 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x1, 0x0); 1309 1310 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF00, 0x7); 1311 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x4, 0x0); 1312 1313 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF000, 0x7); 1314 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8, 0x0); 1315 1316 /* path B */ 1317 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0, 0x7); 1318 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x20000, 0x0); 1319 1320 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0000, 0x7); 1321 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x100000, 0x0); 1322 1323 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 0xF000, 0x7); 1324 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8000000, 0x0); 1325 } 1326 1327 if (priv->rf_paths > 1) { 1328 /* path B standby */ 1329 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000); 1330 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000); 1331 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); 1332 } 1333 1334 for (i = 0; i < retry; i++) { 1335 path_a_ok = rtl8192fu_iqk_path_a(priv); 1336 1337 if (path_a_ok == 0x01) { 1338 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); 1339 result[t][0] = (val32 >> 16) & 0x3ff; 1340 1341 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); 1342 result[t][1] = (val32 >> 16) & 0x3ff; 1343 break; 1344 } else { 1345 result[t][0] = 0x100; 1346 result[t][1] = 0x0; 1347 } 1348 } 1349 1350 for (i = 0; i < retry; i++) { 1351 path_a_ok = rtl8192fu_rx_iqk_path_a(priv); 1352 1353 if (path_a_ok == 0x03) { 1354 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); 1355 result[t][2] = (val32 >> 16) & 0x3ff; 1356 1357 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); 1358 result[t][3] = (val32 >> 16) & 0x3ff; 1359 break; 1360 } else { 1361 result[t][2] = 0x100; 1362 result[t][3] = 0x0; 1363 } 1364 } 1365 1366 if (!path_a_ok) 1367 dev_warn(dev, "%s: Path A IQK failed!\n", __func__); 1368 1369 if (priv->rf_paths > 1) { 1370 for (i = 0; i < retry; i++) { 1371 path_b_ok = rtl8192fu_iqk_path_b(priv); 1372 1373 if (path_b_ok == 0x01) { 1374 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); 1375 result[t][4] = (val32 >> 16) & 0x3ff; 1376 1377 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); 1378 result[t][5] = (val32 >> 16) & 0x3ff; 1379 break; 1380 } else { 1381 result[t][4] = 0x100; 1382 result[t][5] = 0x0; 1383 } 1384 } 1385 1386 for (i = 0; i < retry; i++) { 1387 path_b_ok = rtl8192fu_rx_iqk_path_b(priv); 1388 1389 if (path_b_ok == 0x03) { 1390 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); 1391 result[t][6] = (val32 >> 16) & 0x3ff; 1392 1393 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); 1394 result[t][7] = (val32 >> 16) & 0x3ff; 1395 break; 1396 } else { 1397 result[t][6] = 0x100; 1398 result[t][7] = 0x0; 1399 } 1400 } 1401 1402 if (!path_b_ok) 1403 dev_warn(dev, "%s: Path B IQK failed!\n", __func__); 1404 } 1405 1406 /* Back to BB mode, load original value */ 1407 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); 1408 1409 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xcc0000c0); 1410 1411 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44bbbb44); 1412 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x80408040); 1413 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005433); 1414 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000004e4); 1415 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400); 1416 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); 1417 1418 /* Reload ADDA power saving parameters */ 1419 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, 1420 ARRAY_SIZE(adda_regs)); 1421 1422 /* Reload MAC parameters */ 1423 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); 1424 1425 /* Reload BB parameters */ 1426 rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS); 1427 1428 rtl8xxxu_write32_clear(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); 1429 1430 /* Restore RX initial gain */ 1431 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50); 1432 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 1433 rx_initial_gain_a & 0xff); 1434 if (priv->rf_paths > 1) { 1435 rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 0x50); 1436 rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 1437 rx_initial_gain_b & 0xff); 1438 } 1439} 1440 1441static void rtl8192fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) 1442{ 1443 s32 reg_e94, reg_e9c, reg_ea4, reg_eac; 1444 s32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; 1445 struct device *dev = &priv->udev->dev; 1446 u32 path_a_0xdf, path_a_0x35; 1447 u32 path_b_0xdf, path_b_0x35; 1448 bool path_a_ok, path_b_ok; 1449 u8 rfe = priv->rfe_type; 1450 u32 rfe_path_select; 1451 int result[4][8]; /* last is final result */ 1452 int i, candidate; 1453 s32 reg_tmp = 0; 1454 bool simu; 1455 u32 val32; 1456 1457 rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT); 1458 1459 path_a_0xdf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); 1460 path_a_0x35 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_P1); 1461 path_b_0xdf = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA); 1462 path_b_0x35 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_P1); 1463 1464 memset(result, 0, sizeof(result)); 1465 candidate = -1; 1466 1467 path_a_ok = false; 1468 path_b_ok = false; 1469 1470 for (i = 0; i < 3; i++) { 1471 rtl8192fu_phy_iqcalibrate(priv, result, i); 1472 1473 if (i == 1) { 1474 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); 1475 if (simu) { 1476 candidate = 0; 1477 break; 1478 } 1479 } 1480 1481 if (i == 2) { 1482 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); 1483 if (simu) { 1484 candidate = 0; 1485 break; 1486 } 1487 1488 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); 1489 if (simu) { 1490 candidate = 1; 1491 } else { 1492 for (i = 0; i < 8; i++) 1493 reg_tmp += result[3][i]; 1494 1495 if (reg_tmp) 1496 candidate = 3; 1497 else 1498 candidate = -1; 1499 } 1500 } 1501 } 1502 1503 if (candidate >= 0) { 1504 reg_e94 = result[candidate][0]; 1505 reg_e9c = result[candidate][1]; 1506 reg_ea4 = result[candidate][2]; 1507 reg_eac = result[candidate][3]; 1508 reg_eb4 = result[candidate][4]; 1509 reg_ebc = result[candidate][5]; 1510 reg_ec4 = result[candidate][6]; 1511 reg_ecc = result[candidate][7]; 1512 1513 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); 1514 dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%c\n", 1515 __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, 1516 reg_eb4, reg_ebc, reg_ec4, reg_ecc); 1517 1518 path_a_ok = true; 1519 path_b_ok = true; 1520 } 1521 1522 rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, 0x3ff00000, 0x100); 1523 rtl8xxxu_write32_mask(priv, REG_NP_ANTA, 0x3ff, 0); 1524 rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, 0x3ff00000, 0x100); 1525 rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, 0x3ff, 0); 1526 1527 if (candidate >= 0) { 1528 if (reg_e94) 1529 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, 1530 candidate, (reg_ea4 == 0)); 1531 1532 if (reg_eb4) 1533 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, 1534 candidate, (reg_ec4 == 0)); 1535 } 1536 1537 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, path_a_0xdf); 1538 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, path_a_0x35); 1539 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, path_b_0xdf); 1540 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, path_b_0x35); 1541 1542 if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { 1543 rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000); 1544 rtl8xxxu_write32_clear(priv, REG_LEDCFG0, 0x6c00000); 1545 rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28)); 1546 rtl8xxxu_write32_clear(priv, REG_SW_GPIO_SHARE_CTRL_0, 1547 0x600000 | BIT(4)); 1548 1549 /* 1550 * Originally: 1551 * odm_set_bb_reg(dm, R_0x944, BIT(11) | 0x1F, 0x3F); 1552 * 1553 * It clears bit 11 and sets bits 0..4. The mask doesn't cover 1554 * bit 5 so it's not modified. Is that what it's supposed to 1555 * accomplish? 1556 */ 1557 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); 1558 val32 &= ~BIT(11); 1559 val32 |= 0x1f; 1560 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); 1561 1562 if (rfe == 7) { 1563 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 1564 0xfffff, 0x23200); 1565 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 1566 0xfffff, 0x23200); 1567 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, 1568 0xf000, 0x3); 1569 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 1570 0xf000, 0x3); 1571 } else { 1572 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 1573 0xfffff, 0x22200); 1574 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 1575 0xfffff, 0x22200); 1576 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, 1577 0xf000, 0x2); 1578 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 1579 0xf000, 0x2); 1580 } 1581 1582 rtl8xxxu_write32_clear(priv, REG_RFE_OPT62, BIT(2)); 1583 1584 if (rfe == 7) 1585 rtl8xxxu_write32(priv, REG_RFE_OPT, 0x03000003); 1586 1587 rtl8xxxu_write32(priv, REG_RFE_PATH_SELECT, rfe_path_select); 1588 } 1589} 1590 1591static void rtl8192fu_disabled_to_emu(struct rtl8xxxu_priv *priv) 1592{ 1593 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, 1594 APS_FSMCO_HW_POWERDOWN | APS_FSMCO_HW_SUSPEND); 1595 1596 rtl8xxxu_write32_clear(priv, REG_GPIO_INTM, BIT(16)); 1597 1598 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, 1599 APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); 1600} 1601 1602static int rtl8192fu_emu_to_active(struct rtl8xxxu_priv *priv) 1603{ 1604 u32 val32; 1605 u16 val16; 1606 int count; 1607 1608 /* enable LDOA12 MACRO block for all interface */ 1609 rtl8xxxu_write8_set(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); 1610 1611 /* disable BT_GPS_SEL pins */ 1612 rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28)); 1613 1614 mdelay(1); 1615 1616 /* release analog Ips to digital */ 1617 rtl8xxxu_write8_clear(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); 1618 1619 val16 = APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND | APS_FSMCO_SW_LPS; 1620 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, val16); 1621 1622 /* wait till 0x04[17] = 1 power ready */ 1623 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1624 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1625 if (val32 & BIT(17)) 1626 break; 1627 1628 udelay(10); 1629 } 1630 1631 if (!count) 1632 return -EBUSY; 1633 1634 rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); 1635 1636 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1637 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1638 if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0) 1639 break; 1640 1641 udelay(10); 1642 } 1643 1644 if (!count) 1645 return -EBUSY; 1646 1647 /* SWR OCP enable */ 1648 rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18)); 1649 1650 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN); 1651 1652 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, 1653 APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); 1654 1655 /* 0x7c[31]=1, LDO has max output capability */ 1656 rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31)); 1657 1658 rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_ENABLE); 1659 1660 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1661 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1662 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) 1663 break; 1664 1665 udelay(10); 1666 } 1667 1668 if (!count) 1669 return -EBUSY; 1670 1671 /* Enable WL control XTAL setting */ 1672 rtl8xxxu_write8_set(priv, REG_AFE_MISC, AFE_MISC_WL_XTAL_CTRL); 1673 1674 /* Enable falling edge triggering interrupt */ 1675 rtl8xxxu_write16_set(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); 1676 1677 /* Enable GPIO9 data mode */ 1678 rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_IRQ); 1679 1680 /* Enable GPIO9 input mode */ 1681 rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_INPUT); 1682 1683 /* Enable HSISR GPIO[C:0] interrupt */ 1684 rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0)); 1685 1686 /* RF HW ON/OFF Enable */ 1687 rtl8xxxu_write8_clear(priv, REG_MULTI_FUNC_CTRL, MULTI_WIFI_HW_ROF_EN); 1688 1689 /* Register Lock Disable */ 1690 rtl8xxxu_write8_set(priv, REG_RSV_CTRL, BIT(7)); 1691 1692 /* For GPIO9 internal pull high setting */ 1693 rtl8xxxu_write16_set(priv, REG_MULTI_FUNC_CTRL, BIT(14)); 1694 1695 /* reset RF path S1 */ 1696 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); 1697 1698 /* reset RF path S0 */ 1699 rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, 0); 1700 1701 /* enable RF path S1 */ 1702 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_SDMRSTB | RF_RSTB | RF_ENABLE); 1703 1704 /* enable RF path S0 */ 1705 rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, RF_SDMRSTB | RF_RSTB | RF_ENABLE); 1706 1707 /* AFE_Ctrl */ 1708 rtl8xxxu_write8_set(priv, REG_RSVD_1, BIT(5)); 1709 1710 /* AFE_Ctrl */ 1711 rtl8xxxu_write8(priv, REG_RSVD_4, 0xcc); 1712 1713 /* AFE_Ctrl 0x24[4:3]=00 for xtal gmn */ 1714 rtl8xxxu_write8_clear(priv, REG_AFE_XTAL_CTRL, BIT(4) | BIT(3)); 1715 1716 /* GPIO_A[31:0] Pull down software register */ 1717 rtl8xxxu_write32(priv, REG_GPIO_A0, 0xffffffff); 1718 1719 /* GPIO_B[7:0] Pull down software register */ 1720 rtl8xxxu_write8(priv, REG_GPIO_B0, 0xff); 1721 1722 /* Register Lock Enable */ 1723 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(7)); 1724 1725 return 0; 1726} 1727 1728static int rtl8192fu_active_to_emu(struct rtl8xxxu_priv *priv) 1729{ 1730 u32 val32; 1731 int count; 1732 1733 /* Reset BB, RF enter Power Down mode */ 1734 rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); 1735 1736 /* Enable rising edge triggering interrupt */ 1737 rtl8xxxu_write16_clear(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); 1738 1739 /* release WLON reset */ 1740 rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); 1741 1742 /* turn off MAC by HW state machine */ 1743 rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_OFF); 1744 1745 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { 1746 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); 1747 if ((val32 & APS_FSMCO_MAC_OFF) == 0) 1748 break; 1749 1750 udelay(10); 1751 } 1752 1753 if (!count) 1754 return -EBUSY; 1755 1756 /* analog Ips to digital, 1:isolation */ 1757 rtl8xxxu_write8_set(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); 1758 1759 /* disable LDOA12 MACRO block */ 1760 rtl8xxxu_write8_clear(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); 1761 1762 return 0; 1763} 1764 1765static int rtl8192fu_emu_to_disabled(struct rtl8xxxu_priv *priv) 1766{ 1767 u16 val16; 1768 1769 /* SOP option to disable BG/MB */ 1770 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); 1771 1772 /* 0x04[12:11] = 2b'01 enable WL suspend */ 1773 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); 1774 val16 &= ~APS_FSMCO_PCIE; 1775 val16 |= APS_FSMCO_HW_SUSPEND; 1776 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); 1777 1778 /* enable GPIO9 as EXT WAKEUP */ 1779 rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16)); 1780 1781 return 0; 1782} 1783 1784static int rtl8192fu_active_to_lps(struct rtl8xxxu_priv *priv) 1785{ 1786 struct device *dev = &priv->udev->dev; 1787 u16 val16; 1788 u32 val32; 1789 int retry; 1790 1791 /* Tx Pause */ 1792 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); 1793 1794 retry = 100; 1795 1796 /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ 1797 do { 1798 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); 1799 if (!val32) 1800 break; 1801 1802 udelay(10); 1803 } while (retry--); 1804 1805 if (!retry) { 1806 dev_warn(dev, "%s: Failed to flush TX queue\n", __func__); 1807 return -EBUSY; 1808 } 1809 1810 /* Disable CCK and OFDM, clock gated */ 1811 rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); 1812 1813 udelay(2); 1814 1815 /* Whole BB is reset */ 1816 rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BB_GLB_RSTN); 1817 1818 /* Reset MAC TRX */ 1819 val16 = rtl8xxxu_read16(priv, REG_CR); 1820 val16 &= 0xff00; 1821 val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE; 1822 val16 &= ~CR_SECURITY_ENABLE; 1823 rtl8xxxu_write16(priv, REG_CR, val16); 1824 1825 /* Respond TxOK to scheduler */ 1826 rtl8xxxu_write8_set(priv, REG_DUAL_TSF_RST, DUAL_TSF_TX_OK); 1827 1828 return 0; 1829} 1830 1831static int rtl8192fu_power_on(struct rtl8xxxu_priv *priv) 1832{ 1833 u16 val16; 1834 int ret; 1835 1836 rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80); 1837 1838 rtl8192fu_disabled_to_emu(priv); 1839 1840 ret = rtl8192fu_emu_to_active(priv); 1841 if (ret) 1842 return ret; 1843 1844 rtl8xxxu_write16(priv, REG_CR, 0); 1845 1846 val16 = rtl8xxxu_read16(priv, REG_CR); 1847 1848 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | 1849 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | 1850 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | 1851 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE; 1852 rtl8xxxu_write16(priv, REG_CR, val16); 1853 1854 return 0; 1855} 1856 1857static void rtl8192fu_power_off(struct rtl8xxxu_priv *priv) 1858{ 1859 rtl8xxxu_flush_fifo(priv); 1860 1861 /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ 1862 rtl8xxxu_write8_clear(priv, REG_TX_REPORT_CTRL, 1863 TX_REPORT_CTRL_TIMER_ENABLE); 1864 1865 /* stop rx */ 1866 rtl8xxxu_write8(priv, REG_CR, 0x00); 1867 1868 rtl8192fu_active_to_lps(priv); 1869 1870 /* Reset Firmware if running in RAM */ 1871 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) 1872 rtl8xxxu_firmware_self_reset(priv); 1873 1874 /* Reset MCU */ 1875 rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); 1876 1877 /* Reset MCU ready status */ 1878 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); 1879 1880 rtl8192fu_active_to_emu(priv); 1881 rtl8192fu_emu_to_disabled(priv); 1882} 1883 1884static void rtl8192f_reset_8051(struct rtl8xxxu_priv *priv) 1885{ 1886 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); 1887 1888 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0)); 1889 1890 rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); 1891 1892 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); 1893 1894 rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0)); 1895 1896 rtl8xxxu_write16_set(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); 1897} 1898 1899static void rtl8192f_enable_rf(struct rtl8xxxu_priv *priv) 1900{ 1901 u32 val32; 1902 1903 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); 1904 1905 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1906 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); 1907 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | 1908 OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; 1909 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1910 1911 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); 1912} 1913 1914static void rtl8192f_disable_rf(struct rtl8xxxu_priv *priv) 1915{ 1916 u32 val32; 1917 1918 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); 1919 val32 &= ~OFDM_RF_PATH_TX_MASK; 1920 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); 1921 1922 /* Power down RF module */ 1923 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); 1924} 1925 1926static void rtl8192f_usb_quirks(struct rtl8xxxu_priv *priv) 1927{ 1928 u16 val16; 1929 1930 rtl8xxxu_gen2_usb_quirks(priv); 1931 1932 val16 = rtl8xxxu_read16(priv, REG_CR); 1933 val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); 1934 rtl8xxxu_write16(priv, REG_CR, val16); 1935} 1936 1937#define XTAL1 GENMASK(6, 1) 1938#define XTAL0 GENMASK(30, 25) 1939 1940static void rtl8192f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) 1941{ 1942 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; 1943 u32 xtal1, xtal0; 1944 1945 if (crystal_cap == cfo->crystal_cap) 1946 return; 1947 1948 xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL); 1949 xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); 1950 1951 dev_dbg(&priv->udev->dev, 1952 "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n", 1953 __func__, 1954 cfo->crystal_cap, 1955 u32_get_bits(xtal1, XTAL1), 1956 u32_get_bits(xtal0, XTAL0), 1957 crystal_cap); 1958 1959 u32p_replace_bits(&xtal1, crystal_cap, XTAL1); 1960 u32p_replace_bits(&xtal0, crystal_cap, XTAL0); 1961 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, xtal1); 1962 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, xtal0); 1963 1964 cfo->crystal_cap = crystal_cap; 1965} 1966 1967static s8 rtl8192f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) 1968{ 1969 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; 1970 u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l; 1971 u8 vga_idx = phy_stats0->vga; 1972 s8 rx_pwr_all; 1973 1974 switch (lna_idx) { 1975 case 7: 1976 rx_pwr_all = -44 - (2 * vga_idx); 1977 break; 1978 case 5: 1979 rx_pwr_all = -28 - (2 * vga_idx); 1980 break; 1981 case 3: 1982 rx_pwr_all = -10 - (2 * vga_idx); 1983 break; 1984 case 0: 1985 rx_pwr_all = 14 - (2 * vga_idx); 1986 break; 1987 default: 1988 rx_pwr_all = 0; 1989 break; 1990 } 1991 1992 return rx_pwr_all; 1993} 1994 1995static int rtl8192fu_led_brightness_set(struct led_classdev *led_cdev, 1996 enum led_brightness brightness) 1997{ 1998 struct rtl8xxxu_priv *priv = container_of(led_cdev, 1999 struct rtl8xxxu_priv, 2000 led_cdev); 2001 u32 ledcfg; 2002 2003 /* Values obtained by observing the USB traffic from the Windows driver. */ 2004 rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, 0x20080); 2005 rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x1b0000); 2006 2007 ledcfg = rtl8xxxu_read32(priv, REG_LEDCFG0); 2008 2009 /* Comfast CF-826F uses LED1. Asus USB-N13 C1 uses LED0. Set both. */ 2010 2011 u32p_replace_bits(&ledcfg, LED_GPIO_ENABLE, LEDCFG0_LED2EN); 2012 u32p_replace_bits(&ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED0_IO_MODE); 2013 u32p_replace_bits(&ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED1_IO_MODE); 2014 2015 if (brightness == LED_OFF) { 2016 u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); 2017 u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); 2018 u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); 2019 u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); 2020 } else if (brightness == LED_ON) { 2021 u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); 2022 u32p_replace_bits(&ledcfg, LED_SW_ON, LEDCFG0_LED0SV); 2023 u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); 2024 u32p_replace_bits(&ledcfg, LED_SW_ON, LEDCFG0_LED1SV); 2025 } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { 2026 u32p_replace_bits(&ledcfg, LED_MODE_TX_OR_RX_EVENTS, 2027 LEDCFG0_LED0CM); 2028 u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); 2029 u32p_replace_bits(&ledcfg, LED_MODE_TX_OR_RX_EVENTS, 2030 LEDCFG0_LED1CM); 2031 u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); 2032 } 2033 2034 rtl8xxxu_write32(priv, REG_LEDCFG0, ledcfg); 2035 2036 return 0; 2037} 2038 2039struct rtl8xxxu_fileops rtl8192fu_fops = { 2040 .identify_chip = rtl8192fu_identify_chip, 2041 .parse_efuse = rtl8192fu_parse_efuse, 2042 .load_firmware = rtl8192fu_load_firmware, 2043 .power_on = rtl8192fu_power_on, 2044 .power_off = rtl8192fu_power_off, 2045 .read_efuse = rtl8xxxu_read_efuse, 2046 .reset_8051 = rtl8192f_reset_8051, 2047 .llt_init = rtl8xxxu_auto_llt_table, 2048 .init_phy_bb = rtl8192fu_init_phy_bb, 2049 .init_phy_rf = rtl8192fu_init_phy_rf, 2050 .phy_lc_calibrate = rtl8192f_phy_lc_calibrate, 2051 .phy_iq_calibrate = rtl8192fu_phy_iq_calibrate, 2052 .config_channel = rtl8192fu_config_channel, 2053 .parse_rx_desc = rtl8xxxu_parse_rxdesc24, 2054 .parse_phystats = jaguar2_rx_parse_phystats, 2055 .init_aggregation = rtl8192fu_init_aggregation, 2056 .init_burst = rtl8xxxu_init_burst, 2057 .enable_rf = rtl8192f_enable_rf, 2058 .disable_rf = rtl8192f_disable_rf, 2059 .usb_quirks = rtl8192f_usb_quirks, 2060 .set_tx_power = rtl8192f_set_tx_power, 2061 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, 2062 .report_connect = rtl8xxxu_gen2_report_connect, 2063 .report_rssi = rtl8xxxu_gen2_report_rssi, 2064 .fill_txdesc = rtl8xxxu_fill_txdesc_v2, 2065 .set_crystal_cap = rtl8192f_set_crystal_cap, 2066 .cck_rssi = rtl8192f_cck_rssi, 2067 .led_classdev_brightness_set = rtl8192fu_led_brightness_set, 2068 .writeN_block_size = 254, 2069 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), 2070 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), 2071 .has_tx_report = 1, 2072 .gen2_thermal_meter = 1, 2073 .needs_full_init = 1, 2074 .init_reg_rxfltmap = 1, 2075 .init_reg_pkt_life_time = 1, 2076 .init_reg_hmtfr = 1, 2077 .ampdu_max_time = 0x5e, 2078 .ustime_tsf_edca = 0x50, 2079 .max_aggr_num = 0x1f1f, 2080 .supports_ap = 1, 2081 .max_macid_num = 128, 2082 .max_sec_cam_num = 64, 2083 .trxff_boundary = 0x3f3f, 2084 .pbp_rx = PBP_PAGE_SIZE_256, 2085 .pbp_tx = PBP_PAGE_SIZE_256, 2086 .mactable = rtl8192f_mac_init_table, 2087 .total_page_num = TX_TOTAL_PAGE_NUM_8192F, 2088 .page_num_hi = TX_PAGE_NUM_HI_PQ_8192F, 2089 .page_num_lo = TX_PAGE_NUM_LO_PQ_8192F, 2090 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192F, 2091}; 2092