1// SPDX-License-Identifier: ISC 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/platform_device.h> 7#include <linux/rtnetlink.h> 8#include <linux/pci.h> 9 10#include "mt7915.h" 11#include "mac.h" 12#include "mcu.h" 13#include "../trace.h" 14#include "../dma.h" 15 16static bool wed_enable; 17module_param(wed_enable, bool, 0644); 18MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support"); 19 20static const u32 mt7915_reg[] = { 21 [INT_SOURCE_CSR] = 0xd7010, 22 [INT_MASK_CSR] = 0xd7014, 23 [INT1_SOURCE_CSR] = 0xd7088, 24 [INT1_MASK_CSR] = 0xd708c, 25 [INT_MCU_CMD_SOURCE] = 0xd51f0, 26 [INT_MCU_CMD_EVENT] = 0x3108, 27 [WFDMA0_ADDR] = 0xd4000, 28 [WFDMA0_PCIE1_ADDR] = 0xd8000, 29 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 30 [CBTOP1_PHY_END] = 0x77ffffff, 31 [INFRA_MCU_ADDR_END] = 0x7c3fffff, 32 [FW_ASSERT_STAT_ADDR] = 0x219848, 33 [FW_EXCEPT_TYPE_ADDR] = 0x21987c, 34 [FW_EXCEPT_COUNT_ADDR] = 0x219848, 35 [FW_CIRQ_COUNT_ADDR] = 0x216f94, 36 [FW_CIRQ_IDX_ADDR] = 0x216ef8, 37 [FW_CIRQ_LISR_ADDR] = 0x2170ac, 38 [FW_TASK_ID_ADDR] = 0x216f90, 39 [FW_TASK_IDX_ADDR] = 0x216f9c, 40 [FW_TASK_QID1_ADDR] = 0x219680, 41 [FW_TASK_QID2_ADDR] = 0x219760, 42 [FW_TASK_START_ADDR] = 0x219558, 43 [FW_TASK_END_ADDR] = 0x219554, 44 [FW_TASK_SIZE_ADDR] = 0x219560, 45 [FW_LAST_MSG_ID_ADDR] = 0x216f70, 46 [FW_EINT_INFO_ADDR] = 0x219818, 47 [FW_SCHED_INFO_ADDR] = 0x219828, 48 [SWDEF_BASE_ADDR] = 0x41f200, 49 [TXQ_WED_RING_BASE] = 0xd7300, 50 [RXQ_WED_RING_BASE] = 0xd7410, 51 [RXQ_WED_DATA_RING_BASE] = 0xd4500, 52}; 53 54static const u32 mt7916_reg[] = { 55 [INT_SOURCE_CSR] = 0xd4200, 56 [INT_MASK_CSR] = 0xd4204, 57 [INT1_SOURCE_CSR] = 0xd8200, 58 [INT1_MASK_CSR] = 0xd8204, 59 [INT_MCU_CMD_SOURCE] = 0xd41f0, 60 [INT_MCU_CMD_EVENT] = 0x2108, 61 [WFDMA0_ADDR] = 0xd4000, 62 [WFDMA0_PCIE1_ADDR] = 0xd8000, 63 [WFDMA_EXT_CSR_ADDR] = 0xd7000, 64 [CBTOP1_PHY_END] = 0x7fffffff, 65 [INFRA_MCU_ADDR_END] = 0x7c085fff, 66 [FW_ASSERT_STAT_ADDR] = 0x02204c14, 67 [FW_EXCEPT_TYPE_ADDR] = 0x022051a4, 68 [FW_EXCEPT_COUNT_ADDR] = 0x022050bc, 69 [FW_CIRQ_COUNT_ADDR] = 0x022001ac, 70 [FW_CIRQ_IDX_ADDR] = 0x02204f84, 71 [FW_CIRQ_LISR_ADDR] = 0x022050d0, 72 [FW_TASK_ID_ADDR] = 0x0220406c, 73 [FW_TASK_IDX_ADDR] = 0x0220500c, 74 [FW_TASK_QID1_ADDR] = 0x022028c8, 75 [FW_TASK_QID2_ADDR] = 0x02202a38, 76 [FW_TASK_START_ADDR] = 0x0220286c, 77 [FW_TASK_END_ADDR] = 0x02202870, 78 [FW_TASK_SIZE_ADDR] = 0x02202878, 79 [FW_LAST_MSG_ID_ADDR] = 0x02204fe8, 80 [FW_EINT_INFO_ADDR] = 0x0220525c, 81 [FW_SCHED_INFO_ADDR] = 0x0220516c, 82 [SWDEF_BASE_ADDR] = 0x411400, 83 [TXQ_WED_RING_BASE] = 0xd7300, 84 [RXQ_WED_RING_BASE] = 0xd7410, 85 [RXQ_WED_DATA_RING_BASE] = 0xd4540, 86}; 87 88static const u32 mt7986_reg[] = { 89 [INT_SOURCE_CSR] = 0x24200, 90 [INT_MASK_CSR] = 0x24204, 91 [INT1_SOURCE_CSR] = 0x28200, 92 [INT1_MASK_CSR] = 0x28204, 93 [INT_MCU_CMD_SOURCE] = 0x241f0, 94 [INT_MCU_CMD_EVENT] = 0x54000108, 95 [WFDMA0_ADDR] = 0x24000, 96 [WFDMA0_PCIE1_ADDR] = 0x28000, 97 [WFDMA_EXT_CSR_ADDR] = 0x27000, 98 [CBTOP1_PHY_END] = 0x7fffffff, 99 [INFRA_MCU_ADDR_END] = 0x7c085fff, 100 [FW_ASSERT_STAT_ADDR] = 0x02204b54, 101 [FW_EXCEPT_TYPE_ADDR] = 0x022050dc, 102 [FW_EXCEPT_COUNT_ADDR] = 0x02204ffc, 103 [FW_CIRQ_COUNT_ADDR] = 0x022001ac, 104 [FW_CIRQ_IDX_ADDR] = 0x02204ec4, 105 [FW_CIRQ_LISR_ADDR] = 0x02205010, 106 [FW_TASK_ID_ADDR] = 0x02204fac, 107 [FW_TASK_IDX_ADDR] = 0x02204f4c, 108 [FW_TASK_QID1_ADDR] = 0x02202814, 109 [FW_TASK_QID2_ADDR] = 0x02202984, 110 [FW_TASK_START_ADDR] = 0x022027b8, 111 [FW_TASK_END_ADDR] = 0x022027bc, 112 [FW_TASK_SIZE_ADDR] = 0x022027c4, 113 [FW_LAST_MSG_ID_ADDR] = 0x02204f28, 114 [FW_EINT_INFO_ADDR] = 0x02205194, 115 [FW_SCHED_INFO_ADDR] = 0x022051a4, 116 [SWDEF_BASE_ADDR] = 0x411400, 117 [TXQ_WED_RING_BASE] = 0x24420, 118 [RXQ_WED_RING_BASE] = 0x24520, 119 [RXQ_WED_DATA_RING_BASE] = 0x24540, 120}; 121 122static const u32 mt7915_offs[] = { 123 [TMAC_CDTR] = 0x090, 124 [TMAC_ODTR] = 0x094, 125 [TMAC_ATCR] = 0x098, 126 [TMAC_TRCR0] = 0x09c, 127 [TMAC_ICR0] = 0x0a4, 128 [TMAC_ICR1] = 0x0b4, 129 [TMAC_CTCR0] = 0x0f4, 130 [TMAC_TFCR0] = 0x1e0, 131 [MDP_BNRCFR0] = 0x070, 132 [MDP_BNRCFR1] = 0x074, 133 [ARB_DRNGR0] = 0x194, 134 [ARB_SCR] = 0x080, 135 [RMAC_MIB_AIRTIME14] = 0x3b8, 136 [AGG_AWSCR0] = 0x05c, 137 [AGG_PCR0] = 0x06c, 138 [AGG_ACR0] = 0x084, 139 [AGG_ACR4] = 0x08c, 140 [AGG_MRCR] = 0x098, 141 [AGG_ATCR1] = 0x0f0, 142 [AGG_ATCR3] = 0x0f4, 143 [LPON_UTTR0] = 0x080, 144 [LPON_UTTR1] = 0x084, 145 [LPON_FRCR] = 0x314, 146 [MIB_SDR3] = 0x014, 147 [MIB_SDR4] = 0x018, 148 [MIB_SDR5] = 0x01c, 149 [MIB_SDR7] = 0x024, 150 [MIB_SDR8] = 0x028, 151 [MIB_SDR9] = 0x02c, 152 [MIB_SDR10] = 0x030, 153 [MIB_SDR11] = 0x034, 154 [MIB_SDR12] = 0x038, 155 [MIB_SDR13] = 0x03c, 156 [MIB_SDR14] = 0x040, 157 [MIB_SDR15] = 0x044, 158 [MIB_SDR16] = 0x048, 159 [MIB_SDR17] = 0x04c, 160 [MIB_SDR18] = 0x050, 161 [MIB_SDR19] = 0x054, 162 [MIB_SDR20] = 0x058, 163 [MIB_SDR21] = 0x05c, 164 [MIB_SDR22] = 0x060, 165 [MIB_SDR23] = 0x064, 166 [MIB_SDR24] = 0x068, 167 [MIB_SDR25] = 0x06c, 168 [MIB_SDR27] = 0x074, 169 [MIB_SDR28] = 0x078, 170 [MIB_SDR29] = 0x07c, 171 [MIB_SDRVEC] = 0x080, 172 [MIB_SDR31] = 0x084, 173 [MIB_SDR32] = 0x088, 174 [MIB_SDRMUBF] = 0x090, 175 [MIB_DR8] = 0x0c0, 176 [MIB_DR9] = 0x0c4, 177 [MIB_DR11] = 0x0cc, 178 [MIB_MB_SDR0] = 0x100, 179 [MIB_MB_SDR1] = 0x104, 180 [TX_AGG_CNT] = 0x0a8, 181 [TX_AGG_CNT2] = 0x164, 182 [MIB_ARNG] = 0x4b8, 183 [WTBLON_TOP_WDUCR] = 0x0, 184 [WTBL_UPDATE] = 0x030, 185 [PLE_FL_Q_EMPTY] = 0x0b0, 186 [PLE_FL_Q_CTRL] = 0x1b0, 187 [PLE_AC_QEMPTY] = 0x500, 188 [PLE_FREEPG_CNT] = 0x100, 189 [PLE_FREEPG_HEAD_TAIL] = 0x104, 190 [PLE_PG_HIF_GROUP] = 0x110, 191 [PLE_HIF_PG_INFO] = 0x114, 192 [AC_OFFSET] = 0x040, 193 [ETBF_PAR_RPT0] = 0x068, 194}; 195 196static const u32 mt7916_offs[] = { 197 [TMAC_CDTR] = 0x0c8, 198 [TMAC_ODTR] = 0x0cc, 199 [TMAC_ATCR] = 0x00c, 200 [TMAC_TRCR0] = 0x010, 201 [TMAC_ICR0] = 0x014, 202 [TMAC_ICR1] = 0x018, 203 [TMAC_CTCR0] = 0x114, 204 [TMAC_TFCR0] = 0x0e4, 205 [MDP_BNRCFR0] = 0x090, 206 [MDP_BNRCFR1] = 0x094, 207 [ARB_DRNGR0] = 0x1e0, 208 [ARB_SCR] = 0x000, 209 [RMAC_MIB_AIRTIME14] = 0x0398, 210 [AGG_AWSCR0] = 0x030, 211 [AGG_PCR0] = 0x040, 212 [AGG_ACR0] = 0x054, 213 [AGG_ACR4] = 0x05c, 214 [AGG_MRCR] = 0x068, 215 [AGG_ATCR1] = 0x1a8, 216 [AGG_ATCR3] = 0x080, 217 [LPON_UTTR0] = 0x360, 218 [LPON_UTTR1] = 0x364, 219 [LPON_FRCR] = 0x37c, 220 [MIB_SDR3] = 0x698, 221 [MIB_SDR4] = 0x788, 222 [MIB_SDR5] = 0x780, 223 [MIB_SDR7] = 0x5a8, 224 [MIB_SDR8] = 0x78c, 225 [MIB_SDR9] = 0x024, 226 [MIB_SDR10] = 0x76c, 227 [MIB_SDR11] = 0x790, 228 [MIB_SDR12] = 0x558, 229 [MIB_SDR13] = 0x560, 230 [MIB_SDR14] = 0x564, 231 [MIB_SDR15] = 0x568, 232 [MIB_SDR16] = 0x7fc, 233 [MIB_SDR17] = 0x800, 234 [MIB_SDR18] = 0x030, 235 [MIB_SDR19] = 0x5ac, 236 [MIB_SDR20] = 0x5b0, 237 [MIB_SDR21] = 0x5b4, 238 [MIB_SDR22] = 0x770, 239 [MIB_SDR23] = 0x774, 240 [MIB_SDR24] = 0x778, 241 [MIB_SDR25] = 0x77c, 242 [MIB_SDR27] = 0x080, 243 [MIB_SDR28] = 0x084, 244 [MIB_SDR29] = 0x650, 245 [MIB_SDRVEC] = 0x5a8, 246 [MIB_SDR31] = 0x55c, 247 [MIB_SDR32] = 0x7a8, 248 [MIB_SDRMUBF] = 0x7ac, 249 [MIB_DR8] = 0x56c, 250 [MIB_DR9] = 0x570, 251 [MIB_DR11] = 0x574, 252 [MIB_MB_SDR0] = 0x688, 253 [MIB_MB_SDR1] = 0x690, 254 [TX_AGG_CNT] = 0x7dc, 255 [TX_AGG_CNT2] = 0x7ec, 256 [MIB_ARNG] = 0x0b0, 257 [WTBLON_TOP_WDUCR] = 0x200, 258 [WTBL_UPDATE] = 0x230, 259 [PLE_FL_Q_EMPTY] = 0x360, 260 [PLE_FL_Q_CTRL] = 0x3e0, 261 [PLE_AC_QEMPTY] = 0x600, 262 [PLE_FREEPG_CNT] = 0x380, 263 [PLE_FREEPG_HEAD_TAIL] = 0x384, 264 [PLE_PG_HIF_GROUP] = 0x00c, 265 [PLE_HIF_PG_INFO] = 0x388, 266 [AC_OFFSET] = 0x080, 267 [ETBF_PAR_RPT0] = 0x100, 268}; 269 270static const struct mt76_connac_reg_map mt7915_reg_map[] = { 271 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 272 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */ 273 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 274 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 275 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 276 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 277 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 278 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 279 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 280 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 281 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 282 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 283 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 284 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 285 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 286 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 287 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 288 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 289 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 290 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 291 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 292 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 293 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 294 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 295 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 296 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 297 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 298 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 299 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 300 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 301 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 302 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 303 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 304 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 305 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 306 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 307 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 308 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 309 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 310 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 311 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 312 { 0x0, 0x0, 0x0 }, /* imply end of search */ 313}; 314 315static const struct mt76_connac_reg_map mt7916_reg_map[] = { 316 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 317 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 318 { 0x56000000, 0x04000, 0x01000 }, /* WFDMA_2 (Reserved) */ 319 { 0x57000000, 0x05000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 320 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 321 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 322 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 323 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 324 { 0x820cc000, 0x0e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 325 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 326 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 327 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 328 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 329 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 330 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 331 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 332 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 333 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 334 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 335 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 336 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 337 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 338 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 339 { 0x820ca000, 0x26000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 340 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 341 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 342 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure cr) */ 343 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 344 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 345 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 346 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 347 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 348 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 349 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 350 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 351 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 352 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 353 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 354 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 355 { 0x820c4000, 0xa8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 356 { 0x820b0000, 0xae000, 0x01000 }, /* [APB2] WFSYS_ON */ 357 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 358 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 359 { 0x0, 0x0, 0x0 }, /* imply end of search */ 360}; 361 362static const struct mt76_connac_reg_map mt7986_reg_map[] = { 363 { 0x54000000, 0x402000, 0x01000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 364 { 0x55000000, 0x403000, 0x01000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 365 { 0x56000000, 0x404000, 0x01000 }, /* WFDMA_2 (Reserved) */ 366 { 0x57000000, 0x405000, 0x01000 }, /* WFDMA_3 (MCU wrap CR) */ 367 { 0x58000000, 0x406000, 0x01000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */ 368 { 0x59000000, 0x407000, 0x01000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */ 369 { 0x820c0000, 0x408000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 370 { 0x820c8000, 0x40c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 371 { 0x820cc000, 0x40e000, 0x02000 }, /* WF_UMAC_TOP (PP) */ 372 { 0x820e0000, 0x420000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 373 { 0x820e1000, 0x420400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 374 { 0x820e2000, 0x420800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 375 { 0x820e3000, 0x420c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 376 { 0x820e4000, 0x421000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 377 { 0x820e5000, 0x421400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 378 { 0x820ce000, 0x421c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 379 { 0x820e7000, 0x421e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 380 { 0x820cf000, 0x422000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 381 { 0x820e9000, 0x423400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 382 { 0x820ea000, 0x424000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 383 { 0x820eb000, 0x424200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 384 { 0x820ec000, 0x424600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 385 { 0x820ed000, 0x424800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 386 { 0x820ca000, 0x426000, 0x02000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 387 { 0x820d0000, 0x430000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 388 { 0x00400000, 0x480000, 0x10000 }, /* WF_MCU_SYSRAM */ 389 { 0x00410000, 0x490000, 0x10000 }, /* WF_MCU_SYSRAM */ 390 { 0x820f0000, 0x4a0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 391 { 0x820f1000, 0x4a0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 392 { 0x820f2000, 0x4a0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 393 { 0x820f3000, 0x4a0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 394 { 0x820f4000, 0x4a1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 395 { 0x820f5000, 0x4a1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 396 { 0x820f7000, 0x4a1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 397 { 0x820f9000, 0x4a3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 398 { 0x820fa000, 0x4a4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 399 { 0x820fb000, 0x4a4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 400 { 0x820fc000, 0x4a4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 401 { 0x820fd000, 0x4a4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 402 { 0x820c4000, 0x4a8000, 0x01000 }, /* WF_LMAC_TOP (WF_UWTBL ) */ 403 { 0x820b0000, 0x4ae000, 0x01000 }, /* [APB2] WFSYS_ON */ 404 { 0x80020000, 0x4b0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 405 { 0x81020000, 0x4c0000, 0x10000 }, /* WF_TOP_MISC_ON */ 406 { 0x89000000, 0x4d0000, 0x01000 }, /* WF_MCU_CFG_ON */ 407 { 0x89010000, 0x4d1000, 0x01000 }, /* WF_MCU_CIRQ */ 408 { 0x89020000, 0x4d2000, 0x01000 }, /* WF_MCU_GPT */ 409 { 0x89030000, 0x4d3000, 0x01000 }, /* WF_MCU_WDT */ 410 { 0x80010000, 0x4d4000, 0x01000 }, /* WF_AXIDMA */ 411 { 0x0, 0x0, 0x0 }, /* imply end of search */ 412}; 413 414static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr) 415{ 416 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 417 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 418 u32 l1_remap; 419 420 if (is_mt798x(&dev->mt76)) 421 return MT_CONN_INFRA_OFFSET(addr); 422 423 l1_remap = is_mt7915(&dev->mt76) ? 424 MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916; 425 426 dev->bus_ops->rmw(&dev->mt76, l1_remap, 427 MT_HIF_REMAP_L1_MASK, 428 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 429 /* use read to push write */ 430 dev->bus_ops->rr(&dev->mt76, l1_remap); 431 432 return MT_HIF_REMAP_BASE_L1 + offset; 433} 434 435static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr) 436{ 437 u32 offset, base; 438 439 if (is_mt7915(&dev->mt76)) { 440 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 441 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 442 443 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 444 MT_HIF_REMAP_L2_MASK, 445 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 446 447 /* use read to push write */ 448 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 449 } else { 450 u32 ofs = is_mt798x(&dev->mt76) ? 0x400000 : 0; 451 452 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr); 453 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr); 454 455 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs, 456 MT_HIF_REMAP_L2_MASK_MT7916, 457 FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base)); 458 459 /* use read to push write */ 460 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs); 461 462 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs); 463 } 464 465 return offset; 466} 467 468static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr) 469{ 470 int i; 471 472 if (addr < 0x100000) 473 return addr; 474 475 if (!dev->reg.map) { 476 dev_err(dev->mt76.dev, "err: reg_map is null\n"); 477 return addr; 478 } 479 480 for (i = 0; i < dev->reg.map_size; i++) { 481 u32 ofs; 482 483 if (addr < dev->reg.map[i].phys) 484 continue; 485 486 ofs = addr - dev->reg.map[i].phys; 487 if (ofs > dev->reg.map[i].size) 488 continue; 489 490 return dev->reg.map[i].maps + ofs; 491 } 492 493 return 0; 494} 495 496static u32 __mt7915_reg_remap_addr(struct mt7915_dev *dev, u32 addr) 497{ 498 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 499 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 500 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 501 return mt7915_reg_map_l1(dev, addr); 502 503 if (dev_is_pci(dev->mt76.dev) && 504 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 505 addr >= MT_CBTOP2_PHY_START)) 506 return mt7915_reg_map_l1(dev, addr); 507 508 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 509 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 510 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 511 return mt7915_reg_map_l1(dev, addr); 512 } 513 514 return mt7915_reg_map_l2(dev, addr); 515} 516 517void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset, 518 size_t len) 519{ 520 u32 addr = __mt7915_reg_addr(dev, offset); 521 522 if (addr) { 523 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 524 return; 525 } 526 527 spin_lock_bh(&dev->reg_lock); 528 memcpy_fromio(buf, dev->mt76.mmio.regs + 529 __mt7915_reg_remap_addr(dev, offset), len); 530 spin_unlock_bh(&dev->reg_lock); 531} 532 533static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset) 534{ 535 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 536 u32 addr = __mt7915_reg_addr(dev, offset), val; 537 538 if (addr) 539 return dev->bus_ops->rr(mdev, addr); 540 541 spin_lock_bh(&dev->reg_lock); 542 val = dev->bus_ops->rr(mdev, __mt7915_reg_remap_addr(dev, offset)); 543 spin_unlock_bh(&dev->reg_lock); 544 545 return val; 546} 547 548static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val) 549{ 550 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 551 u32 addr = __mt7915_reg_addr(dev, offset); 552 553 if (addr) { 554 dev->bus_ops->wr(mdev, addr, val); 555 return; 556 } 557 558 spin_lock_bh(&dev->reg_lock); 559 dev->bus_ops->wr(mdev, __mt7915_reg_remap_addr(dev, offset), val); 560 spin_unlock_bh(&dev->reg_lock); 561} 562 563static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 564{ 565 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 566 u32 addr = __mt7915_reg_addr(dev, offset); 567 568 if (addr) 569 return dev->bus_ops->rmw(mdev, addr, mask, val); 570 571 spin_lock_bh(&dev->reg_lock); 572 val = dev->bus_ops->rmw(mdev, __mt7915_reg_remap_addr(dev, offset), mask, val); 573 spin_unlock_bh(&dev->reg_lock); 574 575 return val; 576} 577 578#ifdef CONFIG_NET_MEDIATEK_SOC_WED 579static void mt7915_mmio_wed_update_rx_stats(struct mtk_wed_device *wed, 580 struct mtk_wed_wo_rx_stats *stats) 581{ 582 int idx = le16_to_cpu(stats->wlan_idx); 583 struct mt7915_dev *dev; 584 struct mt76_wcid *wcid; 585 586 dev = container_of(wed, struct mt7915_dev, mt76.mmio.wed); 587 588 if (idx >= mt7915_wtbl_size(dev)) 589 return; 590 591 rcu_read_lock(); 592 593 wcid = rcu_dereference(dev->mt76.wcid[idx]); 594 if (wcid) { 595 wcid->stats.rx_bytes += le32_to_cpu(stats->rx_byte_cnt); 596 wcid->stats.rx_packets += le32_to_cpu(stats->rx_pkt_cnt); 597 wcid->stats.rx_errors += le32_to_cpu(stats->rx_err_cnt); 598 wcid->stats.rx_drops += le32_to_cpu(stats->rx_drop_cnt); 599 } 600 601 rcu_read_unlock(); 602} 603 604static int mt7915_mmio_wed_reset(struct mtk_wed_device *wed) 605{ 606 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); 607 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 608 struct mt76_phy *mphy = &dev->mphy; 609 int ret; 610 611 ASSERT_RTNL(); 612 613 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) 614 return -EBUSY; 615 616 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L1, 617 mphy->band_idx); 618 if (ret) 619 goto out; 620 621 rtnl_unlock(); 622 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { 623 dev_err(mdev->dev, "wed reset timeout\n"); 624 ret = -ETIMEDOUT; 625 } 626 rtnl_lock(); 627out: 628 clear_bit(MT76_STATE_WED_RESET, &mphy->state); 629 630 return ret; 631} 632#endif 633 634int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 635 bool pci, int *irq) 636{ 637#ifdef CONFIG_NET_MEDIATEK_SOC_WED 638 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 639 int ret; 640 641 if (!wed_enable) 642 return 0; 643 644 if (pci) { 645 struct pci_dev *pci_dev = pdev_ptr; 646 647 wed->wlan.pci_dev = pci_dev; 648 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 649 wed->wlan.base = devm_ioremap(dev->mt76.dev, 650 pci_resource_start(pci_dev, 0), 651 pci_resource_len(pci_dev, 0)); 652 wed->wlan.phy_base = pci_resource_start(pci_dev, 0); 653 wed->wlan.wpdma_int = pci_resource_start(pci_dev, 0) + 654 MT_INT_WED_SOURCE_CSR; 655 wed->wlan.wpdma_mask = pci_resource_start(pci_dev, 0) + 656 MT_INT_WED_MASK_CSR; 657 wed->wlan.wpdma_phys = pci_resource_start(pci_dev, 0) + 658 MT_WFDMA_EXT_CSR_BASE; 659 wed->wlan.wpdma_tx = pci_resource_start(pci_dev, 0) + 660 MT_TXQ_WED_RING_BASE; 661 wed->wlan.wpdma_txfree = pci_resource_start(pci_dev, 0) + 662 MT_RXQ_WED_RING_BASE; 663 wed->wlan.wpdma_rx_glo = pci_resource_start(pci_dev, 0) + 664 MT_WPDMA_GLO_CFG; 665 wed->wlan.wpdma_rx = pci_resource_start(pci_dev, 0) + 666 MT_RXQ_WED_DATA_RING_BASE; 667 } else { 668 struct platform_device *plat_dev = pdev_ptr; 669 struct resource *res; 670 671 res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); 672 if (!res) 673 return 0; 674 675 wed->wlan.platform_dev = plat_dev; 676 wed->wlan.bus_type = MTK_WED_BUS_AXI; 677 wed->wlan.base = devm_ioremap(dev->mt76.dev, res->start, 678 resource_size(res)); 679 wed->wlan.phy_base = res->start; 680 wed->wlan.wpdma_int = res->start + MT_INT_SOURCE_CSR; 681 wed->wlan.wpdma_mask = res->start + MT_INT_MASK_CSR; 682 wed->wlan.wpdma_tx = res->start + MT_TXQ_WED_RING_BASE; 683 wed->wlan.wpdma_txfree = res->start + MT_RXQ_WED_RING_BASE; 684 wed->wlan.wpdma_rx_glo = res->start + MT_WPDMA_GLO_CFG; 685 wed->wlan.wpdma_rx = res->start + MT_RXQ_WED_DATA_RING_BASE; 686 } 687 wed->wlan.nbuf = MT7915_HW_TOKEN_SIZE; 688 wed->wlan.tx_tbit[0] = is_mt7915(&dev->mt76) ? 4 : 30; 689 wed->wlan.tx_tbit[1] = is_mt7915(&dev->mt76) ? 5 : 31; 690 wed->wlan.txfree_tbit = is_mt798x(&dev->mt76) ? 2 : 1; 691 wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf; 692 wed->wlan.wcid_512 = !is_mt7915(&dev->mt76); 693 694 wed->wlan.rx_nbuf = 65536; 695 wed->wlan.rx_npkt = MT7915_WED_RX_TOKEN_SIZE; 696 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 697 if (is_mt7915(&dev->mt76)) { 698 wed->wlan.rx_tbit[0] = 16; 699 wed->wlan.rx_tbit[1] = 17; 700 } else if (is_mt798x(&dev->mt76)) { 701 wed->wlan.rx_tbit[0] = 22; 702 wed->wlan.rx_tbit[1] = 23; 703 } else { 704 wed->wlan.rx_tbit[0] = 18; 705 wed->wlan.rx_tbit[1] = 19; 706 } 707 708 wed->wlan.init_buf = mt7915_wed_init_buf; 709 wed->wlan.offload_enable = mt76_wed_offload_enable; 710 wed->wlan.offload_disable = mt76_wed_offload_disable; 711 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf; 712 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf; 713 wed->wlan.update_wo_rx_stats = mt7915_mmio_wed_update_rx_stats; 714 wed->wlan.reset = mt7915_mmio_wed_reset; 715 wed->wlan.reset_complete = mt76_wed_reset_complete; 716 717 dev->mt76.rx_token_size = wed->wlan.rx_npkt; 718 719 if (mtk_wed_device_attach(wed)) 720 return 0; 721 722 *irq = wed->irq; 723 dev->mt76.dma_dev = wed->dev; 724 725 ret = dma_set_mask(wed->dev, DMA_BIT_MASK(32)); 726 if (ret) 727 return ret; 728 729 return 1; 730#else 731 return 0; 732#endif 733} 734 735static int mt7915_mmio_init(struct mt76_dev *mdev, 736 void __iomem *mem_base, 737 u32 device_id) 738{ 739 struct mt76_bus_ops *bus_ops; 740 struct mt7915_dev *dev; 741 742 dev = container_of(mdev, struct mt7915_dev, mt76); 743 mt76_mmio_init(&dev->mt76, mem_base); 744 spin_lock_init(&dev->reg_lock); 745 746 switch (device_id) { 747 case 0x7915: 748 dev->reg.reg_rev = mt7915_reg; 749 dev->reg.offs_rev = mt7915_offs; 750 dev->reg.map = mt7915_reg_map; 751 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map); 752 break; 753 case 0x7906: 754 dev->reg.reg_rev = mt7916_reg; 755 dev->reg.offs_rev = mt7916_offs; 756 dev->reg.map = mt7916_reg_map; 757 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map); 758 break; 759 case 0x7981: 760 case 0x7986: 761 dev->reg.reg_rev = mt7986_reg; 762 dev->reg.offs_rev = mt7916_offs; 763 dev->reg.map = mt7986_reg_map; 764 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map); 765 break; 766 default: 767 return -EINVAL; 768 } 769 770 dev->bus_ops = dev->mt76.bus; 771 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 772 GFP_KERNEL); 773 if (!bus_ops) 774 return -ENOMEM; 775 776 bus_ops->rr = mt7915_rr; 777 bus_ops->wr = mt7915_wr; 778 bus_ops->rmw = mt7915_rmw; 779 dev->mt76.bus = bus_ops; 780 781 mdev->rev = (device_id << 16) | 782 (mt76_rr(dev, MT_HW_REV) & 0xff); 783 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 784 785 return 0; 786} 787 788void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, 789 bool write_reg, 790 u32 clear, u32 set) 791{ 792 struct mt76_dev *mdev = &dev->mt76; 793 unsigned long flags; 794 795 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 796 797 mdev->mmio.irqmask &= ~clear; 798 mdev->mmio.irqmask |= set; 799 800 if (write_reg) { 801 if (mtk_wed_device_active(&mdev->mmio.wed)) 802 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 803 mdev->mmio.irqmask); 804 else 805 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 806 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 807 } 808 809 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 810} 811 812static void mt7915_rx_poll_complete(struct mt76_dev *mdev, 813 enum mt76_rxq_id q) 814{ 815 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 816 817 mt7915_irq_enable(dev, MT_INT_RX(q)); 818} 819 820/* TODO: support 2/4/6/8 MSI-X vectors */ 821static void mt7915_irq_tasklet(struct tasklet_struct *t) 822{ 823 struct mt7915_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet); 824 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 825 u32 intr, intr1, mask; 826 827 if (mtk_wed_device_active(wed)) { 828 mtk_wed_device_irq_set_mask(wed, 0); 829 if (dev->hif2) 830 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 831 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 832 } else { 833 mt76_wr(dev, MT_INT_MASK_CSR, 0); 834 if (dev->hif2) 835 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 836 837 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 838 intr &= dev->mt76.mmio.irqmask; 839 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 840 } 841 842 if (dev->hif2) { 843 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 844 intr1 &= dev->mt76.mmio.irqmask; 845 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 846 847 intr |= intr1; 848 } 849 850 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 851 852 mask = intr & MT_INT_RX_DONE_ALL; 853 if (intr & MT_INT_TX_DONE_MCU) 854 mask |= MT_INT_TX_DONE_MCU; 855 856 mt7915_irq_disable(dev, mask); 857 858 if (intr & MT_INT_TX_DONE_MCU) 859 napi_schedule(&dev->mt76.tx_napi); 860 861 if (intr & MT_INT_RX(MT_RXQ_MAIN)) 862 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 863 864 if (intr & MT_INT_RX(MT_RXQ_BAND1)) 865 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); 866 867 if (intr & MT_INT_RX(MT_RXQ_MCU)) 868 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 869 870 if (intr & MT_INT_RX(MT_RXQ_MCU_WA)) 871 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 872 873 if (!is_mt7915(&dev->mt76) && 874 (intr & MT_INT_RX(MT_RXQ_MAIN_WA))) 875 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]); 876 877 if (intr & MT_INT_RX(MT_RXQ_BAND1_WA)) 878 napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]); 879 880 if (intr & MT_INT_MCU_CMD) { 881 u32 val = mt76_rr(dev, MT_MCU_CMD); 882 883 mt76_wr(dev, MT_MCU_CMD, val); 884 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 885 dev->recovery.state = val; 886 mt7915_reset(dev); 887 } 888 } 889} 890 891irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) 892{ 893 struct mt7915_dev *dev = dev_instance; 894 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 895 896 if (mtk_wed_device_active(wed)) 897 mtk_wed_device_irq_set_mask(wed, 0); 898 else 899 mt76_wr(dev, MT_INT_MASK_CSR, 0); 900 901 if (dev->hif2) 902 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 903 904 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 905 return IRQ_NONE; 906 907 tasklet_schedule(&dev->mt76.irq_tasklet); 908 909 return IRQ_HANDLED; 910} 911 912struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 913 void __iomem *mem_base, u32 device_id) 914{ 915 static const struct mt76_driver_ops drv_ops = { 916 /* txwi_size = txd size + txp size */ 917 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 918 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 919 MT_DRV_AMSDU_OFFLOAD, 920 .survey_flags = SURVEY_INFO_TIME_TX | 921 SURVEY_INFO_TIME_RX | 922 SURVEY_INFO_TIME_BSS_RX, 923 .token_size = MT7915_TOKEN_SIZE, 924 .tx_prepare_skb = mt7915_tx_prepare_skb, 925 .tx_complete_skb = mt76_connac_tx_complete_skb, 926 .rx_skb = mt7915_queue_rx_skb, 927 .rx_check = mt7915_rx_check, 928 .rx_poll_complete = mt7915_rx_poll_complete, 929 .sta_add = mt7915_mac_sta_add, 930 .sta_remove = mt7915_mac_sta_remove, 931 .update_survey = mt7915_update_channel, 932 }; 933 struct mt7915_dev *dev; 934 struct mt76_dev *mdev; 935 int ret; 936 937 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops); 938 if (!mdev) 939 return ERR_PTR(-ENOMEM); 940 941 dev = container_of(mdev, struct mt7915_dev, mt76); 942 943 ret = mt7915_mmio_init(mdev, mem_base, device_id); 944 if (ret) 945 goto error; 946 947 tasklet_setup(&mdev->irq_tasklet, mt7915_irq_tasklet); 948 949 return dev; 950 951error: 952 mt76_free_device(&dev->mt76); 953 954 return ERR_PTR(ret); 955} 956 957static int __init mt7915_init(void) 958{ 959 int ret; 960 961 ret = pci_register_driver(&mt7915_hif_driver); 962 if (ret) 963 return ret; 964 965 ret = pci_register_driver(&mt7915_pci_driver); 966 if (ret) 967 goto error_pci; 968 969 if (IS_ENABLED(CONFIG_MT798X_WMAC)) { 970 ret = platform_driver_register(&mt798x_wmac_driver); 971 if (ret) 972 goto error_wmac; 973 } 974 975 return 0; 976 977error_wmac: 978 pci_unregister_driver(&mt7915_pci_driver); 979error_pci: 980 pci_unregister_driver(&mt7915_hif_driver); 981 982 return ret; 983} 984 985static void __exit mt7915_exit(void) 986{ 987 if (IS_ENABLED(CONFIG_MT798X_WMAC)) 988 platform_driver_unregister(&mt798x_wmac_driver); 989 990 pci_unregister_driver(&mt7915_pci_driver); 991 pci_unregister_driver(&mt7915_hif_driver); 992} 993 994module_init(mt7915_init); 995module_exit(mt7915_exit); 996MODULE_DESCRIPTION("MediaTek MT7915E MMIO helpers"); 997MODULE_LICENSE("Dual BSD/GPL"); 998