1// SPDX-License-Identifier: ISC 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#include <linux/etherdevice.h> 5#include <linux/hwmon.h> 6#include <linux/hwmon-sysfs.h> 7#include <linux/of.h> 8#include <linux/thermal.h> 9#include "mt7915.h" 10#include "mac.h" 11#include "mcu.h" 12#include "coredump.h" 13#include "eeprom.h" 14 15static const struct ieee80211_iface_limit if_limits[] = { 16 { 17 .max = 1, 18 .types = BIT(NL80211_IFTYPE_ADHOC) 19 }, { 20 .max = 16, 21 .types = BIT(NL80211_IFTYPE_AP) 22#ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24#endif 25 }, { 26 .max = MT7915_MAX_INTERFACES, 27 .types = BIT(NL80211_IFTYPE_STATION) 28 } 29}; 30 31static const struct ieee80211_iface_combination if_comb[] = { 32 { 33 .limits = if_limits, 34 .n_limits = ARRAY_SIZE(if_limits), 35 .max_interfaces = MT7915_MAX_INTERFACES, 36 .num_different_channels = 1, 37 .beacon_int_infra_match = true, 38 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 39 BIT(NL80211_CHAN_WIDTH_20) | 40 BIT(NL80211_CHAN_WIDTH_40) | 41 BIT(NL80211_CHAN_WIDTH_80) | 42 BIT(NL80211_CHAN_WIDTH_160), 43 } 44}; 45 46static ssize_t mt7915_thermal_temp_show(struct device *dev, 47 struct device_attribute *attr, 48 char *buf) 49{ 50 struct mt7915_phy *phy = dev_get_drvdata(dev); 51 int i = to_sensor_dev_attr(attr)->index; 52 int temperature; 53 54 switch (i) { 55 case 0: 56 temperature = mt7915_mcu_get_temperature(phy); 57 if (temperature < 0) 58 return temperature; 59 /* display in millidegree celcius */ 60 return sprintf(buf, "%u\n", temperature * 1000); 61 case 1: 62 case 2: 63 return sprintf(buf, "%u\n", 64 phy->throttle_temp[i - 1] * 1000); 65 case 3: 66 return sprintf(buf, "%hhu\n", phy->throttle_state); 67 default: 68 return -EINVAL; 69 } 70} 71 72static ssize_t mt7915_thermal_temp_store(struct device *dev, 73 struct device_attribute *attr, 74 const char *buf, size_t count) 75{ 76 struct mt7915_phy *phy = dev_get_drvdata(dev); 77 int ret, i = to_sensor_dev_attr(attr)->index; 78 long val; 79 80 ret = kstrtol(buf, 10, &val); 81 if (ret < 0) 82 return ret; 83 84 mutex_lock(&phy->dev->mt76.mutex); 85 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130); 86 87 if ((i - 1 == MT7915_CRIT_TEMP_IDX && 88 val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) || 89 (i - 1 == MT7915_MAX_TEMP_IDX && 90 val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) { 91 dev_err(phy->dev->mt76.dev, 92 "temp1_max shall be greater than temp1_crit."); 93 mutex_unlock(&phy->dev->mt76.mutex); 94 return -EINVAL; 95 } 96 97 phy->throttle_temp[i - 1] = val; 98 mutex_unlock(&phy->dev->mt76.mutex); 99 100 ret = mt7915_mcu_set_thermal_protect(phy); 101 if (ret) 102 return ret; 103 104 return count; 105} 106 107static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0); 108static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1); 109static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2); 110static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3); 111 112static struct attribute *mt7915_hwmon_attrs[] = { 113 &sensor_dev_attr_temp1_input.dev_attr.attr, 114 &sensor_dev_attr_temp1_crit.dev_attr.attr, 115 &sensor_dev_attr_temp1_max.dev_attr.attr, 116 &sensor_dev_attr_throttle1.dev_attr.attr, 117 NULL, 118}; 119ATTRIBUTE_GROUPS(mt7915_hwmon); 120 121static int 122mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 123 unsigned long *state) 124{ 125 *state = MT7915_CDEV_THROTTLE_MAX; 126 127 return 0; 128} 129 130static int 131mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 132 unsigned long *state) 133{ 134 struct mt7915_phy *phy = cdev->devdata; 135 136 *state = phy->cdev_state; 137 138 return 0; 139} 140 141static int 142mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 143 unsigned long state) 144{ 145 struct mt7915_phy *phy = cdev->devdata; 146 u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state; 147 int ret; 148 149 if (state > MT7915_CDEV_THROTTLE_MAX) { 150 dev_err(phy->dev->mt76.dev, 151 "please specify a valid throttling state\n"); 152 return -EINVAL; 153 } 154 155 if (state == phy->cdev_state) 156 return 0; 157 158 /* 159 * cooling_device convention: 0 = no cooling, more = more cooling 160 * mcu convention: 1 = max cooling, more = less cooling 161 */ 162 ret = mt7915_mcu_set_thermal_throttling(phy, throttling); 163 if (ret) 164 return ret; 165 166 phy->cdev_state = state; 167 168 return 0; 169} 170 171static const struct thermal_cooling_device_ops mt7915_thermal_ops = { 172 .get_max_state = mt7915_thermal_get_max_throttle_state, 173 .get_cur_state = mt7915_thermal_get_cur_throttle_state, 174 .set_cur_state = mt7915_thermal_set_cur_throttle_state, 175}; 176 177static void mt7915_unregister_thermal(struct mt7915_phy *phy) 178{ 179 struct wiphy *wiphy = phy->mt76->hw->wiphy; 180 181 if (!phy->cdev) 182 return; 183 184 sysfs_remove_link(&wiphy->dev.kobj, "cooling_device"); 185 thermal_cooling_device_unregister(phy->cdev); 186} 187 188static int mt7915_thermal_init(struct mt7915_phy *phy) 189{ 190 struct wiphy *wiphy = phy->mt76->hw->wiphy; 191 struct thermal_cooling_device *cdev; 192 struct device *hwmon; 193 const char *name; 194 195 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s", 196 wiphy_name(wiphy)); 197 198 cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops); 199 if (!IS_ERR(cdev)) { 200 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 201 "cooling_device") < 0) 202 thermal_cooling_device_unregister(cdev); 203 else 204 phy->cdev = cdev; 205 } 206 207 /* initialize critical/maximum high temperature */ 208 phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP; 209 phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP; 210 211 if (!IS_REACHABLE(CONFIG_HWMON)) 212 return 0; 213 214 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 215 mt7915_hwmon_groups); 216 return PTR_ERR_OR_ZERO(hwmon); 217} 218 219static void mt7915_led_set_config(struct led_classdev *led_cdev, 220 u8 delay_on, u8 delay_off) 221{ 222 struct mt7915_dev *dev; 223 struct mt76_phy *mphy; 224 u32 val; 225 226 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 227 dev = container_of(mphy->dev, struct mt7915_dev, mt76); 228 229 /* set PWM mode */ 230 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | 231 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | 232 FIELD_PREP(MT_LED_STATUS_ON, delay_on); 233 mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val); 234 mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val); 235 236 /* enable LED */ 237 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 238 239 /* control LED */ 240 val = MT_LED_CTRL_KICK; 241 if (dev->mphy.leds.al) 242 val |= MT_LED_CTRL_POLARITY; 243 if (mphy->band_idx) 244 val |= MT_LED_CTRL_BAND; 245 246 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 247 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 248} 249 250static int mt7915_led_set_blink(struct led_classdev *led_cdev, 251 unsigned long *delay_on, 252 unsigned long *delay_off) 253{ 254 u16 delta_on = 0, delta_off = 0; 255 256#define HW_TICK 10 257#define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 258 259 if (*delay_on) 260 delta_on = TO_HW_TICK(*delay_on); 261 if (*delay_off) 262 delta_off = TO_HW_TICK(*delay_off); 263 264 mt7915_led_set_config(led_cdev, delta_on, delta_off); 265 266 return 0; 267} 268 269static void mt7915_led_set_brightness(struct led_classdev *led_cdev, 270 enum led_brightness brightness) 271{ 272 if (!brightness) 273 mt7915_led_set_config(led_cdev, 0, 0xff); 274 else 275 mt7915_led_set_config(led_cdev, 0xff, 0); 276} 277 278static void __mt7915_init_txpower(struct mt7915_phy *phy, 279 struct ieee80211_supported_band *sband) 280{ 281 struct mt7915_dev *dev = phy->dev; 282 int i, n_chains = hweight16(phy->mt76->chainmask); 283 int nss_delta = mt76_tx_power_nss_delta(n_chains); 284 int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band); 285 struct mt76_power_limits limits; 286 287 for (i = 0; i < sband->n_channels; i++) { 288 struct ieee80211_channel *chan = &sband->channels[i]; 289 u32 target_power = 0; 290 int j; 291 292 for (j = 0; j < n_chains; j++) { 293 u32 val; 294 295 val = mt7915_eeprom_get_target_power(dev, chan, j); 296 target_power = max(target_power, val); 297 } 298 299 target_power += pwr_delta; 300 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 301 &limits, 302 target_power); 303 target_power += nss_delta; 304 target_power = DIV_ROUND_UP(target_power, 2); 305 chan->max_power = min_t(int, chan->max_reg_power, 306 target_power); 307 chan->orig_mpwr = target_power; 308 } 309} 310 311void mt7915_init_txpower(struct mt7915_phy *phy) 312{ 313 if (!phy) 314 return; 315 316 if (phy->mt76->cap.has_2ghz) 317 __mt7915_init_txpower(phy, &phy->mt76->sband_2g.sband); 318 if (phy->mt76->cap.has_5ghz) 319 __mt7915_init_txpower(phy, &phy->mt76->sband_5g.sband); 320 if (phy->mt76->cap.has_6ghz) 321 __mt7915_init_txpower(phy, &phy->mt76->sband_6g.sband); 322} 323 324static void 325mt7915_regd_notifier(struct wiphy *wiphy, 326 struct regulatory_request *request) 327{ 328 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 329 struct mt7915_dev *dev = mt7915_hw_dev(hw); 330 struct mt76_phy *mphy = hw->priv; 331 struct mt7915_phy *phy = mphy->priv; 332 333 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 334 dev->mt76.region = request->dfs_region; 335 336 if (dev->mt76.region == NL80211_DFS_UNSET) 337 mt7915_mcu_rdd_background_enable(phy, NULL); 338 339 mt7915_init_txpower(phy); 340 341 mphy->dfs_state = MT_DFS_STATE_UNKNOWN; 342 mt7915_dfs_init_radar_detector(phy); 343} 344 345static void 346mt7915_init_wiphy(struct mt7915_phy *phy) 347{ 348 struct mt76_phy *mphy = phy->mt76; 349 struct ieee80211_hw *hw = mphy->hw; 350 struct mt76_dev *mdev = &phy->dev->mt76; 351 struct wiphy *wiphy = hw->wiphy; 352 struct mt7915_dev *dev = phy->dev; 353 354 hw->queues = 4; 355 hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 356 hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; 357 hw->netdev_features = NETIF_F_RXCSUM; 358 359 if (mtk_wed_device_active(&mdev->mmio.wed)) 360 hw->netdev_features |= NETIF_F_HW_TC; 361 362 hw->radiotap_timestamp.units_pos = 363 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 364 365 phy->slottime = 9; 366 367 hw->sta_data_size = sizeof(struct mt7915_sta); 368 hw->vif_data_size = sizeof(struct mt7915_vif); 369 370 wiphy->iface_combinations = if_comb; 371 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 372 wiphy->reg_notifier = mt7915_regd_notifier; 373 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 374 wiphy->mbssid_max_interfaces = 16; 375 376 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 377 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 378 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 379 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 380 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 381 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 382 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 383 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 384 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 385 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 386 387 if (!is_mt7915(&dev->mt76)) 388 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); 389 390 if (!mdev->dev->of_node || 391 !of_property_read_bool(mdev->dev->of_node, 392 "mediatek,disable-radar-background")) 393 wiphy_ext_feature_set(wiphy, 394 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 395 396 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 397 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 398 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 399 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 400 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 401 402 hw->max_tx_fragments = 4; 403 404 if (phy->mt76->cap.has_2ghz) { 405 phy->mt76->sband_2g.sband.ht_cap.cap |= 406 IEEE80211_HT_CAP_LDPC_CODING | 407 IEEE80211_HT_CAP_MAX_AMSDU; 408 if (is_mt7915(&dev->mt76)) 409 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 410 IEEE80211_HT_MPDU_DENSITY_4; 411 else 412 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 413 IEEE80211_HT_MPDU_DENSITY_2; 414 } 415 416 if (phy->mt76->cap.has_5ghz) { 417 struct ieee80211_sta_vht_cap *vht_cap; 418 419 vht_cap = &phy->mt76->sband_5g.sband.vht_cap; 420 phy->mt76->sband_5g.sband.ht_cap.cap |= 421 IEEE80211_HT_CAP_LDPC_CODING | 422 IEEE80211_HT_CAP_MAX_AMSDU; 423 424 if (is_mt7915(&dev->mt76)) { 425 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 426 IEEE80211_HT_MPDU_DENSITY_4; 427 428 vht_cap->cap |= 429 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | 430 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 431 432 if (!dev->dbdc_support) 433 vht_cap->cap |= 434 IEEE80211_VHT_CAP_SHORT_GI_160 | 435 FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1); 436 } else { 437 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 438 IEEE80211_HT_MPDU_DENSITY_2; 439 440 vht_cap->cap |= 441 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 442 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK; 443 444 /* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */ 445 vht_cap->cap |= 446 IEEE80211_VHT_CAP_SHORT_GI_160 | 447 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 448 } 449 450 if (!is_mt7915(&dev->mt76) || !dev->dbdc_support) 451 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 452 } 453 454 mt76_set_stream_caps(phy->mt76, true); 455 mt7915_set_stream_vht_txbf_caps(phy); 456 mt7915_set_stream_he_caps(phy); 457 mt7915_init_txpower(phy); 458 459 wiphy->available_antennas_rx = phy->mt76->antenna_mask; 460 wiphy->available_antennas_tx = phy->mt76->antenna_mask; 461 462 /* init led callbacks */ 463 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 464 mphy->leds.cdev.brightness_set = mt7915_led_set_brightness; 465 mphy->leds.cdev.blink_set = mt7915_led_set_blink; 466 } 467} 468 469static void 470mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) 471{ 472 u32 mask, set; 473 474 mt76_rmw_field(dev, MT_TMAC_CTCR0(band), 475 MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f); 476 mt76_set(dev, MT_TMAC_CTCR0(band), 477 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN | 478 MT_TMAC_CTCR0_INS_DDLMT_EN); 479 480 mask = MT_MDP_RCFR0_MCU_RX_MGMT | 481 MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR | 482 MT_MDP_RCFR0_MCU_RX_CTL_BAR; 483 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | 484 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) | 485 FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF); 486 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); 487 488 mask = MT_MDP_RCFR1_MCU_RX_BYPASS | 489 MT_MDP_RCFR1_RX_DROPPED_UCAST | 490 MT_MDP_RCFR1_RX_DROPPED_MCAST; 491 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | 492 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) | 493 FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF); 494 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); 495 496 mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680); 497 498 /* mt7915: disable rx rate report by default due to hw issues */ 499 mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); 500 501 /* clear estimated value of EIFS for Rx duration & OBSS time */ 502 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 503 504 /* clear backoff time for Rx duration */ 505 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 506 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 507 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 508 MT_WF_RMAC_MIB_QOS01_BACKOFF); 509 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 510 MT_WF_RMAC_MIB_QOS23_BACKOFF); 511 512 /* clear backoff time and set software compensation for OBSS time */ 513 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 514 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 515 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 516 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 517 518 /* filter out non-resp frames and get instanstaeous signal reporting */ 519 mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM; 520 set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) | 521 FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3); 522 mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set); 523 524 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 525 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 526 */ 527 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 528 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 529} 530 531static void 532mt7915_init_led_mux(struct mt7915_dev *dev) 533{ 534 if (!IS_ENABLED(CONFIG_MT76_LEDS)) 535 return; 536 537 if (dev->dbdc_support) { 538 switch (mt76_chip(&dev->mt76)) { 539 case 0x7915: 540 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 541 GENMASK(11, 8), 4); 542 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 543 GENMASK(11, 8), 4); 544 break; 545 case 0x7986: 546 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 547 GENMASK(7, 4), 1); 548 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 549 GENMASK(11, 8), 1); 550 break; 551 case 0x7916: 552 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 553 GENMASK(27, 24), 3); 554 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 555 GENMASK(31, 28), 3); 556 break; 557 default: 558 break; 559 } 560 } else if (dev->mphy.leds.pin) { 561 switch (mt76_chip(&dev->mt76)) { 562 case 0x7915: 563 mt76_rmw_field(dev, MT_LED_GPIO_MUX3, 564 GENMASK(11, 8), 4); 565 break; 566 case 0x7986: 567 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 568 GENMASK(11, 8), 1); 569 break; 570 case 0x7916: 571 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 572 GENMASK(31, 28), 3); 573 break; 574 default: 575 break; 576 } 577 } else { 578 switch (mt76_chip(&dev->mt76)) { 579 case 0x7915: 580 mt76_rmw_field(dev, MT_LED_GPIO_MUX2, 581 GENMASK(11, 8), 4); 582 break; 583 case 0x7986: 584 mt76_rmw_field(dev, MT_LED_GPIO_MUX0, 585 GENMASK(7, 4), 1); 586 break; 587 case 0x7916: 588 mt76_rmw_field(dev, MT_LED_GPIO_MUX1, 589 GENMASK(27, 24), 3); 590 break; 591 default: 592 break; 593 } 594 } 595} 596 597void mt7915_mac_init(struct mt7915_dev *dev) 598{ 599 int i; 600 u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680; 601 602 /* config pse qid6 wfdma port selection */ 603 if (!is_mt7915(&dev->mt76) && dev->hif2) 604 mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0, 605 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK); 606 607 mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len); 608 609 if (!is_mt7915(&dev->mt76)) 610 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 611 else 612 mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY); 613 614 /* enable hardware de-agg */ 615 mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN); 616 617 for (i = 0; i < mt7915_wtbl_size(dev); i++) 618 mt7915_mac_wtbl_update(dev, i, 619 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 620 for (i = 0; i < 2; i++) 621 mt7915_mac_init_band(dev, i); 622 623 mt7915_init_led_mux(dev); 624} 625 626int mt7915_txbf_init(struct mt7915_dev *dev) 627{ 628 int ret; 629 630 if (dev->dbdc_support) { 631 ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE); 632 if (ret) 633 return ret; 634 } 635 636 /* trigger sounding packets */ 637 ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON); 638 if (ret) 639 return ret; 640 641 /* enable eBF */ 642 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE); 643} 644 645static struct mt7915_phy * 646mt7915_alloc_ext_phy(struct mt7915_dev *dev) 647{ 648 struct mt7915_phy *phy; 649 struct mt76_phy *mphy; 650 651 if (!dev->dbdc_support) 652 return NULL; 653 654 mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1); 655 if (!mphy) 656 return ERR_PTR(-ENOMEM); 657 658 phy = mphy->priv; 659 phy->dev = dev; 660 phy->mt76 = mphy; 661 662 /* Bind main phy to band0 and ext_phy to band1 for dbdc case */ 663 phy->mt76->band_idx = 1; 664 665 return phy; 666} 667 668static int 669mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy) 670{ 671 struct mt76_phy *mphy = phy->mt76; 672 int ret; 673 674 INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work); 675 676 mt7915_eeprom_parse_hw_cap(dev, phy); 677 678 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2, 679 ETH_ALEN); 680 /* Make the secondary PHY MAC address local without overlapping with 681 * the usual MAC address allocation scheme on multiple virtual interfaces 682 */ 683 if (!is_valid_ether_addr(mphy->macaddr)) { 684 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 685 ETH_ALEN); 686 mphy->macaddr[0] |= 2; 687 mphy->macaddr[0] ^= BIT(7); 688 } 689 mt76_eeprom_override(mphy); 690 691 /* init wiphy according to mphy and phy */ 692 mt7915_init_wiphy(phy); 693 694 ret = mt76_register_phy(mphy, true, mt76_rates, 695 ARRAY_SIZE(mt76_rates)); 696 if (ret) 697 return ret; 698 699 ret = mt7915_thermal_init(phy); 700 if (ret) 701 goto unreg; 702 703 mt7915_init_debugfs(phy); 704 705 return 0; 706 707unreg: 708 mt76_unregister_phy(mphy); 709 return ret; 710} 711 712static void mt7915_init_work(struct work_struct *work) 713{ 714 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, 715 init_work); 716 717 mt7915_mcu_set_eeprom(dev); 718 mt7915_mac_init(dev); 719 mt7915_txbf_init(dev); 720} 721 722void mt7915_wfsys_reset(struct mt7915_dev *dev) 723{ 724#define MT_MCU_DUMMY_RANDOM GENMASK(15, 0) 725#define MT_MCU_DUMMY_DEFAULT GENMASK(31, 16) 726 727 if (is_mt7915(&dev->mt76)) { 728 u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON; 729 730 mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM); 731 732 /* change to software control */ 733 val |= MT_TOP_PWR_SW_RST; 734 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 735 736 /* reset wfsys */ 737 val &= ~MT_TOP_PWR_SW_RST; 738 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 739 740 /* release wfsys then mcu re-executes romcode */ 741 val |= MT_TOP_PWR_SW_RST; 742 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 743 744 /* switch to hw control */ 745 val &= ~MT_TOP_PWR_SW_RST; 746 val |= MT_TOP_PWR_HW_CTRL; 747 mt76_wr(dev, MT_TOP_PWR_CTRL, val); 748 749 /* check whether mcu resets to default */ 750 if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR, 751 MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT, 752 1000)) { 753 dev_err(dev->mt76.dev, "wifi subsystem reset failure\n"); 754 return; 755 } 756 757 /* wfsys reset won't clear host registers */ 758 mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE); 759 760 msleep(100); 761 } else if (is_mt798x(&dev->mt76)) { 762 mt7986_wmac_disable(dev); 763 msleep(20); 764 765 mt7986_wmac_enable(dev); 766 msleep(20); 767 } else { 768 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 769 msleep(20); 770 771 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 772 msleep(20); 773 } 774} 775 776static bool mt7915_band_config(struct mt7915_dev *dev) 777{ 778 bool ret = true; 779 780 dev->phy.mt76->band_idx = 0; 781 782 if (is_mt798x(&dev->mt76)) { 783 u32 sku = mt7915_check_adie(dev, true); 784 785 /* 786 * for mt7986, dbdc support is determined by the number 787 * of adie chips and the main phy is bound to band1 when 788 * dbdc is disabled. 789 */ 790 if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) { 791 dev->phy.mt76->band_idx = 1; 792 ret = false; 793 } 794 } else { 795 ret = is_mt7915(&dev->mt76) ? 796 !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; 797 } 798 799 return ret; 800} 801 802static int 803mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2) 804{ 805 int ret, idx; 806 807 mt76_wr(dev, MT_INT_MASK_CSR, 0); 808 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 809 810 INIT_WORK(&dev->init_work, mt7915_init_work); 811 812 ret = mt7915_dma_init(dev, phy2); 813 if (ret) 814 return ret; 815 816 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 817 818 ret = mt7915_mcu_init(dev); 819 if (ret) 820 return ret; 821 822 ret = mt7915_eeprom_init(dev); 823 if (ret < 0) 824 return ret; 825 826 if (dev->flash_mode) { 827 ret = mt7915_mcu_apply_group_cal(dev); 828 if (ret) 829 return ret; 830 } 831 832 /* Beacon and mgmt frames should occupy wcid 0 */ 833 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 834 if (idx) 835 return -ENOSPC; 836 837 dev->mt76.global_wcid.idx = idx; 838 dev->mt76.global_wcid.hw_key_idx = -1; 839 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 840 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 841 842 return 0; 843} 844 845void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy) 846{ 847 int sts; 848 u32 *cap; 849 850 if (!phy->mt76->cap.has_5ghz) 851 return; 852 853 sts = hweight8(phy->mt76->chainmask); 854 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 855 856 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 857 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 858 FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 859 sts - 1); 860 861 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 862 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 863 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 864 865 if (sts < 2) 866 return; 867 868 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 869 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 870 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 871 sts - 1); 872} 873 874static void 875mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy, 876 struct ieee80211_sta_he_cap *he_cap, int vif) 877{ 878 struct mt7915_dev *dev = phy->dev; 879 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 880 int sts = hweight8(phy->mt76->chainmask); 881 u8 c, sts_160 = sts; 882 883 /* Can do 1/2 of STS in 160Mhz mode for mt7915 */ 884 if (is_mt7915(&dev->mt76)) { 885 if (!dev->dbdc_support) 886 sts_160 /= 2; 887 else 888 sts_160 = 0; 889 } 890 891#ifdef CONFIG_MAC80211_MESH 892 if (vif == NL80211_IFTYPE_MESH_POINT) 893 return; 894#endif 895 896 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 897 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 898 899 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; 900 if (sts_160) 901 c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 902 elem->phy_cap_info[5] &= ~c; 903 904 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 905 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 906 elem->phy_cap_info[6] &= ~c; 907 908 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 909 910 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US; 911 if (!is_mt7915(&dev->mt76)) 912 c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO | 913 IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO; 914 elem->phy_cap_info[2] |= c; 915 916 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 917 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 918 if (sts_160) 919 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 920 elem->phy_cap_info[4] |= c; 921 922 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 923 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 924 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 925 926 if (vif == NL80211_IFTYPE_STATION) 927 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 928 929 elem->phy_cap_info[6] |= c; 930 931 if (sts < 2) 932 return; 933 934 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 935 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 936 937 if (vif != NL80211_IFTYPE_AP) 938 return; 939 940 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 941 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 942 943 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 944 sts - 1); 945 if (sts_160) 946 c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 947 sts_160 - 1); 948 elem->phy_cap_info[5] |= c; 949 950 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 951 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 952 elem->phy_cap_info[6] |= c; 953 954 if (!is_mt7915(&dev->mt76)) { 955 c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 956 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 957 elem->phy_cap_info[7] |= c; 958 } 959} 960 961static int 962mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band, 963 struct ieee80211_sband_iftype_data *data) 964{ 965 struct mt7915_dev *dev = phy->dev; 966 int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask); 967 u16 mcs_map = 0; 968 u16 mcs_map_160 = 0; 969 u8 nss_160; 970 971 if (!is_mt7915(&dev->mt76)) 972 nss_160 = nss; 973 else if (!dev->dbdc_support) 974 /* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */ 975 nss_160 = nss / 2; 976 else 977 /* Can't do 160MHz with mt7915 dbdc */ 978 nss_160 = 0; 979 980 for (i = 0; i < 8; i++) { 981 if (i < nss) 982 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 983 else 984 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 985 986 if (i < nss_160) 987 mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 988 else 989 mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 990 } 991 992 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 993 struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; 994 struct ieee80211_he_cap_elem *he_cap_elem = 995 &he_cap->he_cap_elem; 996 struct ieee80211_he_mcs_nss_supp *he_mcs = 997 &he_cap->he_mcs_nss_supp; 998 999 switch (i) { 1000 case NL80211_IFTYPE_STATION: 1001 case NL80211_IFTYPE_AP: 1002#ifdef CONFIG_MAC80211_MESH 1003 case NL80211_IFTYPE_MESH_POINT: 1004#endif 1005 break; 1006 default: 1007 continue; 1008 } 1009 1010 data[idx].types_mask = BIT(i); 1011 he_cap->has_he = true; 1012 1013 he_cap_elem->mac_cap_info[0] = 1014 IEEE80211_HE_MAC_CAP0_HTC_HE; 1015 he_cap_elem->mac_cap_info[3] = 1016 IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1017 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1018 he_cap_elem->mac_cap_info[4] = 1019 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1020 1021 if (band == NL80211_BAND_2GHZ) 1022 he_cap_elem->phy_cap_info[0] = 1023 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1024 else if (nss_160) 1025 he_cap_elem->phy_cap_info[0] = 1026 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1027 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1028 else 1029 he_cap_elem->phy_cap_info[0] = 1030 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 1031 1032 he_cap_elem->phy_cap_info[1] = 1033 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1034 he_cap_elem->phy_cap_info[2] = 1035 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1036 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1037 1038 switch (i) { 1039 case NL80211_IFTYPE_AP: 1040 he_cap_elem->mac_cap_info[0] |= 1041 IEEE80211_HE_MAC_CAP0_TWT_RES; 1042 he_cap_elem->mac_cap_info[2] |= 1043 IEEE80211_HE_MAC_CAP2_BSR; 1044 he_cap_elem->mac_cap_info[4] |= 1045 IEEE80211_HE_MAC_CAP4_BQR; 1046 he_cap_elem->mac_cap_info[5] |= 1047 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1048 he_cap_elem->phy_cap_info[3] |= 1049 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1050 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1051 he_cap_elem->phy_cap_info[6] |= 1052 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1053 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1054 he_cap_elem->phy_cap_info[9] |= 1055 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1056 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1057 break; 1058 case NL80211_IFTYPE_STATION: 1059 he_cap_elem->mac_cap_info[1] |= 1060 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1061 1062 if (band == NL80211_BAND_2GHZ) 1063 he_cap_elem->phy_cap_info[0] |= 1064 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1065 else 1066 he_cap_elem->phy_cap_info[0] |= 1067 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1068 1069 he_cap_elem->phy_cap_info[1] |= 1070 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1071 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1072 he_cap_elem->phy_cap_info[3] |= 1073 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1074 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1075 he_cap_elem->phy_cap_info[6] |= 1076 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1077 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1078 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1079 he_cap_elem->phy_cap_info[7] |= 1080 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 1081 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1082 he_cap_elem->phy_cap_info[8] |= 1083 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1084 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1085 if (nss_160) 1086 he_cap_elem->phy_cap_info[8] |= 1087 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1088 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 1089 he_cap_elem->phy_cap_info[9] |= 1090 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1091 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1092 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1093 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1094 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1095 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1096 break; 1097 } 1098 1099 memset(he_mcs, 0, sizeof(*he_mcs)); 1100 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1101 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1102 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160); 1103 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160); 1104 1105 mt7915_set_stream_he_txbf_caps(phy, he_cap, i); 1106 1107 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1108 if (he_cap_elem->phy_cap_info[6] & 1109 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1110 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss); 1111 } else { 1112 he_cap_elem->phy_cap_info[9] |= 1113 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1114 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1115 } 1116 1117 if (band == NL80211_BAND_6GHZ) { 1118 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1119 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1120 1121 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2, 1122 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1123 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1124 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1125 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1126 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1127 1128 data[idx].he_6ghz_capa.capa = cpu_to_le16(cap); 1129 } 1130 1131 idx++; 1132 } 1133 1134 return idx; 1135} 1136 1137void mt7915_set_stream_he_caps(struct mt7915_phy *phy) 1138{ 1139 struct ieee80211_sband_iftype_data *data; 1140 struct ieee80211_supported_band *band; 1141 int n; 1142 1143 if (phy->mt76->cap.has_2ghz) { 1144 data = phy->iftype[NL80211_BAND_2GHZ]; 1145 n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data); 1146 1147 band = &phy->mt76->sband_2g.sband; 1148 _ieee80211_set_sband_iftype_data(band, data, n); 1149 } 1150 1151 if (phy->mt76->cap.has_5ghz) { 1152 data = phy->iftype[NL80211_BAND_5GHZ]; 1153 n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data); 1154 1155 band = &phy->mt76->sband_5g.sband; 1156 _ieee80211_set_sband_iftype_data(band, data, n); 1157 } 1158 1159 if (phy->mt76->cap.has_6ghz) { 1160 data = phy->iftype[NL80211_BAND_6GHZ]; 1161 n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data); 1162 1163 band = &phy->mt76->sband_6g.sband; 1164 _ieee80211_set_sband_iftype_data(band, data, n); 1165 } 1166} 1167 1168static void mt7915_unregister_ext_phy(struct mt7915_dev *dev) 1169{ 1170 struct mt7915_phy *phy = mt7915_ext_phy(dev); 1171 struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1]; 1172 1173 if (!phy) 1174 return; 1175 1176 mt7915_unregister_thermal(phy); 1177 mt76_unregister_phy(mphy); 1178 ieee80211_free_hw(mphy->hw); 1179} 1180 1181static void mt7915_stop_hardware(struct mt7915_dev *dev) 1182{ 1183 mt7915_mcu_exit(dev); 1184 mt76_connac2_tx_token_put(&dev->mt76); 1185 mt7915_dma_cleanup(dev); 1186 tasklet_disable(&dev->mt76.irq_tasklet); 1187 1188 if (is_mt798x(&dev->mt76)) 1189 mt7986_wmac_disable(dev); 1190} 1191 1192int mt7915_register_device(struct mt7915_dev *dev) 1193{ 1194 struct mt7915_phy *phy2; 1195 int ret; 1196 1197 dev->phy.dev = dev; 1198 dev->phy.mt76 = &dev->mt76.phy; 1199 dev->mt76.phy.priv = &dev->phy; 1200 INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work); 1201 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work); 1202 INIT_LIST_HEAD(&dev->sta_rc_list); 1203 INIT_LIST_HEAD(&dev->twt_list); 1204 1205 init_waitqueue_head(&dev->reset_wait); 1206 INIT_WORK(&dev->reset_work, mt7915_mac_reset_work); 1207 INIT_WORK(&dev->dump_work, mt7915_mac_dump_work); 1208 mutex_init(&dev->dump_mutex); 1209 1210 dev->dbdc_support = mt7915_band_config(dev); 1211 1212 phy2 = mt7915_alloc_ext_phy(dev); 1213 if (IS_ERR(phy2)) 1214 return PTR_ERR(phy2); 1215 1216 ret = mt7915_init_hardware(dev, phy2); 1217 if (ret) 1218 goto free_phy2; 1219 1220 mt7915_init_wiphy(&dev->phy); 1221 1222#ifdef CONFIG_NL80211_TESTMODE 1223 dev->mt76.test_ops = &mt7915_testmode_ops; 1224#endif 1225 1226 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1227 ARRAY_SIZE(mt76_rates)); 1228 if (ret) 1229 goto stop_hw; 1230 1231 ret = mt7915_thermal_init(&dev->phy); 1232 if (ret) 1233 goto unreg_dev; 1234 1235 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1236 1237 if (phy2) { 1238 ret = mt7915_register_ext_phy(dev, phy2); 1239 if (ret) 1240 goto unreg_thermal; 1241 } 1242 1243 dev->recovery.hw_init_done = true; 1244 1245 ret = mt7915_init_debugfs(&dev->phy); 1246 if (ret) 1247 goto unreg_thermal; 1248 1249 ret = mt7915_coredump_register(dev); 1250 if (ret) 1251 goto unreg_thermal; 1252 1253 return 0; 1254 1255unreg_thermal: 1256 mt7915_unregister_thermal(&dev->phy); 1257unreg_dev: 1258 mt76_unregister_device(&dev->mt76); 1259stop_hw: 1260 mt7915_stop_hardware(dev); 1261free_phy2: 1262 if (phy2) 1263 ieee80211_free_hw(phy2->mt76->hw); 1264 return ret; 1265} 1266 1267void mt7915_unregister_device(struct mt7915_dev *dev) 1268{ 1269 mt7915_unregister_ext_phy(dev); 1270 mt7915_coredump_unregister(dev); 1271 mt7915_unregister_thermal(&dev->phy); 1272 mt76_unregister_device(&dev->mt76); 1273 mt7915_stop_hardware(dev); 1274 1275 mt76_free_device(&dev->mt76); 1276} 1277