1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * NXP Wireless LAN device driver: PCIE specific handling 4 * 5 * Copyright 2011-2020 NXP 6 */ 7 8#include <linux/iopoll.h> 9#include <linux/firmware.h> 10 11#include "decl.h" 12#include "ioctl.h" 13#include "util.h" 14#include "fw.h" 15#include "main.h" 16#include "wmm.h" 17#include "11n.h" 18#include "pcie.h" 19#include "pcie_quirks.h" 20 21#define PCIE_VERSION "1.0" 22#define DRV_NAME "Marvell mwifiex PCIe" 23 24static struct mwifiex_if_ops pcie_ops; 25 26static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { 27 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 28 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 29 .cmd_size = PCIE_SCRATCH_2_REG, 30 .fw_status = PCIE_SCRATCH_3_REG, 31 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 32 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 33 .tx_rdptr = PCIE_SCRATCH_6_REG, 34 .tx_wrptr = PCIE_SCRATCH_7_REG, 35 .rx_rdptr = PCIE_SCRATCH_8_REG, 36 .rx_wrptr = PCIE_SCRATCH_9_REG, 37 .evt_rdptr = PCIE_SCRATCH_10_REG, 38 .evt_wrptr = PCIE_SCRATCH_11_REG, 39 .drv_rdy = PCIE_SCRATCH_12_REG, 40 .tx_start_ptr = 0, 41 .tx_mask = MWIFIEX_TXBD_MASK, 42 .tx_wrap_mask = 0, 43 .rx_mask = MWIFIEX_RXBD_MASK, 44 .rx_wrap_mask = 0, 45 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 46 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 47 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, 48 .ring_flag_sop = 0, 49 .ring_flag_eop = 0, 50 .ring_flag_xs_sop = 0, 51 .ring_flag_xs_eop = 0, 52 .ring_tx_start_ptr = 0, 53 .pfu_enabled = 0, 54 .sleep_cookie = 1, 55 .msix_support = 0, 56}; 57 58static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { 59 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 60 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 61 .cmd_size = PCIE_SCRATCH_2_REG, 62 .fw_status = PCIE_SCRATCH_3_REG, 63 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 64 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 65 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, 66 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, 67 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, 68 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, 69 .evt_rdptr = PCIE_SCRATCH_10_REG, 70 .evt_wrptr = PCIE_SCRATCH_11_REG, 71 .drv_rdy = PCIE_SCRATCH_12_REG, 72 .tx_start_ptr = 16, 73 .tx_mask = 0x03FF0000, 74 .tx_wrap_mask = 0x07FF0000, 75 .rx_mask = 0x000003FF, 76 .rx_wrap_mask = 0x000007FF, 77 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, 78 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, 79 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 80 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 81 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 82 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 83 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 84 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 85 .pfu_enabled = 1, 86 .sleep_cookie = 0, 87 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 88 .fw_dump_start = PCIE_SCRATCH_14_REG, 89 .fw_dump_end = 0xcff, 90 .fw_dump_host_ready = 0xee, 91 .fw_dump_read_done = 0xfe, 92 .msix_support = 0, 93}; 94 95static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = { 96 .cmd_addr_lo = PCIE_SCRATCH_0_REG, 97 .cmd_addr_hi = PCIE_SCRATCH_1_REG, 98 .cmd_size = PCIE_SCRATCH_2_REG, 99 .fw_status = PCIE_SCRATCH_3_REG, 100 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, 101 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, 102 .tx_rdptr = 0xC1A4, 103 .tx_wrptr = 0xC174, 104 .rx_rdptr = 0xC174, 105 .rx_wrptr = 0xC1A4, 106 .evt_rdptr = PCIE_SCRATCH_10_REG, 107 .evt_wrptr = PCIE_SCRATCH_11_REG, 108 .drv_rdy = PCIE_SCRATCH_12_REG, 109 .tx_start_ptr = 16, 110 .tx_mask = 0x0FFF0000, 111 .tx_wrap_mask = 0x1FFF0000, 112 .rx_mask = 0x00000FFF, 113 .rx_wrap_mask = 0x00001FFF, 114 .tx_rollover_ind = BIT(28), 115 .rx_rollover_ind = BIT(12), 116 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, 117 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, 118 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, 119 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, 120 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, 121 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, 122 .pfu_enabled = 1, 123 .sleep_cookie = 0, 124 .fw_dump_ctrl = PCIE_SCRATCH_13_REG, 125 .fw_dump_start = PCIE_SCRATCH_14_REG, 126 .fw_dump_end = 0xcff, 127 .fw_dump_host_ready = 0xcc, 128 .fw_dump_read_done = 0xdd, 129 .msix_support = 0, 130}; 131 132static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = { 133 {"ITCM", NULL, 0, 0xF0}, 134 {"DTCM", NULL, 0, 0xF1}, 135 {"SQRAM", NULL, 0, 0xF2}, 136 {"IRAM", NULL, 0, 0xF3}, 137 {"APU", NULL, 0, 0xF4}, 138 {"CIU", NULL, 0, 0xF5}, 139 {"ICU", NULL, 0, 0xF6}, 140 {"MAC", NULL, 0, 0xF7}, 141}; 142 143static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = { 144 {"DUMP", NULL, 0, 0xDD}, 145}; 146 147static const struct mwifiex_pcie_device mwifiex_pcie8766 = { 148 .reg = &mwifiex_reg_8766, 149 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 150 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 151 .can_dump_fw = false, 152 .can_ext_scan = true, 153}; 154 155static const struct mwifiex_pcie_device mwifiex_pcie8897 = { 156 .reg = &mwifiex_reg_8897, 157 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 158 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 159 .can_dump_fw = true, 160 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897, 161 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897), 162 .can_ext_scan = true, 163}; 164 165static const struct mwifiex_pcie_device mwifiex_pcie8997 = { 166 .reg = &mwifiex_reg_8997, 167 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, 168 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 169 .can_dump_fw = true, 170 .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997, 171 .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997), 172 .can_ext_scan = true, 173}; 174 175static const struct of_device_id mwifiex_pcie_of_match_table[] __maybe_unused = { 176 { .compatible = "pci11ab,2b42" }, 177 { .compatible = "pci1b4b,2b42" }, 178 { } 179}; 180 181static int mwifiex_pcie_probe_of(struct device *dev) 182{ 183 if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) { 184 dev_err(dev, "required compatible string missing\n"); 185 return -EINVAL; 186 } 187 188 return 0; 189} 190 191static void mwifiex_pcie_work(struct work_struct *work); 192static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter); 193static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter); 194 195static int 196mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, 197 size_t size, int flags) 198{ 199 struct pcie_service_card *card = adapter->card; 200 struct mwifiex_dma_mapping mapping; 201 202 mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags); 203 if (dma_mapping_error(&card->dev->dev, mapping.addr)) { 204 mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n"); 205 return -1; 206 } 207 mapping.len = size; 208 mwifiex_store_mapping(skb, &mapping); 209 return 0; 210} 211 212static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, 213 struct sk_buff *skb, int flags) 214{ 215 struct pcie_service_card *card = adapter->card; 216 struct mwifiex_dma_mapping mapping; 217 218 mwifiex_get_mapping(skb, &mapping); 219 dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags); 220} 221 222/* 223 * This function writes data into PCIE card register. 224 */ 225static inline void 226mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) 227{ 228 struct pcie_service_card *card = adapter->card; 229 230 iowrite32(data, card->pci_mmap1 + reg); 231} 232 233/* Non-void wrapper needed for read_poll_timeout(). */ 234static inline int 235mwifiex_write_reg_rpt(struct mwifiex_adapter *adapter, int reg, u32 data) 236{ 237 mwifiex_write_reg(adapter, reg, data); 238 return 0; 239} 240 241/* This function reads data from PCIE card register. 242 */ 243static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) 244{ 245 struct pcie_service_card *card = adapter->card; 246 247 *data = ioread32(card->pci_mmap1 + reg); 248 if (*data == 0xffffffff) 249 return 0xffffffff; 250 251 return 0; 252} 253 254/* This function reads u8 data from PCIE card register. */ 255static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter, 256 int reg, u8 *data) 257{ 258 struct pcie_service_card *card = adapter->card; 259 260 *data = ioread8(card->pci_mmap1 + reg); 261 262 return 0; 263} 264 265/* 266 * This function reads sleep cookie and checks if FW is ready 267 */ 268static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter) 269{ 270 u32 cookie_value; 271 struct pcie_service_card *card = adapter->card; 272 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 273 274 if (!reg->sleep_cookie) 275 return true; 276 277 if (card->sleep_cookie_vbase) { 278 cookie_value = get_unaligned_le32(card->sleep_cookie_vbase); 279 mwifiex_dbg(adapter, INFO, 280 "info: ACCESS_HW: sleep cookie=0x%x\n", 281 cookie_value); 282 if (cookie_value == FW_AWAKE_COOKIE) 283 return true; 284 } 285 286 return false; 287} 288 289#ifdef CONFIG_PM_SLEEP 290/* 291 * Kernel needs to suspend all functions separately. Therefore all 292 * registered functions must have drivers with suspend and resume 293 * methods. Failing that the kernel simply removes the whole card. 294 * 295 * If already not suspended, this function allocates and sends a host 296 * sleep activate request to the firmware and turns off the traffic. 297 */ 298static int mwifiex_pcie_suspend(struct device *dev) 299{ 300 struct mwifiex_adapter *adapter; 301 struct pcie_service_card *card = dev_get_drvdata(dev); 302 303 304 /* Might still be loading firmware */ 305 wait_for_completion(&card->fw_done); 306 307 adapter = card->adapter; 308 if (!adapter) { 309 dev_err(dev, "adapter is not valid\n"); 310 return 0; 311 } 312 313 mwifiex_enable_wake(adapter); 314 315 /* Enable the Host Sleep */ 316 if (!mwifiex_enable_hs(adapter)) { 317 mwifiex_dbg(adapter, ERROR, 318 "cmd: failed to suspend\n"); 319 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 320 mwifiex_disable_wake(adapter); 321 return -EFAULT; 322 } 323 324 flush_workqueue(adapter->workqueue); 325 326 /* Indicate device suspended */ 327 set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 328 clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags); 329 330 return 0; 331} 332 333/* 334 * Kernel needs to suspend all functions separately. Therefore all 335 * registered functions must have drivers with suspend and resume 336 * methods. Failing that the kernel simply removes the whole card. 337 * 338 * If already not resumed, this function turns on the traffic and 339 * sends a host sleep cancel request to the firmware. 340 */ 341static int mwifiex_pcie_resume(struct device *dev) 342{ 343 struct mwifiex_adapter *adapter; 344 struct pcie_service_card *card = dev_get_drvdata(dev); 345 346 347 if (!card->adapter) { 348 dev_err(dev, "adapter structure is not valid\n"); 349 return 0; 350 } 351 352 adapter = card->adapter; 353 354 if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) { 355 mwifiex_dbg(adapter, WARN, 356 "Device already resumed\n"); 357 return 0; 358 } 359 360 clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags); 361 362 mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA), 363 MWIFIEX_ASYNC_CMD); 364 mwifiex_disable_wake(adapter); 365 366 return 0; 367} 368#endif 369 370/* 371 * This function probes an mwifiex device and registers it. It allocates 372 * the card structure, enables PCIE function number and initiates the 373 * device registration and initialization procedure by adding a logical 374 * interface. 375 */ 376static int mwifiex_pcie_probe(struct pci_dev *pdev, 377 const struct pci_device_id *ent) 378{ 379 struct pcie_service_card *card; 380 int ret; 381 382 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 383 pdev->vendor, pdev->device, pdev->revision); 384 385 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); 386 if (!card) 387 return -ENOMEM; 388 389 init_completion(&card->fw_done); 390 391 card->dev = pdev; 392 393 if (ent->driver_data) { 394 struct mwifiex_pcie_device *data = (void *)ent->driver_data; 395 card->pcie.reg = data->reg; 396 card->pcie.blksz_fw_dl = data->blksz_fw_dl; 397 card->pcie.tx_buf_size = data->tx_buf_size; 398 card->pcie.can_dump_fw = data->can_dump_fw; 399 card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl; 400 card->pcie.num_mem_types = data->num_mem_types; 401 card->pcie.can_ext_scan = data->can_ext_scan; 402 INIT_WORK(&card->work, mwifiex_pcie_work); 403 } 404 405 /* device tree node parsing and platform specific configuration*/ 406 if (pdev->dev.of_node) { 407 ret = mwifiex_pcie_probe_of(&pdev->dev); 408 if (ret) 409 return ret; 410 } 411 412 /* check quirks */ 413 mwifiex_initialize_quirks(card); 414 415 if (mwifiex_add_card(card, &card->fw_done, &pcie_ops, 416 MWIFIEX_PCIE, &pdev->dev)) { 417 pr_err("%s failed\n", __func__); 418 return -1; 419 } 420 421 return 0; 422} 423 424/* 425 * This function removes the interface and frees up the card structure. 426 */ 427static void mwifiex_pcie_remove(struct pci_dev *pdev) 428{ 429 struct pcie_service_card *card; 430 struct mwifiex_adapter *adapter; 431 struct mwifiex_private *priv; 432 const struct mwifiex_pcie_card_reg *reg; 433 u32 fw_status; 434 435 card = pci_get_drvdata(pdev); 436 437 wait_for_completion(&card->fw_done); 438 439 adapter = card->adapter; 440 if (!adapter || !adapter->priv_num) 441 return; 442 443 reg = card->pcie.reg; 444 if (reg) 445 mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 446 else 447 fw_status = -1; 448 449 if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) { 450 mwifiex_deauthenticate_all(adapter); 451 452 priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY); 453 454 mwifiex_disable_auto_ds(priv); 455 456 mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN); 457 } 458 459 mwifiex_remove_card(adapter); 460} 461 462static void mwifiex_pcie_shutdown(struct pci_dev *pdev) 463{ 464 mwifiex_pcie_remove(pdev); 465 466 return; 467} 468 469static void mwifiex_pcie_coredump(struct device *dev) 470{ 471 struct pci_dev *pdev; 472 struct pcie_service_card *card; 473 474 pdev = container_of(dev, struct pci_dev, dev); 475 card = pci_get_drvdata(pdev); 476 477 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 478 &card->work_flags)) 479 schedule_work(&card->work); 480} 481 482static const struct pci_device_id mwifiex_ids[] = { 483 { 484 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P, 485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 486 .driver_data = (unsigned long)&mwifiex_pcie8766, 487 }, 488 { 489 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897, 490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 491 .driver_data = (unsigned long)&mwifiex_pcie8897, 492 }, 493 { 494 PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 496 .driver_data = (unsigned long)&mwifiex_pcie8997, 497 }, 498 { 499 PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997, 500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 501 .driver_data = (unsigned long)&mwifiex_pcie8997, 502 }, 503 {}, 504}; 505 506MODULE_DEVICE_TABLE(pci, mwifiex_ids); 507 508/* 509 * Cleanup all software without cleaning anything related to PCIe and HW. 510 */ 511static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev) 512{ 513 struct pcie_service_card *card = pci_get_drvdata(pdev); 514 struct mwifiex_adapter *adapter = card->adapter; 515 516 if (!adapter) { 517 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 518 __func__); 519 return; 520 } 521 522 mwifiex_dbg(adapter, INFO, 523 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n", 524 __func__, pdev->vendor, pdev->device, pdev->revision); 525 526 mwifiex_shutdown_sw(adapter); 527 clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags); 528 clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags); 529 530 /* On MS Surface gen4+ devices FLR isn't effective to recover from 531 * hangups, so we power-cycle the card instead. 532 */ 533 if (card->quirks & QUIRK_FW_RST_D3COLD) 534 mwifiex_pcie_reset_d3cold_quirk(pdev); 535 536 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 537 538 card->pci_reset_ongoing = true; 539} 540 541/* 542 * Kernel stores and restores PCIe function context before and after performing 543 * FLR respectively. Reconfigure the software and firmware including firmware 544 * redownload. 545 */ 546static void mwifiex_pcie_reset_done(struct pci_dev *pdev) 547{ 548 struct pcie_service_card *card = pci_get_drvdata(pdev); 549 struct mwifiex_adapter *adapter = card->adapter; 550 int ret; 551 552 if (!adapter) { 553 dev_err(&pdev->dev, "%s: adapter structure is not valid\n", 554 __func__); 555 return; 556 } 557 558 mwifiex_dbg(adapter, INFO, 559 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n", 560 __func__, pdev->vendor, pdev->device, pdev->revision); 561 562 ret = mwifiex_reinit_sw(adapter); 563 if (ret) 564 dev_err(&pdev->dev, "reinit failed: %d\n", ret); 565 else 566 mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__); 567 568 card->pci_reset_ongoing = false; 569} 570 571static const struct pci_error_handlers mwifiex_pcie_err_handler = { 572 .reset_prepare = mwifiex_pcie_reset_prepare, 573 .reset_done = mwifiex_pcie_reset_done, 574}; 575 576#ifdef CONFIG_PM_SLEEP 577/* Power Management Hooks */ 578static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend, 579 mwifiex_pcie_resume); 580#endif 581 582/* PCI Device Driver */ 583static struct pci_driver mwifiex_pcie = { 584 .name = "mwifiex_pcie", 585 .id_table = mwifiex_ids, 586 .probe = mwifiex_pcie_probe, 587 .remove = mwifiex_pcie_remove, 588 .driver = { 589 .coredump = mwifiex_pcie_coredump, 590#ifdef CONFIG_PM_SLEEP 591 .pm = &mwifiex_pcie_pm_ops, 592#endif 593 }, 594 .shutdown = mwifiex_pcie_shutdown, 595 .err_handler = &mwifiex_pcie_err_handler, 596}; 597 598/* 599 * This function adds delay loop to ensure FW is awake before proceeding. 600 */ 601static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter) 602{ 603 int i = 0; 604 605 while (mwifiex_pcie_ok_to_access_hw(adapter)) { 606 i++; 607 usleep_range(10, 20); 608 /* 50ms max wait */ 609 if (i == 5000) 610 break; 611 } 612 613 return; 614} 615 616static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, 617 u32 max_delay_loop_cnt) 618{ 619 struct pcie_service_card *card = adapter->card; 620 u8 *buffer; 621 u32 sleep_cookie, count; 622 struct sk_buff *cmdrsp = card->cmdrsp_buf; 623 624 for (count = 0; count < max_delay_loop_cnt; count++) { 625 dma_sync_single_for_cpu(&card->dev->dev, 626 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 627 sizeof(sleep_cookie), DMA_FROM_DEVICE); 628 buffer = cmdrsp->data; 629 sleep_cookie = get_unaligned_le32(buffer); 630 631 if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) { 632 mwifiex_dbg(adapter, INFO, 633 "sleep cookie found at count %d\n", count); 634 break; 635 } 636 dma_sync_single_for_device(&card->dev->dev, 637 MWIFIEX_SKB_DMA_ADDR(cmdrsp), 638 sizeof(sleep_cookie), 639 DMA_FROM_DEVICE); 640 usleep_range(20, 30); 641 } 642 643 if (count >= max_delay_loop_cnt) 644 mwifiex_dbg(adapter, INFO, 645 "max count reached while accessing sleep cookie\n"); 646} 647 648#define N_WAKEUP_TRIES_SHORT_INTERVAL 15 649#define N_WAKEUP_TRIES_LONG_INTERVAL 35 650 651/* This function wakes up the card by reading fw_status register. */ 652static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter) 653{ 654 struct pcie_service_card *card = adapter->card; 655 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 656 int retval __maybe_unused; 657 658 mwifiex_dbg(adapter, EVENT, 659 "event: Wakeup device...\n"); 660 661 if (reg->sleep_cookie) 662 mwifiex_pcie_dev_wakeup_delay(adapter); 663 664 /* The 88W8897 PCIe+USB firmware (latest version 15.68.19.p21) sometimes 665 * appears to ignore or miss our wakeup request, so we continue trying 666 * until we receive an interrupt from the card. 667 */ 668 if (read_poll_timeout(mwifiex_write_reg_rpt, retval, 669 READ_ONCE(adapter->int_status) != 0, 670 500, 500 * N_WAKEUP_TRIES_SHORT_INTERVAL, 671 false, 672 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { 673 if (read_poll_timeout(mwifiex_write_reg_rpt, retval, 674 READ_ONCE(adapter->int_status) != 0, 675 10000, 10000 * N_WAKEUP_TRIES_LONG_INTERVAL, 676 false, 677 adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { 678 mwifiex_dbg(adapter, ERROR, 679 "Firmware didn't wake up\n"); 680 return -EIO; 681 } 682 } 683 684 if (reg->sleep_cookie) { 685 mwifiex_pcie_dev_wakeup_delay(adapter); 686 mwifiex_dbg(adapter, INFO, 687 "PCIE wakeup: Setting PS_STATE_AWAKE\n"); 688 adapter->ps_state = PS_STATE_AWAKE; 689 } 690 691 return 0; 692} 693 694/* 695 * This function is called after the card has woken up. 696 * 697 * The card configuration register is reset. 698 */ 699static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter) 700{ 701 mwifiex_dbg(adapter, CMD, 702 "cmd: Wakeup device completed\n"); 703 704 return 0; 705} 706 707/* 708 * This function disables the host interrupt. 709 * 710 * The host interrupt mask is read, the disable bit is reset and 711 * written back to the card host interrupt mask register. 712 */ 713static void mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter) 714{ 715 if (mwifiex_pcie_ok_to_access_hw(adapter)) 716 mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, 0x00000000); 717 718 atomic_set(&adapter->tx_hw_pending, 0); 719} 720 721/* 722 * This function enables the host interrupt. 723 * 724 * The host interrupt enable mask is written to the card 725 * host interrupt mask register. 726 */ 727static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter) 728{ 729 if (mwifiex_pcie_ok_to_access_hw(adapter)) 730 /* Simply write the mask to the register */ 731 mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, HOST_INTR_MASK); 732 733 return 0; 734} 735 736/* 737 * This function initializes TX buffer ring descriptors 738 */ 739static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter) 740{ 741 struct pcie_service_card *card = adapter->card; 742 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 743 struct mwifiex_pcie_buf_desc *desc; 744 struct mwifiex_pfu_buf_desc *desc2; 745 int i; 746 747 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 748 card->tx_buf_list[i] = NULL; 749 if (reg->pfu_enabled) { 750 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 751 (sizeof(*desc2) * i); 752 desc2 = card->txbd_ring[i]; 753 memset(desc2, 0, sizeof(*desc2)); 754 } else { 755 card->txbd_ring[i] = (void *)card->txbd_ring_vbase + 756 (sizeof(*desc) * i); 757 desc = card->txbd_ring[i]; 758 memset(desc, 0, sizeof(*desc)); 759 } 760 } 761 762 return 0; 763} 764 765/* This function initializes RX buffer ring descriptors. Each SKB is allocated 766 * here and after mapping PCI memory, its physical address is assigned to 767 * PCIE Rx buffer descriptor's physical address. 768 */ 769static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) 770{ 771 struct pcie_service_card *card = adapter->card; 772 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 773 struct sk_buff *skb; 774 struct mwifiex_pcie_buf_desc *desc; 775 struct mwifiex_pfu_buf_desc *desc2; 776 dma_addr_t buf_pa; 777 int i; 778 779 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 780 /* Allocate skb here so that firmware can DMA data from it */ 781 skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 782 GFP_KERNEL); 783 if (!skb) { 784 mwifiex_dbg(adapter, ERROR, 785 "Unable to allocate skb for RX ring.\n"); 786 return -ENOMEM; 787 } 788 789 if (mwifiex_map_pci_memory(adapter, skb, 790 MWIFIEX_RX_DATA_BUF_SIZE, 791 DMA_FROM_DEVICE)) { 792 kfree_skb(skb); 793 return -ENOMEM; 794 } 795 796 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 797 798 mwifiex_dbg(adapter, INFO, 799 "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 800 skb, skb->len, skb->data, (u32)buf_pa, 801 (u32)((u64)buf_pa >> 32)); 802 803 card->rx_buf_list[i] = skb; 804 if (reg->pfu_enabled) { 805 card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase + 806 (sizeof(*desc2) * i); 807 desc2 = card->rxbd_ring[i]; 808 desc2->paddr = buf_pa; 809 desc2->len = (u16)skb->len; 810 desc2->frag_len = (u16)skb->len; 811 desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; 812 desc2->offset = 0; 813 } else { 814 card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase + 815 (sizeof(*desc) * i)); 816 desc = card->rxbd_ring[i]; 817 desc->paddr = buf_pa; 818 desc->len = (u16)skb->len; 819 desc->flags = 0; 820 } 821 } 822 823 return 0; 824} 825 826/* This function initializes event buffer ring descriptors. Each SKB is 827 * allocated here and after mapping PCI memory, its physical address is assigned 828 * to PCIE Rx buffer descriptor's physical address 829 */ 830static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) 831{ 832 struct pcie_service_card *card = adapter->card; 833 struct mwifiex_evt_buf_desc *desc; 834 struct sk_buff *skb; 835 dma_addr_t buf_pa; 836 int i; 837 838 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 839 /* Allocate skb here so that firmware can DMA data from it */ 840 skb = dev_alloc_skb(MAX_EVENT_SIZE); 841 if (!skb) { 842 mwifiex_dbg(adapter, ERROR, 843 "Unable to allocate skb for EVENT buf.\n"); 844 return -ENOMEM; 845 } 846 skb_put(skb, MAX_EVENT_SIZE); 847 848 if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, 849 DMA_FROM_DEVICE)) { 850 kfree_skb(skb); 851 return -ENOMEM; 852 } 853 854 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 855 856 mwifiex_dbg(adapter, EVENT, 857 "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", 858 skb, skb->len, skb->data, (u32)buf_pa, 859 (u32)((u64)buf_pa >> 32)); 860 861 card->evt_buf_list[i] = skb; 862 card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase + 863 (sizeof(*desc) * i)); 864 desc = card->evtbd_ring[i]; 865 desc->paddr = buf_pa; 866 desc->len = (u16)skb->len; 867 desc->flags = 0; 868 } 869 870 return 0; 871} 872 873/* This function cleans up TX buffer rings. If any of the buffer list has valid 874 * SKB address, associated SKB is freed. 875 */ 876static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) 877{ 878 struct pcie_service_card *card = adapter->card; 879 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 880 struct sk_buff *skb; 881 struct mwifiex_pcie_buf_desc *desc; 882 struct mwifiex_pfu_buf_desc *desc2; 883 int i; 884 885 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 886 if (reg->pfu_enabled) { 887 desc2 = card->txbd_ring[i]; 888 if (card->tx_buf_list[i]) { 889 skb = card->tx_buf_list[i]; 890 mwifiex_unmap_pci_memory(adapter, skb, 891 DMA_TO_DEVICE); 892 dev_kfree_skb_any(skb); 893 } 894 memset(desc2, 0, sizeof(*desc2)); 895 } else { 896 desc = card->txbd_ring[i]; 897 if (card->tx_buf_list[i]) { 898 skb = card->tx_buf_list[i]; 899 mwifiex_unmap_pci_memory(adapter, skb, 900 DMA_TO_DEVICE); 901 dev_kfree_skb_any(skb); 902 } 903 memset(desc, 0, sizeof(*desc)); 904 } 905 card->tx_buf_list[i] = NULL; 906 } 907 908 atomic_set(&adapter->tx_hw_pending, 0); 909 return; 910} 911 912/* This function cleans up RX buffer rings. If any of the buffer list has valid 913 * SKB address, associated SKB is freed. 914 */ 915static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) 916{ 917 struct pcie_service_card *card = adapter->card; 918 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 919 struct mwifiex_pcie_buf_desc *desc; 920 struct mwifiex_pfu_buf_desc *desc2; 921 struct sk_buff *skb; 922 int i; 923 924 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { 925 if (reg->pfu_enabled) { 926 desc2 = card->rxbd_ring[i]; 927 if (card->rx_buf_list[i]) { 928 skb = card->rx_buf_list[i]; 929 mwifiex_unmap_pci_memory(adapter, skb, 930 DMA_FROM_DEVICE); 931 dev_kfree_skb_any(skb); 932 } 933 memset(desc2, 0, sizeof(*desc2)); 934 } else { 935 desc = card->rxbd_ring[i]; 936 if (card->rx_buf_list[i]) { 937 skb = card->rx_buf_list[i]; 938 mwifiex_unmap_pci_memory(adapter, skb, 939 DMA_FROM_DEVICE); 940 dev_kfree_skb_any(skb); 941 } 942 memset(desc, 0, sizeof(*desc)); 943 } 944 card->rx_buf_list[i] = NULL; 945 } 946 947 return; 948} 949 950/* This function cleans up event buffer rings. If any of the buffer list has 951 * valid SKB address, associated SKB is freed. 952 */ 953static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) 954{ 955 struct pcie_service_card *card = adapter->card; 956 struct mwifiex_evt_buf_desc *desc; 957 struct sk_buff *skb; 958 int i; 959 960 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { 961 desc = card->evtbd_ring[i]; 962 if (card->evt_buf_list[i]) { 963 skb = card->evt_buf_list[i]; 964 mwifiex_unmap_pci_memory(adapter, skb, 965 DMA_FROM_DEVICE); 966 dev_kfree_skb_any(skb); 967 } 968 card->evt_buf_list[i] = NULL; 969 memset(desc, 0, sizeof(*desc)); 970 } 971 972 return; 973} 974 975/* This function creates buffer descriptor ring for TX 976 */ 977static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) 978{ 979 struct pcie_service_card *card = adapter->card; 980 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 981 982 /* 983 * driver maintaines the write pointer and firmware maintaines the read 984 * pointer. The write pointer starts at 0 (zero) while the read pointer 985 * starts at zero with rollover bit set 986 */ 987 card->txbd_wrptr = 0; 988 989 if (reg->pfu_enabled) 990 card->txbd_rdptr = 0; 991 else 992 card->txbd_rdptr |= reg->tx_rollover_ind; 993 994 /* allocate shared memory for the BD ring and divide the same in to 995 several descriptors */ 996 if (reg->pfu_enabled) 997 card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 998 MWIFIEX_MAX_TXRX_BD; 999 else 1000 card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 1001 MWIFIEX_MAX_TXRX_BD; 1002 1003 mwifiex_dbg(adapter, INFO, 1004 "info: txbd_ring: Allocating %d bytes\n", 1005 card->txbd_ring_size); 1006 card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1007 card->txbd_ring_size, 1008 &card->txbd_ring_pbase, 1009 GFP_KERNEL); 1010 if (!card->txbd_ring_vbase) { 1011 mwifiex_dbg(adapter, ERROR, 1012 "allocate coherent memory (%d bytes) failed!\n", 1013 card->txbd_ring_size); 1014 return -ENOMEM; 1015 } 1016 1017 mwifiex_dbg(adapter, DATA, 1018 "info: txbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1019 card->txbd_ring_vbase, (u32)card->txbd_ring_pbase, 1020 (u32)((u64)card->txbd_ring_pbase >> 32), 1021 card->txbd_ring_size); 1022 1023 return mwifiex_init_txq_ring(adapter); 1024} 1025 1026static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) 1027{ 1028 struct pcie_service_card *card = adapter->card; 1029 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1030 1031 mwifiex_cleanup_txq_ring(adapter); 1032 1033 if (card->txbd_ring_vbase) 1034 dma_free_coherent(&card->dev->dev, card->txbd_ring_size, 1035 card->txbd_ring_vbase, 1036 card->txbd_ring_pbase); 1037 card->txbd_ring_size = 0; 1038 card->txbd_wrptr = 0; 1039 card->txbd_rdptr = 0 | reg->tx_rollover_ind; 1040 card->txbd_ring_vbase = NULL; 1041 card->txbd_ring_pbase = 0; 1042 1043 return 0; 1044} 1045 1046/* 1047 * This function creates buffer descriptor ring for RX 1048 */ 1049static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) 1050{ 1051 int ret; 1052 struct pcie_service_card *card = adapter->card; 1053 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1054 1055 /* 1056 * driver maintaines the read pointer and firmware maintaines the write 1057 * pointer. The write pointer starts at 0 (zero) while the read pointer 1058 * starts at zero with rollover bit set 1059 */ 1060 card->rxbd_wrptr = 0; 1061 card->rxbd_rdptr = reg->rx_rollover_ind; 1062 1063 if (reg->pfu_enabled) 1064 card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * 1065 MWIFIEX_MAX_TXRX_BD; 1066 else 1067 card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * 1068 MWIFIEX_MAX_TXRX_BD; 1069 1070 mwifiex_dbg(adapter, INFO, 1071 "info: rxbd_ring: Allocating %d bytes\n", 1072 card->rxbd_ring_size); 1073 card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1074 card->rxbd_ring_size, 1075 &card->rxbd_ring_pbase, 1076 GFP_KERNEL); 1077 if (!card->rxbd_ring_vbase) { 1078 mwifiex_dbg(adapter, ERROR, 1079 "allocate coherent memory (%d bytes) failed!\n", 1080 card->rxbd_ring_size); 1081 return -ENOMEM; 1082 } 1083 1084 mwifiex_dbg(adapter, DATA, 1085 "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", 1086 card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase, 1087 (u32)((u64)card->rxbd_ring_pbase >> 32), 1088 card->rxbd_ring_size); 1089 1090 ret = mwifiex_init_rxq_ring(adapter); 1091 if (ret) 1092 mwifiex_pcie_delete_rxbd_ring(adapter); 1093 return ret; 1094} 1095 1096/* 1097 * This function deletes Buffer descriptor ring for RX 1098 */ 1099static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) 1100{ 1101 struct pcie_service_card *card = adapter->card; 1102 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1103 1104 mwifiex_cleanup_rxq_ring(adapter); 1105 1106 if (card->rxbd_ring_vbase) 1107 dma_free_coherent(&card->dev->dev, card->rxbd_ring_size, 1108 card->rxbd_ring_vbase, 1109 card->rxbd_ring_pbase); 1110 card->rxbd_ring_size = 0; 1111 card->rxbd_wrptr = 0; 1112 card->rxbd_rdptr = 0 | reg->rx_rollover_ind; 1113 card->rxbd_ring_vbase = NULL; 1114 card->rxbd_ring_pbase = 0; 1115 1116 return 0; 1117} 1118 1119/* 1120 * This function creates buffer descriptor ring for Events 1121 */ 1122static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) 1123{ 1124 int ret; 1125 struct pcie_service_card *card = adapter->card; 1126 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1127 1128 /* 1129 * driver maintaines the read pointer and firmware maintaines the write 1130 * pointer. The write pointer starts at 0 (zero) while the read pointer 1131 * starts at zero with rollover bit set 1132 */ 1133 card->evtbd_wrptr = 0; 1134 card->evtbd_rdptr = reg->evt_rollover_ind; 1135 1136 card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) * 1137 MWIFIEX_MAX_EVT_BD; 1138 1139 mwifiex_dbg(adapter, INFO, 1140 "info: evtbd_ring: Allocating %d bytes\n", 1141 card->evtbd_ring_size); 1142 card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, 1143 card->evtbd_ring_size, 1144 &card->evtbd_ring_pbase, 1145 GFP_KERNEL); 1146 if (!card->evtbd_ring_vbase) { 1147 mwifiex_dbg(adapter, ERROR, 1148 "allocate coherent memory (%d bytes) failed!\n", 1149 card->evtbd_ring_size); 1150 return -ENOMEM; 1151 } 1152 1153 mwifiex_dbg(adapter, EVENT, 1154 "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n", 1155 card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase, 1156 (u32)((u64)card->evtbd_ring_pbase >> 32), 1157 card->evtbd_ring_size); 1158 1159 ret = mwifiex_pcie_init_evt_ring(adapter); 1160 if (ret) 1161 mwifiex_pcie_delete_evtbd_ring(adapter); 1162 return ret; 1163} 1164 1165/* 1166 * This function deletes Buffer descriptor ring for Events 1167 */ 1168static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) 1169{ 1170 struct pcie_service_card *card = adapter->card; 1171 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1172 1173 mwifiex_cleanup_evt_ring(adapter); 1174 1175 if (card->evtbd_ring_vbase) 1176 dma_free_coherent(&card->dev->dev, card->evtbd_ring_size, 1177 card->evtbd_ring_vbase, 1178 card->evtbd_ring_pbase); 1179 card->evtbd_wrptr = 0; 1180 card->evtbd_rdptr = 0 | reg->evt_rollover_ind; 1181 card->evtbd_ring_size = 0; 1182 card->evtbd_ring_vbase = NULL; 1183 card->evtbd_ring_pbase = 0; 1184 1185 return 0; 1186} 1187 1188/* 1189 * This function allocates a buffer for CMDRSP 1190 */ 1191static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) 1192{ 1193 struct pcie_service_card *card = adapter->card; 1194 struct sk_buff *skb; 1195 1196 /* Allocate memory for receiving command response data */ 1197 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 1198 if (!skb) { 1199 mwifiex_dbg(adapter, ERROR, 1200 "Unable to allocate skb for command response data.\n"); 1201 return -ENOMEM; 1202 } 1203 skb_put(skb, MWIFIEX_UPLD_SIZE); 1204 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1205 DMA_FROM_DEVICE)) { 1206 kfree_skb(skb); 1207 return -1; 1208 } 1209 1210 card->cmdrsp_buf = skb; 1211 1212 return 0; 1213} 1214 1215/* 1216 * This function deletes a buffer for CMDRSP 1217 */ 1218static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) 1219{ 1220 struct pcie_service_card *card; 1221 1222 if (!adapter) 1223 return 0; 1224 1225 card = adapter->card; 1226 1227 if (card && card->cmdrsp_buf) { 1228 mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, 1229 DMA_FROM_DEVICE); 1230 dev_kfree_skb_any(card->cmdrsp_buf); 1231 card->cmdrsp_buf = NULL; 1232 } 1233 1234 if (card && card->cmd_buf) { 1235 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1236 DMA_TO_DEVICE); 1237 dev_kfree_skb_any(card->cmd_buf); 1238 card->cmd_buf = NULL; 1239 } 1240 return 0; 1241} 1242 1243/* 1244 * This function allocates a buffer for sleep cookie 1245 */ 1246static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1247{ 1248 struct pcie_service_card *card = adapter->card; 1249 u32 *cookie; 1250 1251 card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev, 1252 sizeof(u32), 1253 &card->sleep_cookie_pbase, 1254 GFP_KERNEL); 1255 if (!card->sleep_cookie_vbase) { 1256 mwifiex_dbg(adapter, ERROR, 1257 "dma_alloc_coherent failed!\n"); 1258 return -ENOMEM; 1259 } 1260 cookie = (u32 *)card->sleep_cookie_vbase; 1261 /* Init val of Sleep Cookie */ 1262 *cookie = FW_AWAKE_COOKIE; 1263 1264 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie); 1265 1266 return 0; 1267} 1268 1269/* 1270 * This function deletes buffer for sleep cookie 1271 */ 1272static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) 1273{ 1274 struct pcie_service_card *card; 1275 1276 if (!adapter) 1277 return 0; 1278 1279 card = adapter->card; 1280 1281 if (card && card->sleep_cookie_vbase) { 1282 dma_free_coherent(&card->dev->dev, sizeof(u32), 1283 card->sleep_cookie_vbase, 1284 card->sleep_cookie_pbase); 1285 card->sleep_cookie_vbase = NULL; 1286 } 1287 1288 return 0; 1289} 1290 1291/* This function flushes the TX buffer descriptor ring 1292 * This function defined as handler is also called while cleaning TXRX 1293 * during disconnect/ bss stop. 1294 */ 1295static void mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter) 1296{ 1297 struct pcie_service_card *card = adapter->card; 1298 1299 if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) { 1300 card->txbd_flush = 1; 1301 /* write pointer already set at last send 1302 * send dnld-rdy intr again, wait for completion. 1303 */ 1304 mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1305 CPU_INTR_DNLD_RDY); 1306 } 1307} 1308 1309/* 1310 * This function unmaps and frees downloaded data buffer 1311 */ 1312static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) 1313{ 1314 struct sk_buff *skb; 1315 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; 1316 struct mwifiex_pcie_buf_desc *desc; 1317 struct mwifiex_pfu_buf_desc *desc2; 1318 struct pcie_service_card *card = adapter->card; 1319 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1320 1321 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1322 mwifiex_pm_wakeup_card(adapter); 1323 1324 /* Read the TX ring read pointer set by firmware */ 1325 if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { 1326 mwifiex_dbg(adapter, ERROR, 1327 "SEND COMP: failed to read reg->tx_rdptr\n"); 1328 return -1; 1329 } 1330 1331 mwifiex_dbg(adapter, DATA, 1332 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", 1333 card->txbd_rdptr, rdptr); 1334 1335 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1336 /* free from previous txbd_rdptr to current txbd_rdptr */ 1337 while (((card->txbd_rdptr & reg->tx_mask) != 1338 (rdptr & reg->tx_mask)) || 1339 ((card->txbd_rdptr & reg->tx_rollover_ind) != 1340 (rdptr & reg->tx_rollover_ind))) { 1341 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> 1342 reg->tx_start_ptr; 1343 1344 skb = card->tx_buf_list[wrdoneidx]; 1345 1346 if (skb) { 1347 mwifiex_dbg(adapter, DATA, 1348 "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", 1349 skb, wrdoneidx); 1350 mwifiex_unmap_pci_memory(adapter, skb, 1351 DMA_TO_DEVICE); 1352 1353 unmap_count++; 1354 1355 if (card->txbd_flush) 1356 mwifiex_write_data_complete(adapter, skb, 0, 1357 -1); 1358 else 1359 mwifiex_write_data_complete(adapter, skb, 0, 0); 1360 atomic_dec(&adapter->tx_hw_pending); 1361 } 1362 1363 card->tx_buf_list[wrdoneidx] = NULL; 1364 1365 if (reg->pfu_enabled) { 1366 desc2 = card->txbd_ring[wrdoneidx]; 1367 memset(desc2, 0, sizeof(*desc2)); 1368 } else { 1369 desc = card->txbd_ring[wrdoneidx]; 1370 memset(desc, 0, sizeof(*desc)); 1371 } 1372 switch (card->dev->device) { 1373 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1374 card->txbd_rdptr++; 1375 break; 1376 case PCIE_DEVICE_ID_MARVELL_88W8897: 1377 case PCIE_DEVICE_ID_MARVELL_88W8997: 1378 card->txbd_rdptr += reg->ring_tx_start_ptr; 1379 break; 1380 } 1381 1382 1383 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) 1384 card->txbd_rdptr = ((card->txbd_rdptr & 1385 reg->tx_rollover_ind) ^ 1386 reg->tx_rollover_ind); 1387 } 1388 1389 if (unmap_count) 1390 adapter->data_sent = false; 1391 1392 if (card->txbd_flush) { 1393 if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) 1394 card->txbd_flush = 0; 1395 else 1396 mwifiex_clean_pcie_ring_buf(adapter); 1397 } 1398 1399 return 0; 1400} 1401 1402/* This function sends data buffer to device. First 4 bytes of payload 1403 * are filled with payload length and payload type. Then this payload 1404 * is mapped to PCI device memory. Tx ring pointers are advanced accordingly. 1405 * Download ready interrupt to FW is deffered if Tx ring is not full and 1406 * additional payload can be accomodated. 1407 * Caller must ensure tx_param parameter to this function is not NULL. 1408 */ 1409static int 1410mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, 1411 struct mwifiex_tx_param *tx_param) 1412{ 1413 struct pcie_service_card *card = adapter->card; 1414 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1415 u32 wrindx, num_tx_buffs, rx_val; 1416 dma_addr_t buf_pa; 1417 struct mwifiex_pcie_buf_desc *desc = NULL; 1418 struct mwifiex_pfu_buf_desc *desc2 = NULL; 1419 1420 if (!(skb->data && skb->len)) { 1421 mwifiex_dbg(adapter, ERROR, 1422 "%s(): invalid parameter <%p, %#x>\n", 1423 __func__, skb->data, skb->len); 1424 return -1; 1425 } 1426 1427 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1428 mwifiex_pm_wakeup_card(adapter); 1429 1430 num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; 1431 mwifiex_dbg(adapter, DATA, 1432 "info: SEND DATA: <Rd: %#x, Wr: %#x>\n", 1433 card->txbd_rdptr, card->txbd_wrptr); 1434 if (mwifiex_pcie_txbd_not_full(card)) { 1435 u8 *payload; 1436 1437 adapter->data_sent = true; 1438 payload = skb->data; 1439 put_unaligned_le16((u16)skb->len, payload + 0); 1440 put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2); 1441 1442 if (mwifiex_map_pci_memory(adapter, skb, skb->len, 1443 DMA_TO_DEVICE)) 1444 return -1; 1445 1446 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; 1447 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1448 card->tx_buf_list[wrindx] = skb; 1449 atomic_inc(&adapter->tx_hw_pending); 1450 1451 if (reg->pfu_enabled) { 1452 desc2 = card->txbd_ring[wrindx]; 1453 desc2->paddr = buf_pa; 1454 desc2->len = (u16)skb->len; 1455 desc2->frag_len = (u16)skb->len; 1456 desc2->offset = 0; 1457 desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1458 MWIFIEX_BD_FLAG_LAST_DESC; 1459 } else { 1460 desc = card->txbd_ring[wrindx]; 1461 desc->paddr = buf_pa; 1462 desc->len = (u16)skb->len; 1463 desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC | 1464 MWIFIEX_BD_FLAG_LAST_DESC; 1465 } 1466 1467 switch (card->dev->device) { 1468 case PCIE_DEVICE_ID_MARVELL_88W8766P: 1469 card->txbd_wrptr++; 1470 break; 1471 case PCIE_DEVICE_ID_MARVELL_88W8897: 1472 case PCIE_DEVICE_ID_MARVELL_88W8997: 1473 card->txbd_wrptr += reg->ring_tx_start_ptr; 1474 break; 1475 } 1476 1477 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) 1478 card->txbd_wrptr = ((card->txbd_wrptr & 1479 reg->tx_rollover_ind) ^ 1480 reg->tx_rollover_ind); 1481 1482 rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; 1483 /* Write the TX ring write pointer in to reg->tx_wrptr */ 1484 mwifiex_write_reg(adapter, reg->tx_wrptr, 1485 card->txbd_wrptr | rx_val); 1486 1487 /* The firmware (latest version 15.68.19.p21) of the 88W8897 PCIe+USB card 1488 * seems to crash randomly after setting the TX ring write pointer when 1489 * ASPM powersaving is enabled. A workaround seems to be keeping the bus 1490 * busy by reading a random register afterwards. 1491 */ 1492 mwifiex_read_reg(adapter, PCI_VENDOR_ID, &rx_val); 1493 1494 if ((mwifiex_pcie_txbd_not_full(card)) && 1495 tx_param->next_pkt_len) { 1496 /* have more packets and TxBD still can hold more */ 1497 mwifiex_dbg(adapter, DATA, 1498 "SEND DATA: delay dnld-rdy interrupt.\n"); 1499 adapter->data_sent = false; 1500 } else { 1501 /* Send the TX ready interrupt */ 1502 mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1503 CPU_INTR_DNLD_RDY); 1504 } 1505 mwifiex_dbg(adapter, DATA, 1506 "info: SEND DATA: Updated <Rd: %#x, Wr:\t" 1507 "%#x> and sent packet to firmware successfully\n", 1508 card->txbd_rdptr, card->txbd_wrptr); 1509 } else { 1510 mwifiex_dbg(adapter, DATA, 1511 "info: TX Ring full, can't send packets to fw\n"); 1512 adapter->data_sent = true; 1513 /* Send the TX ready interrupt */ 1514 mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1515 CPU_INTR_DNLD_RDY); 1516 return -EBUSY; 1517 } 1518 1519 return -EINPROGRESS; 1520} 1521 1522/* 1523 * This function handles received buffer ring and 1524 * dispatches packets to upper 1525 */ 1526static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) 1527{ 1528 struct pcie_service_card *card = adapter->card; 1529 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1530 u32 wrptr, rd_index, tx_val; 1531 dma_addr_t buf_pa; 1532 int ret = 0; 1533 struct sk_buff *skb_tmp = NULL; 1534 struct mwifiex_pcie_buf_desc *desc; 1535 struct mwifiex_pfu_buf_desc *desc2; 1536 1537 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1538 mwifiex_pm_wakeup_card(adapter); 1539 1540 /* Read the RX ring Write pointer set by firmware */ 1541 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1542 mwifiex_dbg(adapter, ERROR, 1543 "RECV DATA: failed to read reg->rx_wrptr\n"); 1544 ret = -1; 1545 goto done; 1546 } 1547 card->rxbd_wrptr = wrptr; 1548 1549 while (((wrptr & reg->rx_mask) != 1550 (card->rxbd_rdptr & reg->rx_mask)) || 1551 ((wrptr & reg->rx_rollover_ind) == 1552 (card->rxbd_rdptr & reg->rx_rollover_ind))) { 1553 struct sk_buff *skb_data; 1554 u16 rx_len; 1555 1556 rd_index = card->rxbd_rdptr & reg->rx_mask; 1557 skb_data = card->rx_buf_list[rd_index]; 1558 1559 /* If skb allocation was failed earlier for Rx packet, 1560 * rx_buf_list[rd_index] would have been left with a NULL. 1561 */ 1562 if (!skb_data) 1563 return -ENOMEM; 1564 1565 mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE); 1566 card->rx_buf_list[rd_index] = NULL; 1567 1568 /* Get data length from interface header - 1569 * first 2 bytes for len, next 2 bytes is for type 1570 */ 1571 rx_len = get_unaligned_le16(skb_data->data); 1572 if (WARN_ON(rx_len <= adapter->intf_hdr_len || 1573 rx_len > MWIFIEX_RX_DATA_BUF_SIZE)) { 1574 mwifiex_dbg(adapter, ERROR, 1575 "Invalid RX len %d, Rd=%#x, Wr=%#x\n", 1576 rx_len, card->rxbd_rdptr, wrptr); 1577 dev_kfree_skb_any(skb_data); 1578 } else { 1579 skb_put(skb_data, rx_len); 1580 mwifiex_dbg(adapter, DATA, 1581 "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n", 1582 card->rxbd_rdptr, wrptr, rx_len); 1583 skb_pull(skb_data, adapter->intf_hdr_len); 1584 if (adapter->rx_work_enabled) { 1585 skb_queue_tail(&adapter->rx_data_q, skb_data); 1586 adapter->data_received = true; 1587 atomic_inc(&adapter->rx_pending); 1588 } else { 1589 mwifiex_handle_rx_packet(adapter, skb_data); 1590 } 1591 } 1592 1593 skb_tmp = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE, 1594 GFP_KERNEL); 1595 if (!skb_tmp) { 1596 mwifiex_dbg(adapter, ERROR, 1597 "Unable to allocate skb.\n"); 1598 return -ENOMEM; 1599 } 1600 1601 if (mwifiex_map_pci_memory(adapter, skb_tmp, 1602 MWIFIEX_RX_DATA_BUF_SIZE, 1603 DMA_FROM_DEVICE)) 1604 return -1; 1605 1606 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); 1607 1608 mwifiex_dbg(adapter, INFO, 1609 "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n", 1610 skb_tmp, rd_index); 1611 card->rx_buf_list[rd_index] = skb_tmp; 1612 1613 if (reg->pfu_enabled) { 1614 desc2 = card->rxbd_ring[rd_index]; 1615 desc2->paddr = buf_pa; 1616 desc2->len = skb_tmp->len; 1617 desc2->frag_len = skb_tmp->len; 1618 desc2->offset = 0; 1619 desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; 1620 } else { 1621 desc = card->rxbd_ring[rd_index]; 1622 desc->paddr = buf_pa; 1623 desc->len = skb_tmp->len; 1624 desc->flags = 0; 1625 } 1626 1627 if ((++card->rxbd_rdptr & reg->rx_mask) == 1628 MWIFIEX_MAX_TXRX_BD) { 1629 card->rxbd_rdptr = ((card->rxbd_rdptr & 1630 reg->rx_rollover_ind) ^ 1631 reg->rx_rollover_ind); 1632 } 1633 mwifiex_dbg(adapter, DATA, 1634 "info: RECV DATA: <Rd: %#x, Wr: %#x>\n", 1635 card->rxbd_rdptr, wrptr); 1636 1637 tx_val = card->txbd_wrptr & reg->tx_wrap_mask; 1638 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1639 mwifiex_write_reg(adapter, reg->rx_rdptr, 1640 card->rxbd_rdptr | tx_val); 1641 1642 /* Read the RX ring Write pointer set by firmware */ 1643 if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { 1644 mwifiex_dbg(adapter, ERROR, 1645 "RECV DATA: failed to read reg->rx_wrptr\n"); 1646 ret = -1; 1647 goto done; 1648 } 1649 mwifiex_dbg(adapter, DATA, 1650 "info: RECV DATA: Rcvd packet from fw successfully\n"); 1651 card->rxbd_wrptr = wrptr; 1652 } 1653 1654done: 1655 return ret; 1656} 1657 1658/* 1659 * This function downloads the boot command to device 1660 */ 1661static int 1662mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1663{ 1664 dma_addr_t buf_pa; 1665 struct pcie_service_card *card = adapter->card; 1666 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1667 1668 if (!(skb->data && skb->len)) { 1669 mwifiex_dbg(adapter, ERROR, 1670 "Invalid parameter in %s <%p. len %d>\n", 1671 __func__, skb->data, skb->len); 1672 return -1; 1673 } 1674 1675 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1676 return -1; 1677 1678 buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); 1679 1680 /* Write the lower 32bits of the physical address to low command 1681 * address scratch register 1682 */ 1683 mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa); 1684 1685 /* Write the upper 32bits of the physical address to high command 1686 * address scratch register 1687 */ 1688 mwifiex_write_reg(adapter, reg->cmd_addr_hi, (u32)((u64)buf_pa >> 32)); 1689 1690 /* Write the command length to cmd_size scratch register */ 1691 mwifiex_write_reg(adapter, reg->cmd_size, skb->len); 1692 1693 /* Ring the door bell */ 1694 mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, CPU_INTR_DOOR_BELL); 1695 1696 return 0; 1697} 1698 1699/* This function init rx port in firmware which in turn enables to receive data 1700 * from device before transmitting any packet. 1701 */ 1702static void mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter) 1703{ 1704 struct pcie_service_card *card = adapter->card; 1705 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1706 int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; 1707 1708 /* Write the RX ring read pointer in to reg->rx_rdptr */ 1709 mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | tx_wrap); 1710} 1711 1712/* This function downloads commands to the device 1713 */ 1714static int 1715mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) 1716{ 1717 struct pcie_service_card *card = adapter->card; 1718 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1719 dma_addr_t cmd_buf_pa, cmdrsp_buf_pa; 1720 u8 *payload = (u8 *)skb->data; 1721 1722 if (!(skb->data && skb->len)) { 1723 mwifiex_dbg(adapter, ERROR, 1724 "Invalid parameter in %s <%p, %#x>\n", 1725 __func__, skb->data, skb->len); 1726 return -1; 1727 } 1728 1729 /* Make sure a command response buffer is available */ 1730 if (!card->cmdrsp_buf) { 1731 mwifiex_dbg(adapter, ERROR, 1732 "No response buffer available, send command failed\n"); 1733 return -EBUSY; 1734 } 1735 1736 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1737 mwifiex_pm_wakeup_card(adapter); 1738 1739 adapter->cmd_sent = true; 1740 1741 put_unaligned_le16((u16)skb->len, &payload[0]); 1742 put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]); 1743 1744 if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) 1745 return -1; 1746 1747 card->cmd_buf = skb; 1748 /* 1749 * Need to keep a reference, since core driver might free up this 1750 * buffer before we've unmapped it. 1751 */ 1752 skb_get(skb); 1753 1754 /* To send a command, the driver will: 1755 1. Write the 64bit physical address of the data buffer to 1756 cmd response address low + cmd response address high 1757 2. Ring the door bell (i.e. set the door bell interrupt) 1758 1759 In response to door bell interrupt, the firmware will perform 1760 the DMA of the command packet (first header to obtain the total 1761 length and then rest of the command). 1762 */ 1763 1764 if (card->cmdrsp_buf) { 1765 cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf); 1766 /* Write the lower 32bits of the cmdrsp buffer physical 1767 address */ 1768 mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 1769 (u32)cmdrsp_buf_pa); 1770 1771 /* Write the upper 32bits of the cmdrsp buffer physical 1772 address */ 1773 mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 1774 (u32)((u64)cmdrsp_buf_pa >> 32)); 1775 } 1776 1777 cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf); 1778 1779 /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */ 1780 mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)cmd_buf_pa); 1781 1782 /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */ 1783 mwifiex_write_reg(adapter, reg->cmd_addr_hi, 1784 (u32)((u64)cmd_buf_pa >> 32)); 1785 1786 /* Write the command length to reg->cmd_size */ 1787 mwifiex_write_reg(adapter, reg->cmd_size, card->cmd_buf->len); 1788 1789 /* Ring the door bell */ 1790 mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, CPU_INTR_DOOR_BELL); 1791 1792 return 0; 1793} 1794 1795/* 1796 * This function handles command complete interrupt 1797 */ 1798static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) 1799{ 1800 struct pcie_service_card *card = adapter->card; 1801 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1802 struct sk_buff *skb = card->cmdrsp_buf; 1803 int count = 0; 1804 u16 rx_len; 1805 1806 mwifiex_dbg(adapter, CMD, 1807 "info: Rx CMD Response\n"); 1808 1809 if (adapter->curr_cmd) 1810 mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE); 1811 else 1812 dma_sync_single_for_cpu(&card->dev->dev, 1813 MWIFIEX_SKB_DMA_ADDR(skb), 1814 MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE); 1815 1816 /* Unmap the command as a response has been received. */ 1817 if (card->cmd_buf) { 1818 mwifiex_unmap_pci_memory(adapter, card->cmd_buf, 1819 DMA_TO_DEVICE); 1820 dev_kfree_skb_any(card->cmd_buf); 1821 card->cmd_buf = NULL; 1822 } 1823 1824 rx_len = get_unaligned_le16(skb->data); 1825 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 1826 skb_trim(skb, rx_len); 1827 1828 if (!adapter->curr_cmd) { 1829 if (adapter->ps_state == PS_STATE_SLEEP_CFM) { 1830 dma_sync_single_for_device(&card->dev->dev, 1831 MWIFIEX_SKB_DMA_ADDR(skb), 1832 MWIFIEX_SLEEP_COOKIE_SIZE, 1833 DMA_FROM_DEVICE); 1834 mwifiex_write_reg(adapter, 1835 PCIE_CPU_INT_EVENT, 1836 CPU_INTR_SLEEP_CFM_DONE); 1837 mwifiex_delay_for_sleep_cookie(adapter, 1838 MWIFIEX_MAX_DELAY_COUNT); 1839 mwifiex_unmap_pci_memory(adapter, skb, 1840 DMA_FROM_DEVICE); 1841 skb_pull(skb, adapter->intf_hdr_len); 1842 while (reg->sleep_cookie && (count++ < 10) && 1843 mwifiex_pcie_ok_to_access_hw(adapter)) 1844 usleep_range(50, 60); 1845 mwifiex_pcie_enable_host_int(adapter); 1846 mwifiex_process_sleep_confirm_resp(adapter, skb->data, 1847 skb->len); 1848 } else { 1849 mwifiex_dbg(adapter, ERROR, 1850 "There is no command but got cmdrsp\n"); 1851 } 1852 memcpy(adapter->upld_buf, skb->data, 1853 min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); 1854 skb_push(skb, adapter->intf_hdr_len); 1855 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1856 DMA_FROM_DEVICE)) 1857 return -1; 1858 } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { 1859 skb_pull(skb, adapter->intf_hdr_len); 1860 adapter->curr_cmd->resp_skb = skb; 1861 adapter->cmd_resp_received = true; 1862 /* Take the pointer and set it to CMD node and will 1863 return in the response complete callback */ 1864 card->cmdrsp_buf = NULL; 1865 1866 /* Clear the cmd-rsp buffer address in scratch registers. This 1867 will prevent firmware from writing to the same response 1868 buffer again. */ 1869 mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0); 1870 1871 /* Write the upper 32bits of the cmdrsp buffer physical 1872 address */ 1873 mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0); 1874 } 1875 1876 return 0; 1877} 1878 1879/* 1880 * Command Response processing complete handler 1881 */ 1882static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, 1883 struct sk_buff *skb) 1884{ 1885 struct pcie_service_card *card = adapter->card; 1886 1887 if (skb) { 1888 card->cmdrsp_buf = skb; 1889 skb_push(card->cmdrsp_buf, adapter->intf_hdr_len); 1890 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, 1891 DMA_FROM_DEVICE)) 1892 return -1; 1893 } 1894 1895 return 0; 1896} 1897 1898/* 1899 * This function handles firmware event ready interrupt 1900 */ 1901static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) 1902{ 1903 struct pcie_service_card *card = adapter->card; 1904 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1905 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 1906 u32 wrptr, event; 1907 struct mwifiex_evt_buf_desc *desc; 1908 1909 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 1910 mwifiex_pm_wakeup_card(adapter); 1911 1912 if (adapter->event_received) { 1913 mwifiex_dbg(adapter, EVENT, 1914 "info: Event being processed,\t" 1915 "do not process this interrupt just yet\n"); 1916 return 0; 1917 } 1918 1919 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 1920 mwifiex_dbg(adapter, ERROR, 1921 "info: Invalid read pointer...\n"); 1922 return -1; 1923 } 1924 1925 /* Read the event ring write pointer set by firmware */ 1926 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 1927 mwifiex_dbg(adapter, ERROR, 1928 "EventReady: failed to read reg->evt_wrptr\n"); 1929 return -1; 1930 } 1931 1932 mwifiex_dbg(adapter, EVENT, 1933 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", 1934 card->evtbd_rdptr, wrptr); 1935 if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr 1936 & MWIFIEX_EVTBD_MASK)) || 1937 ((wrptr & reg->evt_rollover_ind) == 1938 (card->evtbd_rdptr & reg->evt_rollover_ind))) { 1939 struct sk_buff *skb_cmd; 1940 __le16 data_len = 0; 1941 u16 evt_len; 1942 1943 mwifiex_dbg(adapter, INFO, 1944 "info: Read Index: %d\n", rdptr); 1945 skb_cmd = card->evt_buf_list[rdptr]; 1946 mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE); 1947 1948 /* Take the pointer and set it to event pointer in adapter 1949 and will return back after event handling callback */ 1950 card->evt_buf_list[rdptr] = NULL; 1951 desc = card->evtbd_ring[rdptr]; 1952 memset(desc, 0, sizeof(*desc)); 1953 1954 event = get_unaligned_le32( 1955 &skb_cmd->data[adapter->intf_hdr_len]); 1956 adapter->event_cause = event; 1957 /* The first 4bytes will be the event transfer header 1958 len is 2 bytes followed by type which is 2 bytes */ 1959 memcpy(&data_len, skb_cmd->data, sizeof(__le16)); 1960 evt_len = le16_to_cpu(data_len); 1961 skb_trim(skb_cmd, evt_len); 1962 skb_pull(skb_cmd, adapter->intf_hdr_len); 1963 mwifiex_dbg(adapter, EVENT, 1964 "info: Event length: %d\n", evt_len); 1965 1966 if (evt_len > MWIFIEX_EVENT_HEADER_LEN && 1967 evt_len < MAX_EVENT_SIZE) 1968 memcpy(adapter->event_body, skb_cmd->data + 1969 MWIFIEX_EVENT_HEADER_LEN, evt_len - 1970 MWIFIEX_EVENT_HEADER_LEN); 1971 1972 adapter->event_received = true; 1973 adapter->event_skb = skb_cmd; 1974 1975 /* Do not update the event read pointer here, wait till the 1976 buffer is released. This is just to make things simpler, 1977 we need to find a better method of managing these buffers. 1978 */ 1979 } else { 1980 mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, 1981 CPU_INTR_EVENT_DONE); 1982 } 1983 1984 return 0; 1985} 1986 1987/* 1988 * Event processing complete handler 1989 */ 1990static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, 1991 struct sk_buff *skb) 1992{ 1993 struct pcie_service_card *card = adapter->card; 1994 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 1995 u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; 1996 u32 wrptr; 1997 struct mwifiex_evt_buf_desc *desc; 1998 1999 if (!skb) 2000 return 0; 2001 2002 if (rdptr >= MWIFIEX_MAX_EVT_BD) { 2003 mwifiex_dbg(adapter, ERROR, 2004 "event_complete: Invalid rdptr 0x%x\n", 2005 rdptr); 2006 return -EINVAL; 2007 } 2008 2009 /* Read the event ring write pointer set by firmware */ 2010 if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { 2011 mwifiex_dbg(adapter, ERROR, 2012 "event_complete: failed to read reg->evt_wrptr\n"); 2013 return -1; 2014 } 2015 2016 if (!card->evt_buf_list[rdptr]) { 2017 skb_push(skb, adapter->intf_hdr_len); 2018 skb_put(skb, MAX_EVENT_SIZE - skb->len); 2019 if (mwifiex_map_pci_memory(adapter, skb, 2020 MAX_EVENT_SIZE, 2021 DMA_FROM_DEVICE)) 2022 return -1; 2023 card->evt_buf_list[rdptr] = skb; 2024 desc = card->evtbd_ring[rdptr]; 2025 desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb); 2026 desc->len = (u16)skb->len; 2027 desc->flags = 0; 2028 skb = NULL; 2029 } else { 2030 mwifiex_dbg(adapter, ERROR, 2031 "info: ERROR: buf still valid at index %d, <%p, %p>\n", 2032 rdptr, card->evt_buf_list[rdptr], skb); 2033 } 2034 2035 if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) { 2036 card->evtbd_rdptr = ((card->evtbd_rdptr & 2037 reg->evt_rollover_ind) ^ 2038 reg->evt_rollover_ind); 2039 } 2040 2041 mwifiex_dbg(adapter, EVENT, 2042 "info: Updated <Rd: 0x%x, Wr: 0x%x>", 2043 card->evtbd_rdptr, wrptr); 2044 2045 /* Write the event ring read pointer in to reg->evt_rdptr */ 2046 mwifiex_write_reg(adapter, reg->evt_rdptr, card->evtbd_rdptr); 2047 2048 mwifiex_dbg(adapter, EVENT, 2049 "info: Check Events Again\n"); 2050 return mwifiex_pcie_process_event_ready(adapter); 2051} 2052 2053/* Combo firmware image is a combination of 2054 * (1) combo crc heaer, start with CMD5 2055 * (2) bluetooth image, start with CMD7, end with CMD6, data wrapped in CMD1. 2056 * (3) wifi image. 2057 * 2058 * This function bypass the header and bluetooth part, return 2059 * the offset of tail wifi-only part. If the image is already wifi-only, 2060 * that is start with CMD1, return 0. 2061 */ 2062 2063static int mwifiex_extract_wifi_fw(struct mwifiex_adapter *adapter, 2064 const void *firmware, u32 firmware_len) { 2065 const struct mwifiex_fw_data *fwdata; 2066 u32 offset = 0, data_len, dnld_cmd; 2067 int ret = 0; 2068 bool cmd7_before = false, first_cmd = false; 2069 2070 while (1) { 2071 /* Check for integer and buffer overflow */ 2072 if (offset + sizeof(fwdata->header) < sizeof(fwdata->header) || 2073 offset + sizeof(fwdata->header) >= firmware_len) { 2074 mwifiex_dbg(adapter, ERROR, 2075 "extract wifi-only fw failure!\n"); 2076 ret = -1; 2077 goto done; 2078 } 2079 2080 fwdata = firmware + offset; 2081 dnld_cmd = le32_to_cpu(fwdata->header.dnld_cmd); 2082 data_len = le32_to_cpu(fwdata->header.data_length); 2083 2084 /* Skip past header */ 2085 offset += sizeof(fwdata->header); 2086 2087 switch (dnld_cmd) { 2088 case MWIFIEX_FW_DNLD_CMD_1: 2089 if (offset + data_len < data_len) { 2090 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2091 ret = -1; 2092 goto done; 2093 } 2094 2095 /* Image start with cmd1, already wifi-only firmware */ 2096 if (!first_cmd) { 2097 mwifiex_dbg(adapter, MSG, 2098 "input wifi-only firmware\n"); 2099 return 0; 2100 } 2101 2102 if (!cmd7_before) { 2103 mwifiex_dbg(adapter, ERROR, 2104 "no cmd7 before cmd1!\n"); 2105 ret = -1; 2106 goto done; 2107 } 2108 offset += data_len; 2109 break; 2110 case MWIFIEX_FW_DNLD_CMD_5: 2111 first_cmd = true; 2112 /* Check for integer overflow */ 2113 if (offset + data_len < data_len) { 2114 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2115 ret = -1; 2116 goto done; 2117 } 2118 offset += data_len; 2119 break; 2120 case MWIFIEX_FW_DNLD_CMD_6: 2121 first_cmd = true; 2122 /* Check for integer overflow */ 2123 if (offset + data_len < data_len) { 2124 mwifiex_dbg(adapter, ERROR, "bad FW parse\n"); 2125 ret = -1; 2126 goto done; 2127 } 2128 offset += data_len; 2129 if (offset >= firmware_len) { 2130 mwifiex_dbg(adapter, ERROR, 2131 "extract wifi-only fw failure!\n"); 2132 ret = -1; 2133 } else { 2134 ret = offset; 2135 } 2136 goto done; 2137 case MWIFIEX_FW_DNLD_CMD_7: 2138 first_cmd = true; 2139 cmd7_before = true; 2140 break; 2141 default: 2142 mwifiex_dbg(adapter, ERROR, "unknown dnld_cmd %d\n", 2143 dnld_cmd); 2144 ret = -1; 2145 goto done; 2146 } 2147 } 2148 2149done: 2150 return ret; 2151} 2152 2153/* 2154 * This function downloads the firmware to the card. 2155 * 2156 * Firmware is downloaded to the card in blocks. Every block download 2157 * is tested for CRC errors, and retried a number of times before 2158 * returning failure. 2159 */ 2160static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, 2161 struct mwifiex_fw_image *fw) 2162{ 2163 int ret; 2164 u8 *firmware = fw->fw_buf; 2165 u32 firmware_len = fw->fw_len; 2166 u32 offset = 0; 2167 struct sk_buff *skb; 2168 u32 txlen, tx_blocks = 0, tries, len, val; 2169 u32 block_retry_cnt = 0; 2170 struct pcie_service_card *card = adapter->card; 2171 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2172 2173 if (!firmware || !firmware_len) { 2174 mwifiex_dbg(adapter, ERROR, 2175 "No firmware image found! Terminating download\n"); 2176 return -1; 2177 } 2178 2179 mwifiex_dbg(adapter, INFO, 2180 "info: Downloading FW image (%d bytes)\n", 2181 firmware_len); 2182 2183 mwifiex_pcie_disable_host_int(adapter); 2184 2185 skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); 2186 if (!skb) { 2187 ret = -ENOMEM; 2188 goto done; 2189 } 2190 2191 ret = mwifiex_read_reg(adapter, PCIE_SCRATCH_13_REG, &val); 2192 if (ret) { 2193 mwifiex_dbg(adapter, FATAL, "Failed to read scratch register 13\n"); 2194 goto done; 2195 } 2196 2197 /* PCIE FLR case: extract wifi part from combo firmware*/ 2198 if (val == MWIFIEX_PCIE_FLR_HAPPENS) { 2199 ret = mwifiex_extract_wifi_fw(adapter, firmware, firmware_len); 2200 if (ret < 0) { 2201 mwifiex_dbg(adapter, ERROR, "Failed to extract wifi fw\n"); 2202 goto done; 2203 } 2204 offset = ret; 2205 mwifiex_dbg(adapter, MSG, 2206 "info: dnld wifi firmware from %d bytes\n", offset); 2207 } 2208 2209 /* Perform firmware data transfer */ 2210 do { 2211 u32 ireg_intr = 0; 2212 2213 /* More data? */ 2214 if (offset >= firmware_len) 2215 break; 2216 2217 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2218 ret = mwifiex_read_reg(adapter, reg->cmd_size, 2219 &len); 2220 if (ret) { 2221 mwifiex_dbg(adapter, FATAL, 2222 "Failed reading len from boot code\n"); 2223 goto done; 2224 } 2225 if (len) 2226 break; 2227 usleep_range(10, 20); 2228 } 2229 2230 if (!len) { 2231 break; 2232 } else if (len > MWIFIEX_UPLD_SIZE) { 2233 mwifiex_dbg(adapter, ERROR, 2234 "FW download failure @ %d, invalid length %d\n", 2235 offset, len); 2236 ret = -1; 2237 goto done; 2238 } 2239 2240 txlen = len; 2241 2242 if (len & BIT(0)) { 2243 block_retry_cnt++; 2244 if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) { 2245 mwifiex_dbg(adapter, ERROR, 2246 "FW download failure @ %d, over max\t" 2247 "retry count\n", offset); 2248 ret = -1; 2249 goto done; 2250 } 2251 mwifiex_dbg(adapter, ERROR, 2252 "FW CRC error indicated by the\t" 2253 "helper: len = 0x%04X, txlen = %d\n", 2254 len, txlen); 2255 len &= ~BIT(0); 2256 /* Setting this to 0 to resend from same offset */ 2257 txlen = 0; 2258 } else { 2259 block_retry_cnt = 0; 2260 /* Set blocksize to transfer - checking for 2261 last block */ 2262 if (firmware_len - offset < txlen) 2263 txlen = firmware_len - offset; 2264 2265 tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / 2266 card->pcie.blksz_fw_dl; 2267 2268 /* Copy payload to buffer */ 2269 memmove(skb->data, &firmware[offset], txlen); 2270 } 2271 2272 skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); 2273 skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); 2274 2275 /* Send the boot command to device */ 2276 if (mwifiex_pcie_send_boot_cmd(adapter, skb)) { 2277 mwifiex_dbg(adapter, ERROR, 2278 "Failed to send firmware download command\n"); 2279 ret = -1; 2280 goto done; 2281 } 2282 2283 /* Wait for the command done interrupt */ 2284 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2285 if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS, 2286 &ireg_intr)) { 2287 mwifiex_dbg(adapter, ERROR, 2288 "%s: Failed to read\t" 2289 "interrupt status during fw dnld.\n", 2290 __func__); 2291 mwifiex_unmap_pci_memory(adapter, skb, 2292 DMA_TO_DEVICE); 2293 ret = -1; 2294 goto done; 2295 } 2296 if (!(ireg_intr & CPU_INTR_DOOR_BELL)) 2297 break; 2298 usleep_range(10, 20); 2299 } 2300 if (ireg_intr & CPU_INTR_DOOR_BELL) { 2301 mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n", 2302 __func__); 2303 mwifiex_unmap_pci_memory(adapter, skb, 2304 DMA_TO_DEVICE); 2305 ret = -1; 2306 goto done; 2307 } 2308 2309 mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); 2310 2311 offset += txlen; 2312 } while (true); 2313 2314 mwifiex_dbg(adapter, MSG, 2315 "info: FW download over, size %d bytes\n", offset); 2316 2317 ret = 0; 2318 2319done: 2320 dev_kfree_skb_any(skb); 2321 return ret; 2322} 2323 2324/* 2325 * This function checks the firmware status in card. 2326 */ 2327static int 2328mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num) 2329{ 2330 int ret = 0; 2331 u32 firmware_stat; 2332 struct pcie_service_card *card = adapter->card; 2333 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2334 u32 tries; 2335 2336 /* Mask spurios interrupts */ 2337 mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK, HOST_INTR_MASK); 2338 2339 mwifiex_dbg(adapter, INFO, 2340 "Setting driver ready signature\n"); 2341 2342 mwifiex_write_reg(adapter, reg->drv_rdy, FIRMWARE_READY_PCIE); 2343 2344 /* Wait for firmware initialization event */ 2345 for (tries = 0; tries < poll_num; tries++) { 2346 if (mwifiex_read_reg(adapter, reg->fw_status, 2347 &firmware_stat)) 2348 ret = -1; 2349 else 2350 ret = 0; 2351 2352 mwifiex_dbg(adapter, INFO, "Try %d if FW is ready <%d,%#x>", 2353 tries, ret, firmware_stat); 2354 2355 if (ret) 2356 continue; 2357 if (firmware_stat == FIRMWARE_READY_PCIE) { 2358 ret = 0; 2359 break; 2360 } else { 2361 msleep(100); 2362 ret = -1; 2363 } 2364 } 2365 2366 return ret; 2367} 2368 2369/* This function checks if WLAN is the winner. 2370 */ 2371static int 2372mwifiex_check_winner_status(struct mwifiex_adapter *adapter) 2373{ 2374 u32 winner = 0; 2375 int ret = 0; 2376 struct pcie_service_card *card = adapter->card; 2377 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2378 2379 if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) { 2380 ret = -1; 2381 } else if (!winner) { 2382 mwifiex_dbg(adapter, INFO, "PCI-E is the winner\n"); 2383 adapter->winner = 1; 2384 } else { 2385 mwifiex_dbg(adapter, ERROR, 2386 "PCI-E is not the winner <%#x>", winner); 2387 } 2388 2389 return ret; 2390} 2391 2392/* 2393 * This function reads the interrupt status from card. 2394 */ 2395static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter, 2396 int msg_id) 2397{ 2398 u32 pcie_ireg; 2399 unsigned long flags; 2400 struct pcie_service_card *card = adapter->card; 2401 2402 if (card->msi_enable) { 2403 spin_lock_irqsave(&adapter->int_lock, flags); 2404 adapter->int_status = 1; 2405 spin_unlock_irqrestore(&adapter->int_lock, flags); 2406 return; 2407 } 2408 2409 if (!mwifiex_pcie_ok_to_access_hw(adapter)) 2410 return; 2411 2412 if (card->msix_enable && msg_id >= 0) { 2413 pcie_ireg = BIT(msg_id); 2414 } else { 2415 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2416 &pcie_ireg)) { 2417 mwifiex_dbg(adapter, ERROR, "Read register failed\n"); 2418 return; 2419 } 2420 2421 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg) 2422 return; 2423 2424 2425 mwifiex_pcie_disable_host_int(adapter); 2426 2427 /* Clear the pending interrupts */ 2428 mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS, ~pcie_ireg); 2429 } 2430 2431 if (!adapter->pps_uapsd_mode && 2432 adapter->ps_state == PS_STATE_SLEEP && 2433 mwifiex_pcie_ok_to_access_hw(adapter)) { 2434 /* Potentially for PCIe we could get other 2435 * interrupts like shared. Don't change power 2436 * state until cookie is set 2437 */ 2438 adapter->ps_state = PS_STATE_AWAKE; 2439 adapter->pm_wakeup_fw_try = false; 2440 del_timer(&adapter->wakeup_timer); 2441 } 2442 2443 spin_lock_irqsave(&adapter->int_lock, flags); 2444 adapter->int_status |= pcie_ireg; 2445 spin_unlock_irqrestore(&adapter->int_lock, flags); 2446 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg); 2447} 2448 2449/* 2450 * Interrupt handler for PCIe root port 2451 * 2452 * This function reads the interrupt status from firmware and assigns 2453 * the main process in workqueue which will handle the interrupt. 2454 */ 2455static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context) 2456{ 2457 struct mwifiex_msix_context *ctx = context; 2458 struct pci_dev *pdev = ctx->dev; 2459 struct pcie_service_card *card; 2460 struct mwifiex_adapter *adapter; 2461 2462 card = pci_get_drvdata(pdev); 2463 2464 if (!card->adapter) { 2465 pr_err("info: %s: card=%p adapter=%p\n", __func__, card, 2466 card ? card->adapter : NULL); 2467 goto exit; 2468 } 2469 adapter = card->adapter; 2470 2471 if (test_bit(MWIFIEX_SURPRISE_REMOVED, &adapter->work_flags)) 2472 goto exit; 2473 2474 if (card->msix_enable) 2475 mwifiex_interrupt_status(adapter, ctx->msg_id); 2476 else 2477 mwifiex_interrupt_status(adapter, -1); 2478 2479 mwifiex_queue_main_work(adapter); 2480 2481exit: 2482 return IRQ_HANDLED; 2483} 2484 2485/* 2486 * This function checks the current interrupt status. 2487 * 2488 * The following interrupts are checked and handled by this function - 2489 * - Data sent 2490 * - Command sent 2491 * - Command received 2492 * - Packets received 2493 * - Events received 2494 * 2495 * In case of Rx packets received, the packets are uploaded from card to 2496 * host and processed accordingly. 2497 */ 2498static int mwifiex_process_int_status(struct mwifiex_adapter *adapter) 2499{ 2500 int ret; 2501 u32 pcie_ireg = 0; 2502 unsigned long flags; 2503 struct pcie_service_card *card = adapter->card; 2504 2505 spin_lock_irqsave(&adapter->int_lock, flags); 2506 if (!card->msi_enable) { 2507 /* Clear out unused interrupts */ 2508 pcie_ireg = adapter->int_status; 2509 } 2510 adapter->int_status = 0; 2511 spin_unlock_irqrestore(&adapter->int_lock, flags); 2512 2513 if (card->msi_enable) { 2514 if (mwifiex_pcie_ok_to_access_hw(adapter)) { 2515 if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, 2516 &pcie_ireg)) { 2517 mwifiex_dbg(adapter, ERROR, 2518 "Read register failed\n"); 2519 return -1; 2520 } 2521 2522 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { 2523 mwifiex_write_reg(adapter, 2524 PCIE_HOST_INT_STATUS, 2525 ~pcie_ireg); 2526 if (!adapter->pps_uapsd_mode && 2527 adapter->ps_state == PS_STATE_SLEEP) { 2528 adapter->ps_state = PS_STATE_AWAKE; 2529 adapter->pm_wakeup_fw_try = false; 2530 del_timer(&adapter->wakeup_timer); 2531 } 2532 } 2533 } 2534 } 2535 2536 if (pcie_ireg & HOST_INTR_DNLD_DONE) { 2537 mwifiex_dbg(adapter, INTR, "info: TX DNLD Done\n"); 2538 ret = mwifiex_pcie_send_data_complete(adapter); 2539 if (ret) 2540 return ret; 2541 } 2542 if (pcie_ireg & HOST_INTR_UPLD_RDY) { 2543 mwifiex_dbg(adapter, INTR, "info: Rx DATA\n"); 2544 ret = mwifiex_pcie_process_recv_data(adapter); 2545 if (ret) 2546 return ret; 2547 } 2548 if (pcie_ireg & HOST_INTR_EVENT_RDY) { 2549 mwifiex_dbg(adapter, INTR, "info: Rx EVENT\n"); 2550 ret = mwifiex_pcie_process_event_ready(adapter); 2551 if (ret) 2552 return ret; 2553 } 2554 if (pcie_ireg & HOST_INTR_CMD_DONE) { 2555 if (adapter->cmd_sent) { 2556 mwifiex_dbg(adapter, INTR, 2557 "info: CMD sent Interrupt\n"); 2558 adapter->cmd_sent = false; 2559 } 2560 /* Handle command response */ 2561 ret = mwifiex_pcie_process_cmd_complete(adapter); 2562 if (ret) 2563 return ret; 2564 } 2565 2566 mwifiex_dbg(adapter, INTR, 2567 "info: cmd_sent=%d data_sent=%d\n", 2568 adapter->cmd_sent, adapter->data_sent); 2569 if (!card->msi_enable && !card->msix_enable && 2570 adapter->ps_state != PS_STATE_SLEEP) 2571 mwifiex_pcie_enable_host_int(adapter); 2572 2573 return 0; 2574} 2575 2576/* 2577 * This function downloads data from driver to card. 2578 * 2579 * Both commands and data packets are transferred to the card by this 2580 * function. 2581 * 2582 * This function adds the PCIE specific header to the front of the buffer 2583 * before transferring. The header contains the length of the packet and 2584 * the type. The firmware handles the packets based upon this set type. 2585 */ 2586static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type, 2587 struct sk_buff *skb, 2588 struct mwifiex_tx_param *tx_param) 2589{ 2590 if (!skb) { 2591 mwifiex_dbg(adapter, ERROR, 2592 "Passed NULL skb to %s\n", __func__); 2593 return -1; 2594 } 2595 2596 if (type == MWIFIEX_TYPE_DATA) 2597 return mwifiex_pcie_send_data(adapter, skb, tx_param); 2598 else if (type == MWIFIEX_TYPE_CMD) 2599 return mwifiex_pcie_send_cmd(adapter, skb); 2600 2601 return 0; 2602} 2603 2604/* Function to dump PCIE scratch registers in case of FW crash 2605 */ 2606static int 2607mwifiex_pcie_reg_dump(struct mwifiex_adapter *adapter, char *drv_buf) 2608{ 2609 char *p = drv_buf; 2610 char buf[256], *ptr; 2611 int i; 2612 u32 value; 2613 struct pcie_service_card *card = adapter->card; 2614 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2615 int pcie_scratch_reg[] = {PCIE_SCRATCH_12_REG, 2616 PCIE_SCRATCH_14_REG, 2617 PCIE_SCRATCH_15_REG}; 2618 2619 if (!p) 2620 return 0; 2621 2622 mwifiex_dbg(adapter, MSG, "PCIE register dump start\n"); 2623 2624 if (mwifiex_read_reg(adapter, reg->fw_status, &value)) { 2625 mwifiex_dbg(adapter, ERROR, "failed to read firmware status"); 2626 return 0; 2627 } 2628 2629 ptr = buf; 2630 mwifiex_dbg(adapter, MSG, "pcie scratch register:"); 2631 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) { 2632 mwifiex_read_reg(adapter, pcie_scratch_reg[i], &value); 2633 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n", 2634 pcie_scratch_reg[i], value); 2635 } 2636 2637 mwifiex_dbg(adapter, MSG, "%s\n", buf); 2638 p += sprintf(p, "%s\n", buf); 2639 2640 mwifiex_dbg(adapter, MSG, "PCIE register dump end\n"); 2641 2642 return p - drv_buf; 2643} 2644 2645/* This function read/write firmware */ 2646static enum rdwr_status 2647mwifiex_pcie_rdwr_firmware(struct mwifiex_adapter *adapter, u8 doneflag) 2648{ 2649 int tries; 2650 u8 ctrl_data; 2651 u32 fw_status; 2652 struct pcie_service_card *card = adapter->card; 2653 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2654 2655 if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) 2656 return RDWR_STATUS_FAILURE; 2657 2658 mwifiex_write_reg(adapter, reg->fw_dump_ctrl, reg->fw_dump_host_ready); 2659 2660 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { 2661 mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data); 2662 if (ctrl_data == FW_DUMP_DONE) 2663 return RDWR_STATUS_SUCCESS; 2664 if (doneflag && ctrl_data == doneflag) 2665 return RDWR_STATUS_DONE; 2666 if (ctrl_data != reg->fw_dump_host_ready) { 2667 mwifiex_dbg(adapter, WARN, 2668 "The ctrl reg was changed, re-try again!\n"); 2669 mwifiex_write_reg(adapter, reg->fw_dump_ctrl, 2670 reg->fw_dump_host_ready); 2671 } 2672 usleep_range(100, 200); 2673 } 2674 2675 mwifiex_dbg(adapter, ERROR, "Fail to pull ctrl_data\n"); 2676 return RDWR_STATUS_FAILURE; 2677} 2678 2679/* This function dump firmware memory to file */ 2680static void mwifiex_pcie_fw_dump(struct mwifiex_adapter *adapter) 2681{ 2682 struct pcie_service_card *card = adapter->card; 2683 const struct mwifiex_pcie_card_reg *creg = card->pcie.reg; 2684 unsigned int reg, reg_start, reg_end; 2685 u8 *dbg_ptr, *end_ptr, *tmp_ptr, fw_dump_num, dump_num; 2686 u8 idx, i, read_reg, doneflag = 0; 2687 enum rdwr_status stat; 2688 u32 memory_size; 2689 2690 if (!card->pcie.can_dump_fw) 2691 return; 2692 2693 for (idx = 0; idx < adapter->num_mem_types; idx++) { 2694 struct memory_type_mapping *entry = 2695 &adapter->mem_type_mapping_tbl[idx]; 2696 2697 if (entry->mem_ptr) { 2698 vfree(entry->mem_ptr); 2699 entry->mem_ptr = NULL; 2700 } 2701 entry->mem_size = 0; 2702 } 2703 2704 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump start ==\n"); 2705 2706 /* Read the number of the memories which will dump */ 2707 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2708 if (stat == RDWR_STATUS_FAILURE) 2709 return; 2710 2711 reg = creg->fw_dump_start; 2712 mwifiex_read_reg_byte(adapter, reg, &fw_dump_num); 2713 2714 /* W8997 chipset firmware dump will be restore in single region*/ 2715 if (fw_dump_num == 0) 2716 dump_num = 1; 2717 else 2718 dump_num = fw_dump_num; 2719 2720 /* Read the length of every memory which will dump */ 2721 for (idx = 0; idx < dump_num; idx++) { 2722 struct memory_type_mapping *entry = 2723 &adapter->mem_type_mapping_tbl[idx]; 2724 memory_size = 0; 2725 if (fw_dump_num != 0) { 2726 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2727 if (stat == RDWR_STATUS_FAILURE) 2728 return; 2729 2730 reg = creg->fw_dump_start; 2731 for (i = 0; i < 4; i++) { 2732 mwifiex_read_reg_byte(adapter, reg, &read_reg); 2733 memory_size |= (read_reg << (i * 8)); 2734 reg++; 2735 } 2736 } else { 2737 memory_size = MWIFIEX_FW_DUMP_MAX_MEMSIZE; 2738 } 2739 2740 if (memory_size == 0) { 2741 mwifiex_dbg(adapter, MSG, "Firmware dump Finished!\n"); 2742 mwifiex_write_reg(adapter, creg->fw_dump_ctrl, 2743 creg->fw_dump_read_done); 2744 break; 2745 } 2746 2747 mwifiex_dbg(adapter, DUMP, 2748 "%s_SIZE=0x%x\n", entry->mem_name, memory_size); 2749 entry->mem_ptr = vmalloc(memory_size + 1); 2750 entry->mem_size = memory_size; 2751 if (!entry->mem_ptr) { 2752 mwifiex_dbg(adapter, ERROR, 2753 "Vmalloc %s failed\n", entry->mem_name); 2754 return; 2755 } 2756 dbg_ptr = entry->mem_ptr; 2757 end_ptr = dbg_ptr + memory_size; 2758 2759 doneflag = entry->done_flag; 2760 mwifiex_dbg(adapter, DUMP, "Start %s output, please wait...\n", 2761 entry->mem_name); 2762 2763 do { 2764 stat = mwifiex_pcie_rdwr_firmware(adapter, doneflag); 2765 if (RDWR_STATUS_FAILURE == stat) 2766 return; 2767 2768 reg_start = creg->fw_dump_start; 2769 reg_end = creg->fw_dump_end; 2770 for (reg = reg_start; reg <= reg_end; reg++) { 2771 mwifiex_read_reg_byte(adapter, reg, dbg_ptr); 2772 if (dbg_ptr < end_ptr) { 2773 dbg_ptr++; 2774 continue; 2775 } 2776 mwifiex_dbg(adapter, ERROR, 2777 "pre-allocated buf not enough\n"); 2778 tmp_ptr = 2779 vzalloc(memory_size + MWIFIEX_SIZE_4K); 2780 if (!tmp_ptr) 2781 return; 2782 memcpy(tmp_ptr, entry->mem_ptr, memory_size); 2783 vfree(entry->mem_ptr); 2784 entry->mem_ptr = tmp_ptr; 2785 tmp_ptr = NULL; 2786 dbg_ptr = entry->mem_ptr + memory_size; 2787 memory_size += MWIFIEX_SIZE_4K; 2788 end_ptr = entry->mem_ptr + memory_size; 2789 } 2790 2791 if (stat != RDWR_STATUS_DONE) 2792 continue; 2793 2794 mwifiex_dbg(adapter, DUMP, 2795 "%s done: size=0x%tx\n", 2796 entry->mem_name, dbg_ptr - entry->mem_ptr); 2797 break; 2798 } while (true); 2799 } 2800 mwifiex_dbg(adapter, MSG, "== mwifiex firmware dump end ==\n"); 2801} 2802 2803static void mwifiex_pcie_device_dump_work(struct mwifiex_adapter *adapter) 2804{ 2805 adapter->devdump_data = vzalloc(MWIFIEX_FW_DUMP_SIZE); 2806 if (!adapter->devdump_data) { 2807 mwifiex_dbg(adapter, ERROR, 2808 "vzalloc devdump data failure!\n"); 2809 return; 2810 } 2811 2812 mwifiex_drv_info_dump(adapter); 2813 mwifiex_pcie_fw_dump(adapter); 2814 mwifiex_prepare_fw_dump_info(adapter); 2815 mwifiex_upload_device_dump(adapter); 2816} 2817 2818static void mwifiex_pcie_card_reset_work(struct mwifiex_adapter *adapter) 2819{ 2820 struct pcie_service_card *card = adapter->card; 2821 2822 /* We can't afford to wait here; remove() might be waiting on us. If we 2823 * can't grab the device lock, maybe we'll get another chance later. 2824 */ 2825 pci_try_reset_function(card->dev); 2826} 2827 2828static void mwifiex_pcie_work(struct work_struct *work) 2829{ 2830 struct pcie_service_card *card = 2831 container_of(work, struct pcie_service_card, work); 2832 2833 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 2834 &card->work_flags)) 2835 mwifiex_pcie_device_dump_work(card->adapter); 2836 if (test_and_clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, 2837 &card->work_flags)) 2838 mwifiex_pcie_card_reset_work(card->adapter); 2839} 2840 2841/* This function dumps FW information */ 2842static void mwifiex_pcie_device_dump(struct mwifiex_adapter *adapter) 2843{ 2844 struct pcie_service_card *card = adapter->card; 2845 2846 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, 2847 &card->work_flags)) 2848 schedule_work(&card->work); 2849} 2850 2851static void mwifiex_pcie_card_reset(struct mwifiex_adapter *adapter) 2852{ 2853 struct pcie_service_card *card = adapter->card; 2854 2855 if (!test_and_set_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags)) 2856 schedule_work(&card->work); 2857} 2858 2859static int mwifiex_pcie_alloc_buffers(struct mwifiex_adapter *adapter) 2860{ 2861 struct pcie_service_card *card = adapter->card; 2862 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2863 int ret; 2864 2865 card->cmdrsp_buf = NULL; 2866 ret = mwifiex_pcie_create_txbd_ring(adapter); 2867 if (ret) { 2868 mwifiex_dbg(adapter, ERROR, "Failed to create txbd ring\n"); 2869 goto err_cre_txbd; 2870 } 2871 2872 ret = mwifiex_pcie_create_rxbd_ring(adapter); 2873 if (ret) { 2874 mwifiex_dbg(adapter, ERROR, "Failed to create rxbd ring\n"); 2875 goto err_cre_rxbd; 2876 } 2877 2878 ret = mwifiex_pcie_create_evtbd_ring(adapter); 2879 if (ret) { 2880 mwifiex_dbg(adapter, ERROR, "Failed to create evtbd ring\n"); 2881 goto err_cre_evtbd; 2882 } 2883 2884 ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter); 2885 if (ret) { 2886 mwifiex_dbg(adapter, ERROR, "Failed to allocate cmdbuf buffer\n"); 2887 goto err_alloc_cmdbuf; 2888 } 2889 2890 if (reg->sleep_cookie) { 2891 ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter); 2892 if (ret) { 2893 mwifiex_dbg(adapter, ERROR, "Failed to allocate sleep_cookie buffer\n"); 2894 goto err_alloc_cookie; 2895 } 2896 } else { 2897 card->sleep_cookie_vbase = NULL; 2898 } 2899 2900 return 0; 2901 2902err_alloc_cookie: 2903 mwifiex_pcie_delete_cmdrsp_buf(adapter); 2904err_alloc_cmdbuf: 2905 mwifiex_pcie_delete_evtbd_ring(adapter); 2906err_cre_evtbd: 2907 mwifiex_pcie_delete_rxbd_ring(adapter); 2908err_cre_rxbd: 2909 mwifiex_pcie_delete_txbd_ring(adapter); 2910err_cre_txbd: 2911 return ret; 2912} 2913 2914static void mwifiex_pcie_free_buffers(struct mwifiex_adapter *adapter) 2915{ 2916 struct pcie_service_card *card = adapter->card; 2917 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 2918 2919 if (reg->sleep_cookie) 2920 mwifiex_pcie_delete_sleep_cookie_buf(adapter); 2921 2922 mwifiex_pcie_delete_cmdrsp_buf(adapter); 2923 mwifiex_pcie_delete_evtbd_ring(adapter); 2924 mwifiex_pcie_delete_rxbd_ring(adapter); 2925 mwifiex_pcie_delete_txbd_ring(adapter); 2926} 2927 2928/* 2929 * This function initializes the PCI-E host memory space, WCB rings, etc. 2930 */ 2931static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) 2932{ 2933 struct pcie_service_card *card = adapter->card; 2934 int ret; 2935 struct pci_dev *pdev = card->dev; 2936 2937 pci_set_drvdata(pdev, card); 2938 2939 ret = pci_enable_device(pdev); 2940 if (ret) 2941 goto err_enable_dev; 2942 2943 pci_set_master(pdev); 2944 2945 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2946 if (ret) { 2947 pr_err("dma_set_mask(32) failed: %d\n", ret); 2948 goto err_set_dma_mask; 2949 } 2950 2951 ret = pci_request_region(pdev, 0, DRV_NAME); 2952 if (ret) { 2953 pr_err("req_reg(0) error\n"); 2954 goto err_req_region0; 2955 } 2956 card->pci_mmap = pci_iomap(pdev, 0, 0); 2957 if (!card->pci_mmap) { 2958 pr_err("iomap(0) error\n"); 2959 ret = -EIO; 2960 goto err_iomap0; 2961 } 2962 ret = pci_request_region(pdev, 2, DRV_NAME); 2963 if (ret) { 2964 pr_err("req_reg(2) error\n"); 2965 goto err_req_region2; 2966 } 2967 card->pci_mmap1 = pci_iomap(pdev, 2, 0); 2968 if (!card->pci_mmap1) { 2969 pr_err("iomap(2) error\n"); 2970 ret = -EIO; 2971 goto err_iomap2; 2972 } 2973 2974 pr_notice("PCI memory map Virt0: %pK PCI memory map Virt2: %pK\n", 2975 card->pci_mmap, card->pci_mmap1); 2976 2977 ret = mwifiex_pcie_alloc_buffers(adapter); 2978 if (ret) 2979 goto err_alloc_buffers; 2980 2981 if (pdev->device == PCIE_DEVICE_ID_MARVELL_88W8897) 2982 adapter->ignore_btcoex_events = true; 2983 2984 return 0; 2985 2986err_alloc_buffers: 2987 pci_iounmap(pdev, card->pci_mmap1); 2988err_iomap2: 2989 pci_release_region(pdev, 2); 2990err_req_region2: 2991 pci_iounmap(pdev, card->pci_mmap); 2992err_iomap0: 2993 pci_release_region(pdev, 0); 2994err_req_region0: 2995err_set_dma_mask: 2996 pci_disable_device(pdev); 2997err_enable_dev: 2998 return ret; 2999} 3000 3001/* 3002 * This function cleans up the allocated card buffers. 3003 */ 3004static void mwifiex_cleanup_pcie(struct mwifiex_adapter *adapter) 3005{ 3006 struct pcie_service_card *card = adapter->card; 3007 struct pci_dev *pdev = card->dev; 3008 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3009 u32 fw_status; 3010 3011 /* Perform the cancel_work_sync() only when we're not resetting 3012 * the card. It's because that function never returns if we're 3013 * in reset path. If we're here when resetting the card, it means 3014 * that we failed to reset the card (reset failure path). 3015 */ 3016 if (!card->pci_reset_ongoing) { 3017 mwifiex_dbg(adapter, MSG, "performing cancel_work_sync()...\n"); 3018 cancel_work_sync(&card->work); 3019 mwifiex_dbg(adapter, MSG, "cancel_work_sync() done\n"); 3020 } else { 3021 mwifiex_dbg(adapter, MSG, 3022 "skipped cancel_work_sync() because we're in card reset failure path\n"); 3023 } 3024 3025 mwifiex_read_reg(adapter, reg->fw_status, &fw_status); 3026 if (fw_status == FIRMWARE_READY_PCIE) { 3027 mwifiex_dbg(adapter, INFO, 3028 "Clearing driver ready signature\n"); 3029 mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000); 3030 } 3031 3032 pci_disable_device(pdev); 3033 3034 pci_iounmap(pdev, card->pci_mmap); 3035 pci_iounmap(pdev, card->pci_mmap1); 3036 pci_release_region(pdev, 2); 3037 pci_release_region(pdev, 0); 3038 3039 mwifiex_pcie_free_buffers(adapter); 3040} 3041 3042static int mwifiex_pcie_request_irq(struct mwifiex_adapter *adapter) 3043{ 3044 int ret, i, j; 3045 struct pcie_service_card *card = adapter->card; 3046 struct pci_dev *pdev = card->dev; 3047 3048 if (card->pcie.reg->msix_support) { 3049 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3050 card->msix_entries[i].entry = i; 3051 ret = pci_enable_msix_exact(pdev, card->msix_entries, 3052 MWIFIEX_NUM_MSIX_VECTORS); 3053 if (!ret) { 3054 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) { 3055 card->msix_ctx[i].dev = pdev; 3056 card->msix_ctx[i].msg_id = i; 3057 3058 ret = request_irq(card->msix_entries[i].vector, 3059 mwifiex_pcie_interrupt, 0, 3060 "MWIFIEX_PCIE_MSIX", 3061 &card->msix_ctx[i]); 3062 if (ret) 3063 break; 3064 } 3065 3066 if (ret) { 3067 mwifiex_dbg(adapter, INFO, "request_irq fail: %d\n", 3068 ret); 3069 for (j = 0; j < i; j++) 3070 free_irq(card->msix_entries[j].vector, 3071 &card->msix_ctx[i]); 3072 pci_disable_msix(pdev); 3073 } else { 3074 mwifiex_dbg(adapter, MSG, "MSIx enabled!"); 3075 card->msix_enable = 1; 3076 return 0; 3077 } 3078 } 3079 } 3080 3081 if (pci_enable_msi(pdev) != 0) 3082 pci_disable_msi(pdev); 3083 else 3084 card->msi_enable = 1; 3085 3086 mwifiex_dbg(adapter, INFO, "msi_enable = %d\n", card->msi_enable); 3087 3088 card->share_irq_ctx.dev = pdev; 3089 card->share_irq_ctx.msg_id = -1; 3090 ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED, 3091 "MRVL_PCIE", &card->share_irq_ctx); 3092 if (ret) { 3093 pr_err("request_irq failed: ret=%d\n", ret); 3094 return -1; 3095 } 3096 3097 return 0; 3098} 3099 3100/* 3101 * This function gets the firmware name for downloading by revision id 3102 * 3103 * Read revision id register to get revision id 3104 */ 3105static void mwifiex_pcie_get_fw_name(struct mwifiex_adapter *adapter) 3106{ 3107 int revision_id = 0; 3108 int version, magic; 3109 struct pcie_service_card *card = adapter->card; 3110 3111 switch (card->dev->device) { 3112 case PCIE_DEVICE_ID_MARVELL_88W8766P: 3113 strcpy(adapter->fw_name, PCIE8766_DEFAULT_FW_NAME); 3114 break; 3115 case PCIE_DEVICE_ID_MARVELL_88W8897: 3116 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000); 3117 mwifiex_read_reg(adapter, 0x0c58, &revision_id); 3118 revision_id &= 0xff00; 3119 switch (revision_id) { 3120 case PCIE8897_A0: 3121 strcpy(adapter->fw_name, PCIE8897_A0_FW_NAME); 3122 break; 3123 case PCIE8897_B0: 3124 strcpy(adapter->fw_name, PCIE8897_B0_FW_NAME); 3125 break; 3126 default: 3127 strcpy(adapter->fw_name, PCIE8897_DEFAULT_FW_NAME); 3128 3129 break; 3130 } 3131 break; 3132 case PCIE_DEVICE_ID_MARVELL_88W8997: 3133 mwifiex_read_reg(adapter, 0x8, &revision_id); 3134 mwifiex_read_reg(adapter, 0x0cd0, &version); 3135 mwifiex_read_reg(adapter, 0x0cd4, &magic); 3136 revision_id &= 0xff; 3137 version &= 0x7; 3138 magic &= 0xff; 3139 if (revision_id == PCIE8997_A1 && 3140 magic == CHIP_MAGIC_VALUE && 3141 version == CHIP_VER_PCIEUART) 3142 strcpy(adapter->fw_name, PCIEUART8997_FW_NAME_V4); 3143 else 3144 strcpy(adapter->fw_name, PCIEUSB8997_FW_NAME_V4); 3145 break; 3146 default: 3147 break; 3148 } 3149} 3150 3151/* 3152 * This function registers the PCIE device. 3153 * 3154 * PCIE IRQ is claimed, block size is set and driver data is initialized. 3155 */ 3156static int mwifiex_register_dev(struct mwifiex_adapter *adapter) 3157{ 3158 struct pcie_service_card *card = adapter->card; 3159 3160 /* save adapter pointer in card */ 3161 card->adapter = adapter; 3162 3163 if (mwifiex_pcie_request_irq(adapter)) 3164 return -1; 3165 3166 adapter->tx_buf_size = card->pcie.tx_buf_size; 3167 adapter->mem_type_mapping_tbl = card->pcie.mem_type_mapping_tbl; 3168 adapter->num_mem_types = card->pcie.num_mem_types; 3169 adapter->ext_scan = card->pcie.can_ext_scan; 3170 mwifiex_pcie_get_fw_name(adapter); 3171 3172 return 0; 3173} 3174 3175/* 3176 * This function unregisters the PCIE device. 3177 * 3178 * The PCIE IRQ is released, the function is disabled and driver 3179 * data is set to null. 3180 */ 3181static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter) 3182{ 3183 struct pcie_service_card *card = adapter->card; 3184 struct pci_dev *pdev = card->dev; 3185 int i; 3186 3187 if (card->msix_enable) { 3188 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3189 synchronize_irq(card->msix_entries[i].vector); 3190 3191 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) 3192 free_irq(card->msix_entries[i].vector, 3193 &card->msix_ctx[i]); 3194 3195 card->msix_enable = 0; 3196 pci_disable_msix(pdev); 3197 } else { 3198 mwifiex_dbg(adapter, INFO, 3199 "%s(): calling free_irq()\n", __func__); 3200 free_irq(card->dev->irq, &card->share_irq_ctx); 3201 3202 if (card->msi_enable) 3203 pci_disable_msi(pdev); 3204 } 3205 card->adapter = NULL; 3206} 3207 3208/* 3209 * This function initializes the PCI-E host memory space, WCB rings, etc., 3210 * similar to mwifiex_init_pcie(), but without resetting PCI-E state. 3211 */ 3212static void mwifiex_pcie_up_dev(struct mwifiex_adapter *adapter) 3213{ 3214 struct pcie_service_card *card = adapter->card; 3215 struct pci_dev *pdev = card->dev; 3216 3217 /* tx_buf_size might be changed to 3584 by firmware during 3218 * data transfer, we should reset it to default size. 3219 */ 3220 adapter->tx_buf_size = card->pcie.tx_buf_size; 3221 3222 mwifiex_pcie_alloc_buffers(adapter); 3223 3224 pci_set_master(pdev); 3225} 3226 3227/* This function cleans up the PCI-E host memory space. */ 3228static void mwifiex_pcie_down_dev(struct mwifiex_adapter *adapter) 3229{ 3230 struct pcie_service_card *card = adapter->card; 3231 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; 3232 struct pci_dev *pdev = card->dev; 3233 3234 mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000); 3235 3236 pci_clear_master(pdev); 3237 3238 adapter->seq_num = 0; 3239 3240 mwifiex_pcie_free_buffers(adapter); 3241} 3242 3243static struct mwifiex_if_ops pcie_ops = { 3244 .init_if = mwifiex_init_pcie, 3245 .cleanup_if = mwifiex_cleanup_pcie, 3246 .check_fw_status = mwifiex_check_fw_status, 3247 .check_winner_status = mwifiex_check_winner_status, 3248 .prog_fw = mwifiex_prog_fw_w_helper, 3249 .register_dev = mwifiex_register_dev, 3250 .unregister_dev = mwifiex_unregister_dev, 3251 .enable_int = mwifiex_pcie_enable_host_int, 3252 .disable_int = mwifiex_pcie_disable_host_int, 3253 .process_int_status = mwifiex_process_int_status, 3254 .host_to_card = mwifiex_pcie_host_to_card, 3255 .wakeup = mwifiex_pm_wakeup_card, 3256 .wakeup_complete = mwifiex_pm_wakeup_card_complete, 3257 3258 /* PCIE specific */ 3259 .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete, 3260 .event_complete = mwifiex_pcie_event_complete, 3261 .update_mp_end_port = NULL, 3262 .cleanup_mpa_buf = NULL, 3263 .init_fw_port = mwifiex_pcie_init_fw_port, 3264 .clean_pcie_ring = mwifiex_clean_pcie_ring_buf, 3265 .card_reset = mwifiex_pcie_card_reset, 3266 .reg_dump = mwifiex_pcie_reg_dump, 3267 .device_dump = mwifiex_pcie_device_dump, 3268 .down_dev = mwifiex_pcie_down_dev, 3269 .up_dev = mwifiex_pcie_up_dev, 3270}; 3271 3272module_pci_driver(mwifiex_pcie); 3273 3274MODULE_AUTHOR("Marvell International Ltd."); 3275MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION); 3276MODULE_VERSION(PCIE_VERSION); 3277MODULE_LICENSE("GPL v2"); 3278MODULE_FIRMWARE(PCIE8766_DEFAULT_FW_NAME); 3279MODULE_FIRMWARE(PCIE8897_DEFAULT_FW_NAME); 3280MODULE_FIRMWARE(PCIE8897_A0_FW_NAME); 3281MODULE_FIRMWARE(PCIE8897_B0_FW_NAME); 3282MODULE_FIRMWARE(PCIEUART8997_FW_NAME_V4); 3283MODULE_FIRMWARE(PCIEUSB8997_FW_NAME_V4); 3284