1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * NXP Wireless LAN device driver: generic data structures and APIs
4 *
5 * Copyright 2011-2020 NXP
6 */
7
8#ifndef _MWIFIEX_DECL_H_
9#define _MWIFIEX_DECL_H_
10
11#undef pr_fmt
12#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
13
14#include <linux/wait.h>
15#include <linux/timer.h>
16#include <linux/ieee80211.h>
17#include <uapi/linux/if_arp.h>
18#include <net/cfg80211.h>
19
20#define MWIFIEX_BSS_COEX_COUNT	     2
21#define MWIFIEX_MAX_BSS_NUM         (3)
22
23#define MWIFIEX_DMA_ALIGN_SZ	    64
24#define MWIFIEX_RX_HEADROOM	    64
25#define MAX_TXPD_SZ		    32
26#define INTF_HDR_ALIGN		     4
27
28#define MWIFIEX_MIN_DATA_HEADER_LEN (MWIFIEX_DMA_ALIGN_SZ + INTF_HDR_ALIGN + \
29				     MAX_TXPD_SZ)
30#define MWIFIEX_MGMT_FRAME_HEADER_SIZE	8	/* sizeof(pkt_type)
31						 *   + sizeof(tx_control)
32						 */
33
34#define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED	2
35#define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED	16
36#define MWIFIEX_MAX_TDLS_PEER_SUPPORTED 8
37
38#define MWIFIEX_STA_AMPDU_DEF_TXWINSIZE        64
39#define MWIFIEX_STA_AMPDU_DEF_RXWINSIZE        64
40#define MWIFIEX_STA_COEX_AMPDU_DEF_RXWINSIZE   16
41
42#define MWIFIEX_UAP_AMPDU_DEF_TXWINSIZE        32
43
44#define MWIFIEX_UAP_COEX_AMPDU_DEF_RXWINSIZE   16
45
46#define MWIFIEX_UAP_AMPDU_DEF_RXWINSIZE        16
47#define MWIFIEX_11AC_STA_AMPDU_DEF_TXWINSIZE   64
48#define MWIFIEX_11AC_STA_AMPDU_DEF_RXWINSIZE   64
49#define MWIFIEX_11AC_UAP_AMPDU_DEF_TXWINSIZE   64
50#define MWIFIEX_11AC_UAP_AMPDU_DEF_RXWINSIZE   64
51
52#define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT  0xffff
53
54#define MWIFIEX_RATE_BITMAP_MCS0   32
55
56#define MWIFIEX_RX_DATA_BUF_SIZE     (4 * 1024)
57#define MWIFIEX_RX_CMD_BUF_SIZE	     (2 * 1024)
58
59#define MAX_BEACON_PERIOD                  (4000)
60#define MIN_BEACON_PERIOD                  (50)
61#define MAX_DTIM_PERIOD                    (100)
62#define MIN_DTIM_PERIOD                    (1)
63
64#define MWIFIEX_RTS_MIN_VALUE              (0)
65#define MWIFIEX_RTS_MAX_VALUE              (2347)
66#define MWIFIEX_FRAG_MIN_VALUE             (256)
67#define MWIFIEX_FRAG_MAX_VALUE             (2346)
68#define MWIFIEX_WMM_VERSION                0x01
69#define MWIFIEX_WMM_SUBTYPE                0x01
70
71#define MWIFIEX_RETRY_LIMIT                14
72#define MWIFIEX_SDIO_BLOCK_SIZE            256
73
74#define MWIFIEX_BUF_FLAG_REQUEUED_PKT      BIT(0)
75#define MWIFIEX_BUF_FLAG_BRIDGED_PKT	   BIT(1)
76#define MWIFIEX_BUF_FLAG_TDLS_PKT	   BIT(2)
77#define MWIFIEX_BUF_FLAG_EAPOL_TX_STATUS   BIT(3)
78#define MWIFIEX_BUF_FLAG_ACTION_TX_STATUS  BIT(4)
79#define MWIFIEX_BUF_FLAG_AGGR_PKT          BIT(5)
80
81#define MWIFIEX_BRIDGED_PKTS_THR_HIGH      1024
82#define MWIFIEX_BRIDGED_PKTS_THR_LOW        128
83
84#define MWIFIEX_TDLS_DISABLE_LINK             0x00
85#define MWIFIEX_TDLS_ENABLE_LINK              0x01
86#define MWIFIEX_TDLS_CREATE_LINK              0x02
87#define MWIFIEX_TDLS_CONFIG_LINK              0x03
88
89#define MWIFIEX_TDLS_RSSI_HIGH		50
90#define MWIFIEX_TDLS_RSSI_LOW		55
91#define MWIFIEX_TDLS_MAX_FAIL_COUNT      4
92#define MWIFIEX_AUTO_TDLS_IDLE_TIME     10
93
94/* 54M rates, index from 0 to 11 */
95#define MWIFIEX_RATE_INDEX_MCS0 12
96/* 12-27=MCS0-15(BW20) */
97#define MWIFIEX_BW20_MCS_NUM 15
98
99/* Rate index for OFDM 0 */
100#define MWIFIEX_RATE_INDEX_OFDM0   4
101
102#define MWIFIEX_MAX_STA_NUM		3
103#define MWIFIEX_MAX_UAP_NUM		3
104#define MWIFIEX_MAX_P2P_NUM		3
105
106#define MWIFIEX_A_BAND_START_FREQ	5000
107
108/* SDIO Aggr data packet special info */
109#define SDIO_MAX_AGGR_BUF_SIZE		(256 * 255)
110#define BLOCK_NUMBER_OFFSET		15
111#define SDIO_HEADER_OFFSET		28
112
113#define MWIFIEX_SIZE_4K 0x4000
114
115enum mwifiex_bss_type {
116	MWIFIEX_BSS_TYPE_STA = 0,
117	MWIFIEX_BSS_TYPE_UAP = 1,
118	MWIFIEX_BSS_TYPE_P2P = 2,
119	MWIFIEX_BSS_TYPE_ANY = 0xff,
120};
121
122enum mwifiex_bss_role {
123	MWIFIEX_BSS_ROLE_STA = 0,
124	MWIFIEX_BSS_ROLE_UAP = 1,
125	MWIFIEX_BSS_ROLE_ANY = 0xff,
126};
127
128enum mwifiex_tdls_status {
129	TDLS_NOT_SETUP = 0,
130	TDLS_SETUP_INPROGRESS,
131	TDLS_SETUP_COMPLETE,
132	TDLS_SETUP_FAILURE,
133	TDLS_LINK_TEARDOWN,
134	TDLS_CHAN_SWITCHING,
135	TDLS_IN_BASE_CHAN,
136	TDLS_IN_OFF_CHAN,
137};
138
139enum mwifiex_tdls_error_code {
140	TDLS_ERR_NO_ERROR = 0,
141	TDLS_ERR_INTERNAL_ERROR,
142	TDLS_ERR_MAX_LINKS_EST,
143	TDLS_ERR_LINK_EXISTS,
144	TDLS_ERR_LINK_NONEXISTENT,
145	TDLS_ERR_PEER_STA_UNREACHABLE = 25,
146};
147
148#define BSS_ROLE_BIT_MASK    BIT(0)
149
150#define GET_BSS_ROLE(priv)   ((priv)->bss_role & BSS_ROLE_BIT_MASK)
151
152enum mwifiex_data_frame_type {
153	MWIFIEX_DATA_FRAME_TYPE_ETH_II = 0,
154	MWIFIEX_DATA_FRAME_TYPE_802_11,
155};
156
157struct mwifiex_fw_image {
158	u8 *helper_buf;
159	u32 helper_len;
160	u8 *fw_buf;
161	u32 fw_len;
162};
163
164struct mwifiex_802_11_ssid {
165	u32 ssid_len;
166	u8 ssid[IEEE80211_MAX_SSID_LEN];
167};
168
169struct mwifiex_wait_queue {
170	wait_queue_head_t wait;
171	int status;
172};
173
174struct mwifiex_rxinfo {
175	struct sk_buff *parent;
176	u8 bss_num;
177	u8 bss_type;
178	u8 use_count;
179	u8 buf_type;
180};
181
182struct mwifiex_txinfo {
183	u8 flags;
184	u8 bss_num;
185	u8 bss_type;
186	u8 aggr_num;
187	u32 pkt_len;
188	u8 ack_frame_id;
189	u64 cookie;
190};
191
192enum mwifiex_wmm_ac_e {
193	WMM_AC_BK,
194	WMM_AC_BE,
195	WMM_AC_VI,
196	WMM_AC_VO
197} __packed;
198
199struct ieee_types_wmm_ac_parameters {
200	u8 aci_aifsn_bitmap;
201	u8 ecw_bitmap;
202	__le16 tx_op_limit;
203} __packed;
204
205struct mwifiex_types_wmm_info {
206	u8 oui[4];
207	u8 subtype;
208	u8 version;
209	u8 qos_info;
210	u8 reserved;
211	struct ieee_types_wmm_ac_parameters ac_params[IEEE80211_NUM_ACS];
212} __packed;
213
214struct mwifiex_arp_eth_header {
215	struct arphdr hdr;
216	u8 ar_sha[ETH_ALEN];
217	u8 ar_sip[4];
218	u8 ar_tha[ETH_ALEN];
219	u8 ar_tip[4];
220} __packed;
221
222struct mwifiex_chan_stats {
223	u8 chan_num;
224	u8 bandcfg;
225	u8 flags;
226	s8 noise;
227	u16 total_bss;
228	u16 cca_scan_dur;
229	u16 cca_busy_dur;
230} __packed;
231
232#define MWIFIEX_HIST_MAX_SAMPLES	1048576
233#define MWIFIEX_MAX_RX_RATES		     44
234#define MWIFIEX_MAX_AC_RX_RATES		     74
235#define MWIFIEX_MAX_SNR			    256
236#define MWIFIEX_MAX_NOISE_FLR		    256
237#define MWIFIEX_MAX_SIG_STRENGTH	    256
238
239struct mwifiex_histogram_data {
240	atomic_t rx_rate[MWIFIEX_MAX_AC_RX_RATES];
241	atomic_t snr[MWIFIEX_MAX_SNR];
242	atomic_t noise_flr[MWIFIEX_MAX_NOISE_FLR];
243	atomic_t sig_str[MWIFIEX_MAX_SIG_STRENGTH];
244	atomic_t num_samples;
245};
246
247struct mwifiex_iface_comb {
248	u8 sta_intf;
249	u8 uap_intf;
250	u8 p2p_intf;
251};
252
253struct mwifiex_radar_params {
254	struct cfg80211_chan_def *chandef;
255	u32 cac_time_ms;
256} __packed;
257
258struct mwifiex_11h_intf_state {
259	bool is_11h_enabled;
260	bool is_11h_active;
261} __packed;
262
263#define MWIFIEX_FW_DUMP_IDX		0xff
264#define MWIFIEX_FW_DUMP_MAX_MEMSIZE     0x160000
265#define MWIFIEX_DRV_INFO_IDX		20
266#define FW_DUMP_MAX_NAME_LEN		8
267#define FW_DUMP_HOST_READY      0xEE
268#define FW_DUMP_DONE			0xFF
269#define FW_DUMP_READ_DONE		0xFE
270
271struct memory_type_mapping {
272	u8 mem_name[FW_DUMP_MAX_NAME_LEN];
273	u8 *mem_ptr;
274	u32 mem_size;
275	u8 done_flag;
276};
277
278enum rdwr_status {
279	RDWR_STATUS_SUCCESS = 0,
280	RDWR_STATUS_FAILURE = 1,
281	RDWR_STATUS_DONE = 2
282};
283
284enum mwifiex_chan_width {
285	CHAN_BW_20MHZ = 0,
286	CHAN_BW_10MHZ,
287	CHAN_BW_40MHZ,
288	CHAN_BW_80MHZ,
289	CHAN_BW_8080MHZ,
290	CHAN_BW_160MHZ,
291	CHAN_BW_5MHZ,
292};
293
294enum mwifiex_chan_offset {
295	SEC_CHAN_NONE = 0,
296	SEC_CHAN_ABOVE = 1,
297	SEC_CHAN_5MHZ = 2,
298	SEC_CHAN_BELOW = 3
299};
300
301#endif /* !_MWIFIEX_DECL_H_ */
302