1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
4 */
5#include <linux/types.h>
6#include <linux/slab.h>
7#include <linux/export.h>
8
9#include "iwl-drv.h"
10#include "iwl-debug.h"
11#include "iwl-eeprom-read.h"
12#include "iwl-io.h"
13#include "iwl-prph.h"
14#include "iwl-csr.h"
15
16/*
17 * EEPROM access time values:
18 *
19 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
20 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
21 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
22 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
23 */
24#define IWL_EEPROM_ACCESS_TIMEOUT	5000 /* uSec */
25
26/*
27 * The device's EEPROM semaphore prevents conflicts between driver and uCode
28 * when accessing the EEPROM; each access is a series of pulses to/from the
29 * EEPROM chip, not a single event, so even reads could conflict if they
30 * weren't arbitrated by the semaphore.
31 */
32#define IWL_EEPROM_SEM_TIMEOUT		10   /* microseconds */
33#define IWL_EEPROM_SEM_RETRY_LIMIT	1000 /* number of attempts (not time) */
34
35
36static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
37{
38	u16 count;
39	int ret;
40
41	for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) {
42		/* Request semaphore */
43		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
44			    CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
45
46		/* See if we got it */
47		ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
48				CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
49				CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
50				IWL_EEPROM_SEM_TIMEOUT);
51		if (ret >= 0) {
52			IWL_DEBUG_EEPROM(trans->dev,
53					 "Acquired semaphore after %d tries.\n",
54					 count+1);
55			return ret;
56		}
57	}
58
59	return ret;
60}
61
62static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
63{
64	iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
65		      CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
66}
67
68static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp)
69{
70	u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
71
72	IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp);
73
74	switch (gp) {
75	case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
76		if (!nvm_is_otp) {
77			IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
78				gp);
79			return -ENOENT;
80		}
81		return 0;
82	case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
83	case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
84		if (nvm_is_otp) {
85			IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
86			return -ENOENT;
87		}
88		return 0;
89	case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
90	default:
91		IWL_ERR(trans,
92			"bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n",
93			nvm_is_otp ? "OTP" : "EEPROM", gp);
94		return -ENOENT;
95	}
96}
97
98/******************************************************************************
99 *
100 * OTP related functions
101 *
102******************************************************************************/
103
104static void iwl_set_otp_access_absolute(struct iwl_trans *trans)
105{
106	iwl_read32(trans, CSR_OTP_GP_REG);
107
108	iwl_clear_bit(trans, CSR_OTP_GP_REG,
109		      CSR_OTP_GP_REG_OTP_ACCESS_MODE);
110}
111
112static int iwl_nvm_is_otp(struct iwl_trans *trans)
113{
114	u32 otpgp;
115
116	/* OTP only valid for CP/PP and after */
117	switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) {
118	case CSR_HW_REV_TYPE_NONE:
119		IWL_ERR(trans, "Unknown hardware type\n");
120		return -EIO;
121	case CSR_HW_REV_TYPE_5300:
122	case CSR_HW_REV_TYPE_5350:
123	case CSR_HW_REV_TYPE_5100:
124	case CSR_HW_REV_TYPE_5150:
125		return 0;
126	default:
127		otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
128		if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
129			return 1;
130		return 0;
131	}
132}
133
134static int iwl_init_otp_access(struct iwl_trans *trans)
135{
136	int ret;
137
138	ret = iwl_finish_nic_init(trans);
139	if (ret)
140		return ret;
141
142	iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
143			  APMG_PS_CTRL_VAL_RESET_REQ);
144	udelay(5);
145	iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
146			    APMG_PS_CTRL_VAL_RESET_REQ);
147
148	/*
149	 * CSR auto clock gate disable bit -
150	 * this is only applicable for HW with OTP shadow RAM
151	 */
152	if (trans->trans_cfg->base_params->shadow_ram_support)
153		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
154			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
155
156	return 0;
157}
158
159static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
160			     __le16 *eeprom_data)
161{
162	int ret = 0;
163	u32 r;
164	u32 otpgp;
165
166	iwl_write32(trans, CSR_EEPROM_REG,
167		    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
168	ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
169				 CSR_EEPROM_REG_READ_VALID_MSK,
170				 CSR_EEPROM_REG_READ_VALID_MSK,
171				 IWL_EEPROM_ACCESS_TIMEOUT);
172	if (ret < 0) {
173		IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
174		return ret;
175	}
176	r = iwl_read32(trans, CSR_EEPROM_REG);
177	/* check for ECC errors: */
178	otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
179	if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
180		/* stop in this case */
181		/* set the uncorrectable OTP ECC bit for acknowledgment */
182		iwl_set_bit(trans, CSR_OTP_GP_REG,
183			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
184		IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
185		return -EINVAL;
186	}
187	if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
188		/* continue in this case */
189		/* set the correctable OTP ECC bit for acknowledgment */
190		iwl_set_bit(trans, CSR_OTP_GP_REG,
191			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
192		IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
193	}
194	*eeprom_data = cpu_to_le16(r >> 16);
195	return 0;
196}
197
198/*
199 * iwl_is_otp_empty: check for empty OTP
200 */
201static bool iwl_is_otp_empty(struct iwl_trans *trans)
202{
203	u16 next_link_addr = 0;
204	__le16 link_value;
205	bool is_empty = false;
206
207	/* locate the beginning of OTP link list */
208	if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
209		if (!link_value) {
210			IWL_ERR(trans, "OTP is empty\n");
211			is_empty = true;
212		}
213	} else {
214		IWL_ERR(trans, "Unable to read first block of OTP list.\n");
215		is_empty = true;
216	}
217
218	return is_empty;
219}
220
221
222/*
223 * iwl_find_otp_image: find EEPROM image in OTP
224 *   finding the OTP block that contains the EEPROM image.
225 *   the last valid block on the link list (the block _before_ the last block)
226 *   is the block we should read and used to configure the device.
227 *   If all the available OTP blocks are full, the last block will be the block
228 *   we should read and used to configure the device.
229 *   only perform this operation if shadow RAM is disabled
230 */
231static int iwl_find_otp_image(struct iwl_trans *trans,
232					u16 *validblockaddr)
233{
234	u16 next_link_addr = 0, valid_addr;
235	__le16 link_value = 0;
236	int usedblocks = 0;
237
238	/* set addressing mode to absolute to traverse the link list */
239	iwl_set_otp_access_absolute(trans);
240
241	/* checking for empty OTP or error */
242	if (iwl_is_otp_empty(trans))
243		return -EINVAL;
244
245	/*
246	 * start traverse link list
247	 * until reach the max number of OTP blocks
248	 * different devices have different number of OTP blocks
249	 */
250	do {
251		/* save current valid block address
252		 * check for more block on the link list
253		 */
254		valid_addr = next_link_addr;
255		next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
256		IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n",
257				 usedblocks, next_link_addr);
258		if (iwl_read_otp_word(trans, next_link_addr, &link_value))
259			return -EINVAL;
260		if (!link_value) {
261			/*
262			 * reach the end of link list, return success and
263			 * set address point to the starting address
264			 * of the image
265			 */
266			*validblockaddr = valid_addr;
267			/* skip first 2 bytes (link list pointer) */
268			*validblockaddr += 2;
269			return 0;
270		}
271		/* more in the link list, continue */
272		usedblocks++;
273	} while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
274
275	/* OTP has no valid blocks */
276	IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
277	return -EINVAL;
278}
279
280/*
281 * iwl_read_eeprom - read EEPROM contents
282 *
283 * Load the EEPROM contents from adapter and return it
284 * and its size.
285 *
286 * NOTE:  This routine uses the non-debug IO access functions.
287 */
288int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
289{
290	__le16 *e;
291	u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
292	int sz;
293	int ret;
294	u16 addr;
295	u16 validblockaddr = 0;
296	u16 cache_addr = 0;
297	int nvm_is_otp;
298
299	if (!eeprom || !eeprom_size)
300		return -EINVAL;
301
302	nvm_is_otp = iwl_nvm_is_otp(trans);
303	if (nvm_is_otp < 0)
304		return nvm_is_otp;
305
306	sz = trans->trans_cfg->base_params->eeprom_size;
307	IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
308
309	e = kmalloc(sz, GFP_KERNEL);
310	if (!e)
311		return -ENOMEM;
312
313	ret = iwl_eeprom_verify_signature(trans, nvm_is_otp);
314	if (ret < 0) {
315		IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
316		goto err_free;
317	}
318
319	/* Make sure driver (instead of uCode) is allowed to read EEPROM */
320	ret = iwl_eeprom_acquire_semaphore(trans);
321	if (ret < 0) {
322		IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
323		goto err_free;
324	}
325
326	if (nvm_is_otp) {
327		ret = iwl_init_otp_access(trans);
328		if (ret) {
329			IWL_ERR(trans, "Failed to initialize OTP access.\n");
330			goto err_unlock;
331		}
332
333		iwl_write32(trans, CSR_EEPROM_GP,
334			    iwl_read32(trans, CSR_EEPROM_GP) &
335			    ~CSR_EEPROM_GP_IF_OWNER_MSK);
336
337		iwl_set_bit(trans, CSR_OTP_GP_REG,
338			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
339			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
340		/* traversing the linked list if no shadow ram supported */
341		if (!trans->trans_cfg->base_params->shadow_ram_support) {
342			ret = iwl_find_otp_image(trans, &validblockaddr);
343			if (ret)
344				goto err_unlock;
345		}
346		for (addr = validblockaddr; addr < validblockaddr + sz;
347		     addr += sizeof(u16)) {
348			__le16 eeprom_data;
349
350			ret = iwl_read_otp_word(trans, addr, &eeprom_data);
351			if (ret)
352				goto err_unlock;
353			e[cache_addr / 2] = eeprom_data;
354			cache_addr += sizeof(u16);
355		}
356	} else {
357		/* eeprom is an array of 16bit values */
358		for (addr = 0; addr < sz; addr += sizeof(u16)) {
359			u32 r;
360
361			iwl_write32(trans, CSR_EEPROM_REG,
362				    CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
363
364			ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
365					   CSR_EEPROM_REG_READ_VALID_MSK,
366					   CSR_EEPROM_REG_READ_VALID_MSK,
367					   IWL_EEPROM_ACCESS_TIMEOUT);
368			if (ret < 0) {
369				IWL_ERR(trans,
370					"Time out reading EEPROM[%d]\n", addr);
371				goto err_unlock;
372			}
373			r = iwl_read32(trans, CSR_EEPROM_REG);
374			e[addr / 2] = cpu_to_le16(r >> 16);
375		}
376	}
377
378	IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n",
379			 nvm_is_otp ? "OTP" : "EEPROM");
380
381	iwl_eeprom_release_semaphore(trans);
382
383	*eeprom_size = sz;
384	*eeprom = (u8 *)e;
385	return 0;
386
387 err_unlock:
388	iwl_eeprom_release_semaphore(trans);
389 err_free:
390	kfree(e);
391
392	return ret;
393}
394IWL_EXPORT_SYMBOL(iwl_read_eeprom);
395