1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (c) 2010 Broadcom Corporation 4 */ 5 6#ifndef BRCMFMAC_SDIO_H 7#define BRCMFMAC_SDIO_H 8 9#include <linux/skbuff.h> 10#include <linux/firmware.h> 11#include "firmware.h" 12 13#define SDIOD_FBR_SIZE 0x100 14 15/* io_en */ 16#define SDIO_FUNC_ENABLE_1 0x02 17#define SDIO_FUNC_ENABLE_2 0x04 18 19/* io_rdys */ 20#define SDIO_FUNC_READY_1 0x02 21#define SDIO_FUNC_READY_2 0x04 22 23/* intr_status */ 24#define INTR_STATUS_FUNC1 0x2 25#define INTR_STATUS_FUNC2 0x4 26 27/* mask of register map */ 28#define REG_F0_REG_MASK 0x7FF 29#define REG_F1_MISC_MASK 0x1FFFF 30 31/* function 0 vendor specific CCCR registers */ 32 33#define SDIO_CCCR_BRCM_CARDCAP 0xf0 34#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT BIT(1) 35#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT BIT(2) 36#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC BIT(3) 37 38/* Interrupt enable bits for each function */ 39#define SDIO_CCCR_IEN_FUNC0 BIT(0) 40#define SDIO_CCCR_IEN_FUNC1 BIT(1) 41#define SDIO_CCCR_IEN_FUNC2 BIT(2) 42 43#define SDIO_CCCR_BRCM_CARDCTRL 0xf1 44#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET BIT(1) 45 46#define SDIO_CCCR_BRCM_SEPINT 0xf2 47#define SDIO_CCCR_BRCM_SEPINT_MASK BIT(0) 48#define SDIO_CCCR_BRCM_SEPINT_OE BIT(1) 49#define SDIO_CCCR_BRCM_SEPINT_ACT_HI BIT(2) 50 51/* function 1 miscellaneous registers */ 52 53/* sprom command and status */ 54#define SBSDIO_SPROM_CS 0x10000 55/* sprom info register */ 56#define SBSDIO_SPROM_INFO 0x10001 57/* sprom indirect access data byte 0 */ 58#define SBSDIO_SPROM_DATA_LOW 0x10002 59/* sprom indirect access data byte 1 */ 60#define SBSDIO_SPROM_DATA_HIGH 0x10003 61/* sprom indirect access addr byte 0 */ 62#define SBSDIO_SPROM_ADDR_LOW 0x10004 63/* gpio select */ 64#define SBSDIO_GPIO_SELECT 0x10005 65/* gpio output */ 66#define SBSDIO_GPIO_OUT 0x10006 67/* gpio enable */ 68#define SBSDIO_GPIO_EN 0x10007 69/* rev < 7, watermark for sdio device TX path */ 70#define SBSDIO_WATERMARK 0x10008 71/* control busy signal generation */ 72#define SBSDIO_DEVICE_CTL 0x10009 73 74/* SB Address Window Low (b15) */ 75#define SBSDIO_FUNC1_SBADDRLOW 0x1000A 76/* SB Address Window Mid (b23:b16) */ 77#define SBSDIO_FUNC1_SBADDRMID 0x1000B 78/* SB Address Window High (b31:b24) */ 79#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C 80/* Frame Control (frame term/abort) */ 81#define SBSDIO_FUNC1_FRAMECTRL 0x1000D 82/* ChipClockCSR (ALP/HT ctl/status) */ 83#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E 84/* SdioPullUp (on cmd, d0-d2) */ 85#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F 86/* Write Frame Byte Count Low */ 87#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 88/* Write Frame Byte Count High */ 89#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A 90/* Read Frame Byte Count Low */ 91#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B 92/* Read Frame Byte Count High */ 93#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C 94/* MesBusyCtl (rev 11) */ 95#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D 96/* Watermark for sdio device RX path */ 97#define SBSDIO_MESBUSY_RXFIFO_WM_MASK 0x7F 98#define SBSDIO_MESBUSY_RXFIFO_WM_SHIFT 0 99/* Enable busy capability for MES access */ 100#define SBSDIO_MESBUSYCTRL_ENAB 0x80 101#define SBSDIO_MESBUSYCTRL_ENAB_SHIFT 7 102 103/* Sdio Core Rev 12 */ 104#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E 105#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 106#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 107#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 108#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 109#define SBSDIO_FUNC1_SLEEPCSR 0x1001F 110#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 111#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 112#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 113#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 114#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 115 116#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 117#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */ 118 119/* function 1 OCP space */ 120 121/* sb offset addr is <= 15 bits, 32k */ 122#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF 123#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 124/* with b15, maps to 32-bit SB access */ 125#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 126 127/* Address bits from SBADDR regs */ 128#define SBSDIO_SBWINDOW_MASK 0xffff8000 129 130#define SDIOH_READ 0 /* Read request */ 131#define SDIOH_WRITE 1 /* Write request */ 132 133#define SDIOH_DATA_FIX 0 /* Fixed addressing */ 134#define SDIOH_DATA_INC 1 /* Incremental addressing */ 135 136/* internal return code */ 137#define SUCCESS 0 138#define ERROR 1 139 140/* Packet alignment for most efficient SDIO (can change based on platform) */ 141#define BRCMF_SDALIGN (1 << 6) 142 143/* watchdog polling interval */ 144#define BRCMF_WD_POLL msecs_to_jiffies(10) 145 146/** 147 * enum brcmf_sdiod_state - the state of the bus. 148 * 149 * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC. 150 * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled. 151 * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible. 152 */ 153enum brcmf_sdiod_state { 154 BRCMF_SDIOD_DOWN, 155 BRCMF_SDIOD_DATA, 156 BRCMF_SDIOD_NOMEDIUM 157}; 158 159struct brcmf_sdreg { 160 int func; 161 int offset; 162 int value; 163}; 164 165struct brcmf_sdio; 166struct brcmf_sdiod_freezer; 167 168struct brcmf_sdio_dev { 169 struct sdio_func *func1; 170 struct sdio_func *func2; 171 u32 sbwad; /* Save backplane window address */ 172 struct brcmf_core *cc_core; /* chipcommon core info struct */ 173 struct brcmf_sdio *bus; 174 struct device *dev; 175 struct brcmf_bus *bus_if; 176 struct brcmf_mp_device *settings; 177 bool oob_irq_requested; 178 bool sd_irq_requested; 179 bool irq_en; /* irq enable flags */ 180 spinlock_t irq_en_lock; 181 bool sg_support; 182 uint max_request_size; 183 ushort max_segment_count; 184 uint max_segment_size; 185 uint txglomsz; 186 struct sg_table sgtable; 187 char fw_name[BRCMF_FW_NAME_LEN]; 188 char nvram_name[BRCMF_FW_NAME_LEN]; 189 char clm_name[BRCMF_FW_NAME_LEN]; 190 bool wowl_enabled; 191 bool func1_power_manageable; 192 bool func2_power_manageable; 193 enum brcmf_sdiod_state state; 194 struct brcmf_sdiod_freezer *freezer; 195 const struct firmware *clm_fw; 196}; 197 198/* sdio core registers */ 199struct sdpcmd_regs { 200 u32 corecontrol; /* 0x00, rev8 */ 201 u32 corestatus; /* rev8 */ 202 u32 PAD[1]; 203 u32 biststatus; /* rev8 */ 204 205 /* PCMCIA access */ 206 u16 pcmciamesportaladdr; /* 0x010, rev8 */ 207 u16 PAD[1]; 208 u16 pcmciamesportalmask; /* rev8 */ 209 u16 PAD[1]; 210 u16 pcmciawrframebc; /* rev8 */ 211 u16 PAD[1]; 212 u16 pcmciaunderflowtimer; /* rev8 */ 213 u16 PAD[1]; 214 215 /* interrupt */ 216 u32 intstatus; /* 0x020, rev8 */ 217 u32 hostintmask; /* rev8 */ 218 u32 intmask; /* rev8 */ 219 u32 sbintstatus; /* rev8 */ 220 u32 sbintmask; /* rev8 */ 221 u32 funcintmask; /* rev4 */ 222 u32 PAD[2]; 223 u32 tosbmailbox; /* 0x040, rev8 */ 224 u32 tohostmailbox; /* rev8 */ 225 u32 tosbmailboxdata; /* rev8 */ 226 u32 tohostmailboxdata; /* rev8 */ 227 228 /* synchronized access to registers in SDIO clock domain */ 229 u32 sdioaccess; /* 0x050, rev8 */ 230 u32 PAD[3]; 231 232 /* PCMCIA frame control */ 233 u8 pcmciaframectrl; /* 0x060, rev8 */ 234 u8 PAD[3]; 235 u8 pcmciawatermark; /* rev8 */ 236 u8 PAD[155]; 237 238 /* interrupt batching control */ 239 u32 intrcvlazy; /* 0x100, rev8 */ 240 u32 PAD[3]; 241 242 /* counters */ 243 u32 cmd52rd; /* 0x110, rev8 */ 244 u32 cmd52wr; /* rev8 */ 245 u32 cmd53rd; /* rev8 */ 246 u32 cmd53wr; /* rev8 */ 247 u32 abort; /* rev8 */ 248 u32 datacrcerror; /* rev8 */ 249 u32 rdoutofsync; /* rev8 */ 250 u32 wroutofsync; /* rev8 */ 251 u32 writebusy; /* rev8 */ 252 u32 readwait; /* rev8 */ 253 u32 readterm; /* rev8 */ 254 u32 writeterm; /* rev8 */ 255 u32 PAD[40]; 256 u32 clockctlstatus; /* rev8 */ 257 u32 PAD[7]; 258 259 u32 PAD[128]; /* DMA engines */ 260 261 /* SDIO/PCMCIA CIS region */ 262 char cis[512]; /* 0x400-0x5ff, rev6 */ 263 264 /* PCMCIA function control registers */ 265 char pcmciafcr[256]; /* 0x600-6ff, rev6 */ 266 u16 PAD[55]; 267 268 /* PCMCIA backplane access */ 269 u16 backplanecsr; /* 0x76E, rev6 */ 270 u16 backplaneaddr0; /* rev6 */ 271 u16 backplaneaddr1; /* rev6 */ 272 u16 backplaneaddr2; /* rev6 */ 273 u16 backplaneaddr3; /* rev6 */ 274 u16 backplanedata0; /* rev6 */ 275 u16 backplanedata1; /* rev6 */ 276 u16 backplanedata2; /* rev6 */ 277 u16 backplanedata3; /* rev6 */ 278 u16 PAD[31]; 279 280 /* sprom "size" & "blank" info */ 281 u16 spromstatus; /* 0x7BE, rev2 */ 282 u32 PAD[464]; 283 284 u16 PAD[0x80]; 285}; 286 287/* Register/deregister interrupt handler. */ 288int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev); 289void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev); 290 291/* SDIO device register access interface */ 292/* Accessors for SDIO Function 0 */ 293#define brcmf_sdiod_func0_rb(sdiodev, addr, r) \ 294 sdio_f0_readb((sdiodev)->func1, (addr), (r)) 295 296#define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \ 297 sdio_f0_writeb((sdiodev)->func1, (v), (addr), (ret)) 298 299/* Accessors for SDIO Function 1 */ 300#define brcmf_sdiod_readb(sdiodev, addr, r) \ 301 sdio_readb((sdiodev)->func1, (addr), (r)) 302 303#define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \ 304 sdio_writeb((sdiodev)->func1, (v), (addr), (ret)) 305 306u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret); 307void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data, 308 int *ret); 309 310/* Buffer transfer to/from device (client) core via cmd53. 311 * fn: function number 312 * flags: backplane width, address increment, sync/async 313 * buf: pointer to memory data buffer 314 * nbytes: number of bytes to transfer to/from buf 315 * pkt: pointer to packet associated with buf (if any) 316 * complete: callback function for command completion (async only) 317 * handle: handle for completion callback (first arg in callback) 318 * Returns 0 or error code. 319 * NOTE: Async operation is not currently supported. 320 */ 321int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev, 322 struct sk_buff_head *pktq); 323int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 324 325int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt); 326int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); 327int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev, 328 struct sk_buff_head *pktq, uint totlen); 329 330/* Flags bits */ 331 332/* Four-byte target (backplane) width (vs. two-byte) */ 333#define SDIO_REQ_4BYTE 0x1 334/* Fixed address (FIFO) (vs. incrementing address) */ 335#define SDIO_REQ_FIXED 0x2 336 337/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only). 338 * rw: read or write (0/1) 339 * addr: direct SDIO address 340 * buf: pointer to memory data buffer 341 * nbytes: number of bytes to transfer to/from buf 342 * Returns 0 or error code. 343 */ 344int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address, 345 u8 *data, uint size); 346 347/* Issue an abort to the specified function */ 348int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, struct sdio_func *func); 349 350void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev); 351void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev, 352 enum brcmf_sdiod_state state); 353bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev); 354void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev); 355void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev); 356void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev); 357 358int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev); 359int brcmf_sdiod_remove(struct brcmf_sdio_dev *sdiodev); 360 361struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev); 362void brcmf_sdio_remove(struct brcmf_sdio *bus); 363void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr); 364 365void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active); 366void brcmf_sdio_wowl_config(struct device *dev, bool enabled); 367int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep); 368void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus); 369 370#endif /* BRCMFMAC_SDIO_H */ 371