1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef LINUX_B43_PHY_G_H_
3#define LINUX_B43_PHY_G_H_
4
5/* OFDM PHY registers are defined in the A-PHY header. */
6#include "phy_a.h"
7
8/* CCK (B) PHY Registers */
9#define B43_PHY_VERSION_CCK		B43_PHY_CCK(0x00)	/* Versioning register for B-PHY */
10#define B43_PHY_CCKBBANDCFG		B43_PHY_CCK(0x01)	/* Contains antenna 0/1 control bit */
11#define B43_PHY_PGACTL			B43_PHY_CCK(0x15)	/* PGA control */
12#define  B43_PHY_PGACTL_LPF		0x1000	/* Low pass filter (?) */
13#define  B43_PHY_PGACTL_LOWBANDW	0x0040	/* Low bandwidth flag */
14#define  B43_PHY_PGACTL_UNKNOWN		0xEFA0
15#define B43_PHY_FBCTL1			B43_PHY_CCK(0x18)	/* Frequency bandwidth control 1 */
16#define B43_PHY_ITSSI			B43_PHY_CCK(0x29)	/* Idle TSSI */
17#define B43_PHY_LO_LEAKAGE		B43_PHY_CCK(0x2D)	/* Measured LO leakage */
18#define B43_PHY_ENERGY			B43_PHY_CCK(0x33)	/* Energy */
19#define B43_PHY_SYNCCTL			B43_PHY_CCK(0x35)
20#define B43_PHY_FBCTL2			B43_PHY_CCK(0x38)	/* Frequency bandwidth control 2 */
21#define B43_PHY_DACCTL			B43_PHY_CCK(0x60)	/* DAC control */
22#define B43_PHY_RCCALOVER		B43_PHY_CCK(0x78)	/* RC calibration override */
23
24/* Extended G-PHY Registers */
25#define B43_PHY_CLASSCTL		B43_PHY_EXTG(0x02)	/* Classify control */
26#define B43_PHY_GTABCTL			B43_PHY_EXTG(0x03)	/* G-PHY table control (see below) */
27#define  B43_PHY_GTABOFF		0x03FF	/* G-PHY table offset (see below) */
28#define  B43_PHY_GTABNR			0xFC00	/* G-PHY table number (see below) */
29#define  B43_PHY_GTABNR_SHIFT		10
30#define B43_PHY_GTABDATA		B43_PHY_EXTG(0x04)	/* G-PHY table data */
31#define B43_PHY_LO_MASK			B43_PHY_EXTG(0x0F)	/* Local Oscillator control mask */
32#define B43_PHY_LO_CTL			B43_PHY_EXTG(0x10)	/* Local Oscillator control */
33#define B43_PHY_RFOVER			B43_PHY_EXTG(0x11)	/* RF override */
34#define B43_PHY_RFOVERVAL		B43_PHY_EXTG(0x12)	/* RF override value */
35#define  B43_PHY_RFOVERVAL_EXTLNA	0x8000
36#define  B43_PHY_RFOVERVAL_LNA		0x7000
37#define  B43_PHY_RFOVERVAL_LNA_SHIFT	12
38#define  B43_PHY_RFOVERVAL_PGA		0x0F00
39#define  B43_PHY_RFOVERVAL_PGA_SHIFT	8
40#define  B43_PHY_RFOVERVAL_UNK		0x0010	/* Unknown, always set. */
41#define  B43_PHY_RFOVERVAL_TRSWRX	0x00E0
42#define  B43_PHY_RFOVERVAL_BW		0x0003	/* Bandwidth flags */
43#define   B43_PHY_RFOVERVAL_BW_LPF	0x0001	/* Low Pass Filter */
44#define   B43_PHY_RFOVERVAL_BW_LBW	0x0002	/* Low Bandwidth (when set), high when unset */
45#define B43_PHY_ANALOGOVER		B43_PHY_EXTG(0x14)	/* Analog override */
46#define B43_PHY_ANALOGOVERVAL		B43_PHY_EXTG(0x15)	/* Analog override value */
47
48
49/*** G-PHY table numbers */
50#define B43_GTAB(number, offset)	(((number) << B43_PHY_GTABNR_SHIFT) | (offset))
51#define B43_GTAB_NRSSI			B43_GTAB(0x00, 0)
52#define B43_GTAB_TRFEMW			B43_GTAB(0x0C, 0x120)
53#define B43_GTAB_ORIGTR			B43_GTAB(0x2E, 0x298)
54
55u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);
56void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);
57
58
59/* Returns the boolean whether "TX Magnification" is enabled. */
60#define has_tx_magnification(phy) \
61	(((phy)->rev >= 2) &&			\
62	 ((phy)->radio_ver == 0x2050) &&	\
63	 ((phy)->radio_rev == 8))
64/* Card uses the loopback gain stuff */
65#define has_loopback_gain(phy) \
66	(((phy)->rev > 1) || ((phy)->gmode))
67
68/* Radio Attenuation (RF Attenuation) */
69struct b43_rfatt {
70	u8 att;			/* Attenuation value */
71	bool with_padmix;	/* Flag, PAD Mixer enabled. */
72};
73struct b43_rfatt_list {
74	/* Attenuation values list */
75	const struct b43_rfatt *list;
76	u8 len;
77	/* Minimum/Maximum attenuation values */
78	u8 min_val;
79	u8 max_val;
80};
81
82/* Returns true, if the values are the same. */
83static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
84				     const struct b43_rfatt *b)
85{
86	return ((a->att == b->att) &&
87		(a->with_padmix == b->with_padmix));
88}
89
90/* Baseband Attenuation */
91struct b43_bbatt {
92	u8 att;			/* Attenuation value */
93};
94struct b43_bbatt_list {
95	/* Attenuation values list */
96	const struct b43_bbatt *list;
97	u8 len;
98	/* Minimum/Maximum attenuation values */
99	u8 min_val;
100	u8 max_val;
101};
102
103/* Returns true, if the values are the same. */
104static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
105				     const struct b43_bbatt *b)
106{
107	return (a->att == b->att);
108}
109
110/* tx_control bits. */
111#define B43_TXCTL_PA3DB		0x40	/* PA Gain 3dB */
112#define B43_TXCTL_PA2DB		0x20	/* PA Gain 2dB */
113#define B43_TXCTL_TXMIX		0x10	/* TX Mixer Gain */
114
115struct b43_txpower_lo_control;
116
117struct b43_phy_g {
118	/* ACI (adjacent channel interference) flags. */
119	bool aci_enable;
120	bool aci_wlan_automatic;
121	bool aci_hw_rssi;
122
123	/* Radio switched on/off */
124	bool radio_on;
125	struct {
126		/* Values saved when turning the radio off.
127		 * They are needed when turning it on again. */
128		bool valid;
129		u16 rfover;
130		u16 rfoverval;
131	} radio_off_context;
132
133	u16 minlowsig[2];
134	u16 minlowsigpos[2];
135
136	/* Pointer to the table used to convert a
137	 * TSSI value to dBm-Q5.2 */
138	const s8 *tssi2dbm;
139	/* tssi2dbm is kmalloc()ed. Only used for free()ing. */
140	bool dyn_tssi_tbl;
141	/* Target idle TSSI */
142	int tgt_idle_tssi;
143	/* Current idle TSSI */
144	int cur_idle_tssi;
145	/* The current average TSSI. */
146	u8 average_tssi;
147	/* Current TX power level attenuation control values */
148	struct b43_bbatt bbatt;
149	struct b43_rfatt rfatt;
150	u8 tx_control;		/* B43_TXCTL_XXX */
151	/* The calculated attenuation deltas that are used later
152	 * when adjusting the actual power output. */
153	int bbatt_delta;
154	int rfatt_delta;
155
156	/* LocalOscillator control values. */
157	struct b43_txpower_lo_control *lo_control;
158	/* Values from b43_calc_loopback_gain() */
159	s16 max_lb_gain;	/* Maximum Loopback gain in hdB */
160	s16 trsw_rx_gain;	/* TRSW RX gain in hdB */
161	s16 lna_lod_gain;	/* LNA lod */
162	s16 lna_gain;		/* LNA */
163	s16 pga_gain;		/* PGA */
164
165	/* Current Interference Mitigation mode */
166	int interfmode;
167	/* Stack of saved values from the Interference Mitigation code.
168	 * Each value in the stack is laid out as follows:
169	 * bit 0-11:  offset
170	 * bit 12-15: register ID
171	 * bit 16-32: value
172	 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
173	 */
174#define B43_INTERFSTACK_SIZE	26
175	u32 interfstack[B43_INTERFSTACK_SIZE];	//FIXME: use a data structure
176
177	/* Saved values from the NRSSI Slope calculation */
178	s16 nrssi[2];
179	s32 nrssislope;
180	/* In memory nrssi lookup table. */
181	s8 nrssi_lt[64];
182
183	u16 lofcal;
184
185	u16 initval;		//FIXME rename?
186
187	/* The device does address auto increment for the OFDM tables.
188	 * We cache the previously used address here and omit the address
189	 * write on the next table access, if possible. */
190	u16 ofdmtab_addr; /* The address currently set in hardware. */
191	enum { /* The last data flow direction. */
192		B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
193		B43_OFDMTAB_DIRECTION_READ,
194		B43_OFDMTAB_DIRECTION_WRITE,
195	} ofdmtab_addr_direction;
196};
197
198void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
199				       u16 baseband_attenuation);
200void b43_gphy_channel_switch(struct b43_wldev *dev,
201			     unsigned int channel,
202			     bool synthetic_pu_workaround);
203u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
204				   s16 pab0, s16 pab1, s16 pab2);
205
206struct b43_phy_operations;
207extern const struct b43_phy_operations b43_phyops_g;
208
209#endif /* LINUX_B43_PHY_G_H_ */
210