1/* SPDX-License-Identifier: ISC */ 2/* 3 * Copyright (c) 2005-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#ifndef _RX_DESC_H_ 9#define _RX_DESC_H_ 10 11#include <linux/bitops.h> 12 13enum rx_attention_flags { 14 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0), 15 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1), 16 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2), 17 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3), 18 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4), 19 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5), 20 RX_ATTENTION_FLAGS_NON_QOS = BIT(6), 21 RX_ATTENTION_FLAGS_NULL_DATA = BIT(7), 22 RX_ATTENTION_FLAGS_MGMT_TYPE = BIT(8), 23 RX_ATTENTION_FLAGS_CTRL_TYPE = BIT(9), 24 RX_ATTENTION_FLAGS_MORE_DATA = BIT(10), 25 RX_ATTENTION_FLAGS_EOSP = BIT(11), 26 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = BIT(12), 27 RX_ATTENTION_FLAGS_FRAGMENT = BIT(13), 28 RX_ATTENTION_FLAGS_ORDER = BIT(14), 29 RX_ATTENTION_FLAGS_CLASSIFICATION = BIT(15), 30 RX_ATTENTION_FLAGS_OVERFLOW_ERR = BIT(16), 31 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = BIT(17), 32 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = BIT(18), 33 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = BIT(19), 34 RX_ATTENTION_FLAGS_SA_IDX_INVALID = BIT(20), 35 RX_ATTENTION_FLAGS_DA_IDX_INVALID = BIT(21), 36 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = BIT(22), 37 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = BIT(23), 38 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = BIT(24), 39 RX_ATTENTION_FLAGS_DIRECTED = BIT(25), 40 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = BIT(26), 41 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = BIT(27), 42 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = BIT(28), 43 RX_ATTENTION_FLAGS_DECRYPT_ERR = BIT(29), 44 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30), 45 RX_ATTENTION_FLAGS_MSDU_DONE = BIT(31), 46}; 47 48struct rx_attention { 49 __le32 flags; /* %RX_ATTENTION_FLAGS_ */ 50} __packed; 51 52/* 53 * first_mpdu 54 * Indicates the first MSDU of the PPDU. If both first_mpdu 55 * and last_mpdu are set in the MSDU then this is a not an 56 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 57 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 58 * 0. The PPDU start status will only be valid when this bit 59 * is set. 60 * 61 * last_mpdu 62 * Indicates the last MSDU of the last MPDU of the PPDU. The 63 * PPDU end status will only be valid when this bit is set. 64 * 65 * mcast_bcast 66 * Multicast / broadcast indicator. Only set when the MAC 67 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 68 * matches one of the 4 BSSID registers. Only set when 69 * first_msdu is set. 70 * 71 * peer_idx_invalid 72 * Indicates no matching entries within the max search 73 * count. Only set when first_msdu is set. 74 * 75 * peer_idx_timeout 76 * Indicates an unsuccessful search for the peer index due to 77 * timeout. Only set when first_msdu is set. 78 * 79 * power_mgmt 80 * Power management bit set in the 802.11 header. Only set 81 * when first_msdu is set. 82 * 83 * non_qos 84 * Set if packet is not a non-QoS data frame. Only set when 85 * first_msdu is set. 86 * 87 * null_data 88 * Set if frame type indicates either null data or QoS null 89 * data format. Only set when first_msdu is set. 90 * 91 * mgmt_type 92 * Set if packet is a management packet. Only set when 93 * first_msdu is set. 94 * 95 * ctrl_type 96 * Set if packet is a control packet. Only set when first_msdu 97 * is set. 98 * 99 * more_data 100 * Set if more bit in frame control is set. Only set when 101 * first_msdu is set. 102 * 103 * eosp 104 * Set if the EOSP (end of service period) bit in the QoS 105 * control field is set. Only set when first_msdu is set. 106 * 107 * u_apsd_trigger 108 * Set if packet is U-APSD trigger. Key table will have bits 109 * per TID to indicate U-APSD trigger. 110 * 111 * fragment 112 * Indicates that this is an 802.11 fragment frame. This is 113 * set when either the more_frag bit is set in the frame 114 * control or the fragment number is not zero. Only set when 115 * first_msdu is set. 116 * 117 * order 118 * Set if the order bit in the frame control is set. Only set 119 * when first_msdu is set. 120 * 121 * classification 122 * Indicates that this status has a corresponding MSDU that 123 * requires FW processing. The OLE will have classification 124 * ring mask registers which will indicate the ring(s) for 125 * packets and descriptors which need FW attention. 126 * 127 * overflow_err 128 * PCU Receive FIFO does not have enough space to store the 129 * full receive packet. Enough space is reserved in the 130 * receive FIFO for the status is written. This MPDU remaining 131 * packets in the PPDU will be filtered and no Ack response 132 * will be transmitted. 133 * 134 * msdu_length_err 135 * Indicates that the MSDU length from the 802.3 encapsulated 136 * length field extends beyond the MPDU boundary. 137 * 138 * tcp_udp_chksum_fail 139 * Indicates that the computed checksum (tcp_udp_chksum) did 140 * not match the checksum in the TCP/UDP header. 141 * 142 * ip_chksum_fail 143 * Indicates that the computed checksum did not match the 144 * checksum in the IP header. 145 * 146 * sa_idx_invalid 147 * Indicates no matching entry was found in the address search 148 * table for the source MAC address. 149 * 150 * da_idx_invalid 151 * Indicates no matching entry was found in the address search 152 * table for the destination MAC address. 153 * 154 * sa_idx_timeout 155 * Indicates an unsuccessful search for the source MAC address 156 * due to the expiring of the search timer. 157 * 158 * da_idx_timeout 159 * Indicates an unsuccessful search for the destination MAC 160 * address due to the expiring of the search timer. 161 * 162 * encrypt_required 163 * Indicates that this data type frame is not encrypted even if 164 * the policy for this MPDU requires encryption as indicated in 165 * the peer table key type. 166 * 167 * directed 168 * MPDU is a directed packet which means that the RA matched 169 * our STA addresses. In proxySTA it means that the TA matched 170 * an entry in our address search table with the corresponding 171 * 'no_ack' bit is the address search entry cleared. 172 * 173 * buffer_fragment 174 * Indicates that at least one of the rx buffers has been 175 * fragmented. If set the FW should look at the rx_frag_info 176 * descriptor described below. 177 * 178 * mpdu_length_err 179 * Indicates that the MPDU was pre-maturely terminated 180 * resulting in a truncated MPDU. Don't trust the MPDU length 181 * field. 182 * 183 * tkip_mic_err 184 * Indicates that the MPDU Michael integrity check failed 185 * 186 * decrypt_err 187 * Indicates that the MPDU decrypt integrity check failed 188 * 189 * fcs_err 190 * Indicates that the MPDU FCS check failed 191 * 192 * msdu_done 193 * If set indicates that the RX packet data, RX header data, RX 194 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 195 * start/end descriptors and RX Attention descriptor are all 196 * valid. This bit must be in the last octet of the 197 * descriptor. 198 */ 199 200struct rx_frag_info_common { 201 u8 ring0_more_count; 202 u8 ring1_more_count; 203 u8 ring2_more_count; 204 u8 ring3_more_count; 205} __packed; 206 207struct rx_frag_info_wcn3990 { 208 u8 ring4_more_count; 209 u8 ring5_more_count; 210 u8 ring6_more_count; 211 u8 ring7_more_count; 212} __packed; 213 214struct rx_frag_info { 215 struct rx_frag_info_common common; 216 union { 217 struct rx_frag_info_wcn3990 wcn3990; 218 } __packed; 219} __packed; 220 221struct rx_frag_info_v1 { 222 struct rx_frag_info_common common; 223} __packed; 224 225/* 226 * ring0_more_count 227 * Indicates the number of more buffers associated with RX DMA 228 * ring 0. Field is filled in by the RX_DMA. 229 * 230 * ring1_more_count 231 * Indicates the number of more buffers associated with RX DMA 232 * ring 1. Field is filled in by the RX_DMA. 233 * 234 * ring2_more_count 235 * Indicates the number of more buffers associated with RX DMA 236 * ring 2. Field is filled in by the RX_DMA. 237 * 238 * ring3_more_count 239 * Indicates the number of more buffers associated with RX DMA 240 * ring 3. Field is filled in by the RX_DMA. 241 */ 242 243enum htt_rx_mpdu_encrypt_type { 244 HTT_RX_MPDU_ENCRYPT_WEP40 = 0, 245 HTT_RX_MPDU_ENCRYPT_WEP104 = 1, 246 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2, 247 HTT_RX_MPDU_ENCRYPT_WEP128 = 3, 248 HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4, 249 HTT_RX_MPDU_ENCRYPT_WAPI = 5, 250 HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6, 251 HTT_RX_MPDU_ENCRYPT_NONE = 7, 252 HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2 = 8, 253 HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2 = 9, 254 HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2 = 10, 255}; 256 257#define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff 258#define RX_MPDU_START_INFO0_PEER_IDX_LSB 0 259#define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000 260#define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16 261#define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000 262#define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28 263#define RX_MPDU_START_INFO0_FROM_DS BIT(11) 264#define RX_MPDU_START_INFO0_TO_DS BIT(12) 265#define RX_MPDU_START_INFO0_ENCRYPTED BIT(13) 266#define RX_MPDU_START_INFO0_RETRY BIT(14) 267#define RX_MPDU_START_INFO0_TXBF_H_INFO BIT(15) 268 269#define RX_MPDU_START_INFO1_TID_MASK 0xf0000000 270#define RX_MPDU_START_INFO1_TID_LSB 28 271#define RX_MPDU_START_INFO1_DIRECTED BIT(16) 272 273struct rx_mpdu_start { 274 __le32 info0; 275 union { 276 struct { 277 __le32 pn31_0; 278 __le32 info1; /* %RX_MPDU_START_INFO1_ */ 279 } __packed; 280 struct { 281 u8 pn[6]; 282 } __packed; 283 } __packed; 284} __packed; 285 286/* 287 * peer_idx 288 * The index of the address search table which associated with 289 * the peer table entry corresponding to this MPDU. Only valid 290 * when first_msdu is set. 291 * 292 * fr_ds 293 * Set if the from DS bit is set in the frame control. Only 294 * valid when first_msdu is set. 295 * 296 * to_ds 297 * Set if the to DS bit is set in the frame control. Only 298 * valid when first_msdu is set. 299 * 300 * encrypted 301 * Protected bit from the frame control. Only valid when 302 * first_msdu is set. 303 * 304 * retry 305 * Retry bit from the frame control. Only valid when 306 * first_msdu is set. 307 * 308 * txbf_h_info 309 * The MPDU data will contain H information. Primarily used 310 * for debug. 311 * 312 * seq_num 313 * The sequence number from the 802.11 header. Only valid when 314 * first_msdu is set. 315 * 316 * encrypt_type 317 * Indicates type of decrypt cipher used (as defined in the 318 * peer table) 319 * 0: WEP40 320 * 1: WEP104 321 * 2: TKIP without MIC 322 * 3: WEP128 323 * 4: TKIP (WPA) 324 * 5: WAPI 325 * 6: AES-CCM (WPA2) 326 * 7: No cipher 327 * Only valid when first_msdu_is set 328 * 329 * pn_31_0 330 * Bits [31:0] of the PN number extracted from the IV field 331 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is 332 * valid. 333 * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 334 * WEPSeed[1], pn1}. Only pn[47:0] is valid. 335 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 336 * pn0}. Only pn[47:0] is valid. 337 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 338 * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 339 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and 340 * pn[47:0] are valid. 341 * Only valid when first_msdu is set. 342 * 343 * pn_47_32 344 * Bits [47:32] of the PN number. See description for 345 * pn_31_0. The remaining PN fields are in the rx_msdu_end 346 * descriptor 347 * 348 * pn 349 * Use this field to access the pn without worrying about 350 * byte-order and bitmasking/bitshifting. 351 * 352 * directed 353 * See definition in RX attention descriptor 354 * 355 * reserved_2 356 * Reserved: HW should fill with zero. FW should ignore. 357 * 358 * tid 359 * The TID field in the QoS control field 360 */ 361 362#define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff 363#define RX_MPDU_END_INFO0_RESERVED_0_LSB 0 364#define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000 365#define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16 366#define RX_MPDU_END_INFO0_OVERFLOW_ERR BIT(13) 367#define RX_MPDU_END_INFO0_LAST_MPDU BIT(14) 368#define RX_MPDU_END_INFO0_POST_DELIM_ERR BIT(15) 369#define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR BIT(28) 370#define RX_MPDU_END_INFO0_TKIP_MIC_ERR BIT(29) 371#define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30) 372#define RX_MPDU_END_INFO0_FCS_ERR BIT(31) 373 374struct rx_mpdu_end { 375 __le32 info0; 376} __packed; 377 378/* 379 * reserved_0 380 * Reserved 381 * 382 * overflow_err 383 * PCU Receive FIFO does not have enough space to store the 384 * full receive packet. Enough space is reserved in the 385 * receive FIFO for the status is written. This MPDU remaining 386 * packets in the PPDU will be filtered and no Ack response 387 * will be transmitted. 388 * 389 * last_mpdu 390 * Indicates that this is the last MPDU of a PPDU. 391 * 392 * post_delim_err 393 * Indicates that a delimiter FCS error occurred after this 394 * MPDU before the next MPDU. Only valid when last_msdu is 395 * set. 396 * 397 * post_delim_cnt 398 * Count of the delimiters after this MPDU. This requires the 399 * last MPDU to be held until all the EOF descriptors have been 400 * received. This may be inefficient in the future when 401 * ML-MIMO is used. Only valid when last_mpdu is set. 402 * 403 * mpdu_length_err 404 * See definition in RX attention descriptor 405 * 406 * tkip_mic_err 407 * See definition in RX attention descriptor 408 * 409 * decrypt_err 410 * See definition in RX attention descriptor 411 * 412 * fcs_err 413 * See definition in RX attention descriptor 414 */ 415 416#define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff 417#define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0 418#define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000 419#define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14 420#define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000 421#define RX_MSDU_START_INFO0_RING_MASK_LSB 20 422#define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000 423#define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24 424 425#define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff 426#define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0 427#define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300 428#define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8 429#define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000 430#define RX_MSDU_START_INFO1_SA_IDX_LSB 16 431#define RX_MSDU_START_INFO1_IPV4_PROTO BIT(10) 432#define RX_MSDU_START_INFO1_IPV6_PROTO BIT(11) 433#define RX_MSDU_START_INFO1_TCP_PROTO BIT(12) 434#define RX_MSDU_START_INFO1_UDP_PROTO BIT(13) 435#define RX_MSDU_START_INFO1_IP_FRAG BIT(14) 436#define RX_MSDU_START_INFO1_TCP_ONLY_ACK BIT(15) 437 438#define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff 439#define RX_MSDU_START_INFO2_DA_IDX_LSB 0 440#define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000 441#define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB 16 442#define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11) 443 444/* The decapped header (rx_hdr_status) contains the following: 445 * a) 802.11 header 446 * [padding to 4 bytes] 447 * b) HW crypto parameter 448 * - 0 bytes for no security 449 * - 4 bytes for WEP 450 * - 8 bytes for TKIP, AES 451 * [padding to 4 bytes] 452 * c) A-MSDU subframe header (14 bytes) if applicable 453 * d) LLC/SNAP (RFC1042, 8 bytes) 454 * 455 * In case of A-MSDU only first frame in sequence contains (a) and (b). 456 */ 457enum rx_msdu_decap_format { 458 RX_MSDU_DECAP_RAW = 0, 459 460 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in 461 * htt_rx_desc contains the original decapped 802.11 header. 462 */ 463 RX_MSDU_DECAP_NATIVE_WIFI = 1, 464 465 /* Payload contains an ethernet header (struct ethhdr). */ 466 RX_MSDU_DECAP_ETHERNET2_DIX = 2, 467 468 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes 469 * total), followed by an RFC1042 header (8 bytes). 470 */ 471 RX_MSDU_DECAP_8023_SNAP_LLC = 3 472}; 473 474struct rx_msdu_start_common { 475 __le32 info0; /* %RX_MSDU_START_INFO0_ */ 476 __le32 flow_id_crc; 477 __le32 info1; /* %RX_MSDU_START_INFO1_ */ 478} __packed; 479 480struct rx_msdu_start_qca99x0 { 481 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 482} __packed; 483 484struct rx_msdu_start_wcn3990 { 485 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 486 __le32 info3; /* %RX_MSDU_START_INFO3_ */ 487} __packed; 488 489struct rx_msdu_start { 490 struct rx_msdu_start_common common; 491 union { 492 struct rx_msdu_start_wcn3990 wcn3990; 493 } __packed; 494} __packed; 495 496struct rx_msdu_start_v1 { 497 struct rx_msdu_start_common common; 498 union { 499 struct rx_msdu_start_qca99x0 qca99x0; 500 } __packed; 501} __packed; 502 503/* 504 * msdu_length 505 * MSDU length in bytes after decapsulation. This field is 506 * still valid for MPDU frames without A-MSDU. It still 507 * represents MSDU length after decapsulation 508 * 509 * ip_offset 510 * Indicates the IP offset in bytes from the start of the 511 * packet after decapsulation. Only valid if ipv4_proto or 512 * ipv6_proto is set. 513 * 514 * ring_mask 515 * Indicates the destination RX rings for this MSDU. 516 * 517 * tcp_udp_offset 518 * Indicates the offset in bytes to the start of TCP or UDP 519 * header from the start of the IP header after decapsulation. 520 * Only valid if tcp_prot or udp_prot is set. The value 0 521 * indicates that the offset is longer than 127 bytes. 522 * 523 * reserved_0c 524 * Reserved: HW should fill with zero. FW should ignore. 525 * 526 * flow_id_crc 527 * The flow_id_crc runs CRC32 on the following information: 528 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0, 529 * protocol[7:0]}. 530 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0, 531 * next_header[7:0]} 532 * UDP case: sort_port[15:0], dest_port[15:0] 533 * TCP case: sort_port[15:0], dest_port[15:0], 534 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]}, 535 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit 536 * timestamp. 537 * 538 * msdu_number 539 * Indicates the MSDU number within a MPDU. This value is 540 * reset to zero at the start of each MPDU. If the number of 541 * MSDU exceeds 255 this number will wrap using modulo 256. 542 * 543 * decap_format 544 * Indicates the format after decapsulation: 545 * 0: RAW: No decapsulation 546 * 1: Native WiFi 547 * 2: Ethernet 2 (DIX) 548 * 3: 802.3 (SNAP/LLC) 549 * 550 * ipv4_proto 551 * Set if L2 layer indicates IPv4 protocol. 552 * 553 * ipv6_proto 554 * Set if L2 layer indicates IPv6 protocol. 555 * 556 * tcp_proto 557 * Set if the ipv4_proto or ipv6_proto are set and the IP 558 * protocol indicates TCP. 559 * 560 * udp_proto 561 * Set if the ipv4_proto or ipv6_proto are set and the IP 562 * protocol indicates UDP. 563 * 564 * ip_frag 565 * Indicates that either the IP More frag bit is set or IP frag 566 * number is non-zero. If set indicates that this is a 567 * fragmented IP packet. 568 * 569 * tcp_only_ack 570 * Set if only the TCP Ack bit is set in the TCP flags and if 571 * the TCP payload is 0. 572 * 573 * sa_idx 574 * The offset in the address table which matches the MAC source 575 * address. 576 * 577 * reserved_2b 578 * Reserved: HW should fill with zero. FW should ignore. 579 */ 580 581#define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff 582#define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0 583#define RX_MSDU_END_INFO0_FIRST_MSDU BIT(14) 584#define RX_MSDU_END_INFO0_LAST_MSDU BIT(15) 585#define RX_MSDU_END_INFO0_MSDU_LIMIT_ERR BIT(18) 586#define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30) 587#define RX_MSDU_END_INFO0_RESERVED_3B BIT(31) 588 589struct rx_msdu_end_common { 590 __le16 ip_hdr_cksum; 591 __le16 tcp_hdr_cksum; 592 u8 key_id_octet; 593 u8 classification_filter; 594 u8 wapi_pn[10]; 595 __le32 info0; 596} __packed; 597 598#define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff 599#define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0 600#define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00 601#define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB 10 602#define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000 603#define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB 16 604#define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9) 605 606#define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f 607#define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0 608#define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0 609#define RX_MSDU_END_INFO2_SA_OFFSET_LSB 6 610#define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000 611#define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB 12 612 613struct rx_msdu_end_qca99x0 { 614 __le32 ipv6_crc; 615 __le32 tcp_seq_no; 616 __le32 tcp_ack_no; 617 __le32 info1; 618 __le32 info2; 619} __packed; 620 621struct rx_msdu_end_wcn3990 { 622 __le32 ipv6_crc; 623 __le32 tcp_seq_no; 624 __le32 tcp_ack_no; 625 __le32 info1; 626 __le32 info2; 627 __le32 rule_indication_0; 628 __le32 rule_indication_1; 629 __le32 rule_indication_2; 630 __le32 rule_indication_3; 631} __packed; 632 633struct rx_msdu_end { 634 struct rx_msdu_end_common common; 635 union { 636 struct rx_msdu_end_wcn3990 wcn3990; 637 } __packed; 638} __packed; 639 640struct rx_msdu_end_v1 { 641 struct rx_msdu_end_common common; 642 union { 643 struct rx_msdu_end_qca99x0 qca99x0; 644 } __packed; 645} __packed; 646 647/* 648 *ip_hdr_chksum 649 * This can include the IP header checksum or the pseudo header 650 * checksum used by TCP/UDP checksum. 651 * 652 *tcp_udp_chksum 653 * The value of the computed TCP/UDP checksum. A mode bit 654 * selects whether this checksum is the full checksum or the 655 * partial checksum which does not include the pseudo header. 656 * 657 *key_id_octet 658 * The key ID octet from the IV. Only valid when first_msdu is 659 * set. 660 * 661 *classification_filter 662 * Indicates the number classification filter rule 663 * 664 *ext_wapi_pn_63_48 665 * Extension PN (packet number) which is only used by WAPI. 666 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The 667 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start 668 * descriptor. 669 * 670 *ext_wapi_pn_95_64 671 * Extension PN (packet number) which is only used by WAPI. 672 * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and 673 * pn11). 674 * 675 *ext_wapi_pn_127_96 676 * Extension PN (packet number) which is only used by WAPI. 677 * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, 678 * pn15). 679 * 680 *reported_mpdu_length 681 * MPDU length before decapsulation. Only valid when 682 * first_msdu is set. This field is taken directly from the 683 * length field of the A-MPDU delimiter or the preamble length 684 * field for non-A-MPDU frames. 685 * 686 *first_msdu 687 * Indicates the first MSDU of A-MSDU. If both first_msdu and 688 * last_msdu are set in the MSDU then this is a non-aggregated 689 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 690 * have both first_mpdu and last_mpdu bits set to 0. 691 * 692 *last_msdu 693 * Indicates the last MSDU of the A-MSDU. MPDU end status is 694 * only valid when last_msdu is set. 695 * 696 *msdu_limit_error 697 * Indicates that the MSDU threshold was exceeded and thus 698 * all the rest of the MSDUs will not be scattered and 699 * will not be decapsulated but will be received in RAW format 700 * as a single MSDU buffer. 701 * 702 *reserved_3a 703 * Reserved: HW should fill with zero. FW should ignore. 704 * 705 *pre_delim_err 706 * Indicates that the first delimiter had a FCS failure. Only 707 * valid when first_mpdu and first_msdu are set. 708 * 709 *reserved_3b 710 * Reserved: HW should fill with zero. FW should ignore. 711 */ 712 713#define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04 714#define HTT_RX_PPDU_START_PREAMBLE_HT 0x08 715#define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09 716#define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C 717#define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D 718 719#define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0) 720 721#define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f 722#define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0 723#define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0 724#define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5 725#define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000 726#define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18 727#define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000 728#define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24 729#define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT BIT(4) 730#define RX_PPDU_START_INFO1_L_SIG_PARITY BIT(17) 731 732#define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff 733#define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0 734 735#define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff 736#define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0 737#define RX_PPDU_START_INFO3_TXBF_H_INFO BIT(24) 738 739#define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff 740#define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0 741 742#define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff 743#define RX_PPDU_START_INFO5_SERVICE_LSB 0 744 745/* No idea what this flag means. It seems to be always set in rate. */ 746#define RX_PPDU_START_RATE_FLAG BIT(3) 747 748struct rx_ppdu_start { 749 struct { 750 u8 pri20_mhz; 751 u8 ext20_mhz; 752 u8 ext40_mhz; 753 u8 ext80_mhz; 754 } rssi_chains[4]; 755 u8 rssi_comb; 756 __le16 rsvd0; 757 u8 info0; /* %RX_PPDU_START_INFO0_ */ 758 __le32 info1; /* %RX_PPDU_START_INFO1_ */ 759 __le32 info2; /* %RX_PPDU_START_INFO2_ */ 760 __le32 info3; /* %RX_PPDU_START_INFO3_ */ 761 __le32 info4; /* %RX_PPDU_START_INFO4_ */ 762 __le32 info5; /* %RX_PPDU_START_INFO5_ */ 763} __packed; 764 765/* 766 * rssi_chain0_pri20 767 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 768 * Value of 0x80 indicates invalid. 769 * 770 * rssi_chain0_sec20 771 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth. 772 * Value of 0x80 indicates invalid. 773 * 774 * rssi_chain0_sec40 775 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth. 776 * Value of 0x80 indicates invalid. 777 * 778 * rssi_chain0_sec80 779 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth. 780 * Value of 0x80 indicates invalid. 781 * 782 * rssi_chain1_pri20 783 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 784 * Value of 0x80 indicates invalid. 785 * 786 * rssi_chain1_sec20 787 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth. 788 * Value of 0x80 indicates invalid. 789 * 790 * rssi_chain1_sec40 791 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth. 792 * Value of 0x80 indicates invalid. 793 * 794 * rssi_chain1_sec80 795 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth. 796 * Value of 0x80 indicates invalid. 797 * 798 * rssi_chain2_pri20 799 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 800 * Value of 0x80 indicates invalid. 801 * 802 * rssi_chain2_sec20 803 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth. 804 * Value of 0x80 indicates invalid. 805 * 806 * rssi_chain2_sec40 807 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth. 808 * Value of 0x80 indicates invalid. 809 * 810 * rssi_chain2_sec80 811 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth. 812 * Value of 0x80 indicates invalid. 813 * 814 * rssi_chain3_pri20 815 * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 816 * Value of 0x80 indicates invalid. 817 * 818 * rssi_chain3_sec20 819 * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth. 820 * Value of 0x80 indicates invalid. 821 * 822 * rssi_chain3_sec40 823 * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth. 824 * Value of 0x80 indicates invalid. 825 * 826 * rssi_chain3_sec80 827 * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth. 828 * Value of 0x80 indicates invalid. 829 * 830 * rssi_comb 831 * The combined RSSI of RX PPDU of all active chains and 832 * bandwidths. Value of 0x80 indicates invalid. 833 * 834 * reserved_4a 835 * Reserved: HW should fill with 0, FW should ignore. 836 * 837 * is_greenfield 838 * Do we really support this? 839 * 840 * reserved_4b 841 * Reserved: HW should fill with 0, FW should ignore. 842 * 843 * l_sig_rate 844 * If l_sig_rate_select is 0: 845 * 0x8: OFDM 48 Mbps 846 * 0x9: OFDM 24 Mbps 847 * 0xA: OFDM 12 Mbps 848 * 0xB: OFDM 6 Mbps 849 * 0xC: OFDM 54 Mbps 850 * 0xD: OFDM 36 Mbps 851 * 0xE: OFDM 18 Mbps 852 * 0xF: OFDM 9 Mbps 853 * If l_sig_rate_select is 1: 854 * 0x8: CCK 11 Mbps long preamble 855 * 0x9: CCK 5.5 Mbps long preamble 856 * 0xA: CCK 2 Mbps long preamble 857 * 0xB: CCK 1 Mbps long preamble 858 * 0xC: CCK 11 Mbps short preamble 859 * 0xD: CCK 5.5 Mbps short preamble 860 * 0xE: CCK 2 Mbps short preamble 861 * 862 * l_sig_rate_select 863 * Legacy signal rate select. If set then l_sig_rate indicates 864 * CCK rates. If clear then l_sig_rate indicates OFDM rates. 865 * 866 * l_sig_length 867 * Length of legacy frame in octets. 868 * 869 * l_sig_parity 870 * Odd parity over l_sig_rate and l_sig_length 871 * 872 * l_sig_tail 873 * Tail bits for Viterbi decoder 874 * 875 * preamble_type 876 * Indicates the type of preamble ahead: 877 * 0x4: Legacy (OFDM/CCK) 878 * 0x8: HT 879 * 0x9: HT with TxBF 880 * 0xC: VHT 881 * 0xD: VHT with TxBF 882 * 0x80 - 0xFF: Reserved for special baseband data types such 883 * as radar and spectral scan. 884 * 885 * ht_sig_vht_sig_a_1 886 * If preamble_type == 0x8 or 0x9 887 * HT-SIG (first 24 bits) 888 * If preamble_type == 0xC or 0xD 889 * VHT-SIG A (first 24 bits) 890 * Else 891 * Reserved 892 * 893 * reserved_6 894 * Reserved: HW should fill with 0, FW should ignore. 895 * 896 * ht_sig_vht_sig_a_2 897 * If preamble_type == 0x8 or 0x9 898 * HT-SIG (last 24 bits) 899 * If preamble_type == 0xC or 0xD 900 * VHT-SIG A (last 24 bits) 901 * Else 902 * Reserved 903 * 904 * txbf_h_info 905 * Indicates that the packet data carries H information which 906 * is used for TxBF debug. 907 * 908 * reserved_7 909 * Reserved: HW should fill with 0, FW should ignore. 910 * 911 * vht_sig_b 912 * WiFi 1.0 and WiFi 2.0 will likely have this field to be all 913 * 0s since the BB does not plan on decoding VHT SIG-B. 914 * 915 * reserved_8 916 * Reserved: HW should fill with 0, FW should ignore. 917 * 918 * service 919 * Service field from BB for OFDM, HT and VHT packets. CCK 920 * packets will have service field of 0. 921 * 922 * reserved_9 923 * Reserved: HW should fill with 0, FW should ignore. 924 */ 925 926#define RX_PPDU_END_FLAGS_PHY_ERR BIT(0) 927#define RX_PPDU_END_FLAGS_RX_LOCATION BIT(1) 928#define RX_PPDU_END_FLAGS_TXBF_H_INFO BIT(2) 929 930#define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff 931#define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0 932#define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK BIT(24) 933#define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL BIT(25) 934 935#define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc 936#define RX_PPDU_END_INFO1_PEER_IDX_LSB 2 937#define RX_PPDU_END_INFO1_BB_DATA BIT(0) 938#define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1) 939#define RX_PPDU_END_INFO1_PPDU_DONE BIT(15) 940 941struct rx_ppdu_end_common { 942 __le32 evm_p0; 943 __le32 evm_p1; 944 __le32 evm_p2; 945 __le32 evm_p3; 946 __le32 evm_p4; 947 __le32 evm_p5; 948 __le32 evm_p6; 949 __le32 evm_p7; 950 __le32 evm_p8; 951 __le32 evm_p9; 952 __le32 evm_p10; 953 __le32 evm_p11; 954 __le32 evm_p12; 955 __le32 evm_p13; 956 __le32 evm_p14; 957 __le32 evm_p15; 958 __le32 tsf_timestamp; 959 __le32 wb_timestamp; 960} __packed; 961 962struct rx_ppdu_end_qca988x { 963 u8 locationing_timestamp; 964 u8 phy_err_code; 965 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 966 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 967 __le16 bb_length; 968 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 969} __packed; 970 971#define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff 972#define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0 973#define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000 974#define RX_PPDU_END_RTT_UNUSED_LSB 24 975#define RX_PPDU_END_RTT_NORMAL_MODE BIT(31) 976 977struct rx_ppdu_end_qca6174 { 978 u8 locationing_timestamp; 979 u8 phy_err_code; 980 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 981 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 982 __le32 rtt; /* %RX_PPDU_END_RTT_ */ 983 __le16 bb_length; 984 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 985} __packed; 986 987#define RX_PKT_END_INFO0_RX_SUCCESS BIT(0) 988#define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3) 989#define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4) 990#define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5) 991#define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6) 992#define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7) 993 994#define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff 995#define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0 996#define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000 997#define RX_LOCATION_INFO_FAC_STATUS_LSB 18 998#define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000 999#define RX_LOCATION_INFO_PKT_BW_LSB 20 1000#define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000 1001#define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB 23 1002#define RX_LOCATION_INFO_CIR_STATUS BIT(17) 1003#define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25) 1004#define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26) 1005#define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30) 1006#define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31) 1007 1008struct rx_pkt_end { 1009 __le32 info0; /* %RX_PKT_END_INFO0_ */ 1010 __le32 phy_timestamp_1; 1011 __le32 phy_timestamp_2; 1012} __packed; 1013 1014struct rx_pkt_end_wcn3990 { 1015 __le32 info0; /* %RX_PKT_END_INFO0_ */ 1016 __le64 phy_timestamp_1; 1017 __le64 phy_timestamp_2; 1018} __packed; 1019 1020#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff 1021#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0 1022#define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000 1023#define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15 1024#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000 1025#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30 1026#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) 1027#define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) 1028 1029#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c 1030#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2 1031#define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030 1032#define RX_LOCATION_INFO1_PKT_BW_LSB 4 1033#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00 1034#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8 1035#define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000 1036#define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16 1037#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000 1038#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20 1039#define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000 1040#define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22 1041#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000 1042#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27 1043#define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) 1044#define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) 1045#define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) 1046#define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) 1047#define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) 1048#define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) 1049 1050struct rx_location_info { 1051 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1052 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1053} __packed; 1054 1055struct rx_location_info_wcn3990 { 1056 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1057 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1058 __le32 rx_location_info2; /* %RX_LOCATION_INFO2_ */ 1059} __packed; 1060 1061enum rx_phy_ppdu_end_info0 { 1062 RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2), 1063 RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3), 1064 RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4), 1065 RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5), 1066 RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6), 1067 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7), 1068 RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8), 1069 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9), 1070 RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10), 1071 RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11), 1072 RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12), 1073 RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13), 1074 RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14), 1075 RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15), 1076 RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16), 1077 RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17), 1078 RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18), 1079 RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19), 1080 RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20), 1081 RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21), 1082 RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22), 1083 RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23), 1084 RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24), 1085 RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25), 1086 RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26), 1087 RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27), 1088 RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28), 1089 RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29), 1090 RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30), 1091 RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31), 1092}; 1093 1094enum rx_phy_ppdu_end_info1 { 1095 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0), 1096 RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1), 1097 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2), 1098 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3), 1099 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4), 1100 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5), 1101 RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6), 1102 RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7), 1103 RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8), 1104 RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9), 1105 RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10), 1106 RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11), 1107 RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12), 1108 RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13), 1109}; 1110 1111struct rx_phy_ppdu_end { 1112 __le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */ 1113 __le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */ 1114} __packed; 1115 1116#define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff 1117#define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0 1118 1119#define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff 1120#define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0 1121#define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24) 1122#define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25) 1123#define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26) 1124#define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27) 1125#define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28) 1126#define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29) 1127#define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30) 1128 1129struct rx_ppdu_end_qca99x0 { 1130 struct rx_pkt_end rx_pkt_end; 1131 __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ 1132 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1133 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1134 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1135 __le16 bb_length; 1136 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1137} __packed; 1138 1139struct rx_ppdu_end_qca9984 { 1140 struct rx_pkt_end rx_pkt_end; 1141 struct rx_location_info rx_location_info; 1142 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1143 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1144 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1145 __le16 bb_length; 1146 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1147} __packed; 1148 1149struct rx_ppdu_end_wcn3990 { 1150 struct rx_pkt_end_wcn3990 rx_pkt_end; 1151 struct rx_location_info_wcn3990 rx_location_info; 1152 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1153 __le32 rx_timing_offset; 1154 __le32 reserved_info_0; 1155 __le32 reserved_info_1; 1156 __le32 rx_antenna_info; 1157 __le32 rx_coex_info; 1158 __le32 rx_mpdu_cnt_info; 1159 __le64 phy_timestamp_tx; 1160 __le32 rx_bb_length; 1161} __packed; 1162 1163struct rx_ppdu_end { 1164 struct rx_ppdu_end_common common; 1165 union { 1166 struct rx_ppdu_end_wcn3990 wcn3990; 1167 } __packed; 1168} __packed; 1169 1170struct rx_ppdu_end_v1 { 1171 struct rx_ppdu_end_common common; 1172 union { 1173 struct rx_ppdu_end_qca988x qca988x; 1174 struct rx_ppdu_end_qca6174 qca6174; 1175 struct rx_ppdu_end_qca99x0 qca99x0; 1176 struct rx_ppdu_end_qca9984 qca9984; 1177 } __packed; 1178} __packed; 1179 1180/* 1181 * evm_p0 1182 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3. 1183 * 1184 * evm_p1 1185 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3. 1186 * 1187 * evm_p2 1188 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3. 1189 * 1190 * evm_p3 1191 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3. 1192 * 1193 * evm_p4 1194 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3. 1195 * 1196 * evm_p5 1197 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3. 1198 * 1199 * evm_p6 1200 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3. 1201 * 1202 * evm_p7 1203 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3. 1204 * 1205 * evm_p8 1206 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3. 1207 * 1208 * evm_p9 1209 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3. 1210 * 1211 * evm_p10 1212 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3. 1213 * 1214 * evm_p11 1215 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3. 1216 * 1217 * evm_p12 1218 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3. 1219 * 1220 * evm_p13 1221 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3. 1222 * 1223 * evm_p14 1224 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3. 1225 * 1226 * evm_p15 1227 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3. 1228 * 1229 * tsf_timestamp 1230 * Receive TSF timestamp sampled on the rising edge of 1231 * rx_clear. For PHY errors this may be the current TSF when 1232 * phy_error is asserted if the rx_clear does not assert before 1233 * the end of the PHY error. 1234 * 1235 * wb_timestamp 1236 * WLAN/BT timestamp is a 1 usec resolution timestamp which 1237 * does not get updated based on receive beacon like TSF. The 1238 * same rules for capturing tsf_timestamp are used to capture 1239 * the wb_timestamp. 1240 * 1241 * locationing_timestamp 1242 * Timestamp used for locationing. This timestamp is used to 1243 * indicate fractions of usec. For example if the MAC clock is 1244 * running at 80 MHz, the timestamp will increment every 12.5 1245 * nsec. The value starts at 0 and increments to 79 and 1246 * returns to 0 and repeats. This information is valid for 1247 * every PPDU. This information can be used in conjunction 1248 * with wb_timestamp to capture large delta times. 1249 * 1250 * phy_err_code 1251 * See the 1.10.8.1.2 for the list of the PHY error codes. 1252 * 1253 * phy_err 1254 * Indicates a PHY error was detected for this PPDU. 1255 * 1256 * rx_location 1257 * Indicates that location information was requested. 1258 * 1259 * txbf_h_info 1260 * Indicates that the packet data carries H information which 1261 * is used for TxBF debug. 1262 * 1263 * reserved_18 1264 * Reserved: HW should fill with 0, FW should ignore. 1265 * 1266 * rx_antenna 1267 * Receive antenna value 1268 * 1269 * tx_ht_vht_ack 1270 * Indicates that a HT or VHT Ack/BA frame was transmitted in 1271 * response to this receive packet. 1272 * 1273 * bb_captured_channel 1274 * Indicates that the BB has captured a channel dump. FW can 1275 * then read the channel dump memory. This may indicate that 1276 * the channel was captured either based on PCU setting the 1277 * capture_channel bit BB descriptor or FW setting the 1278 * capture_channel mode bit. 1279 * 1280 * reserved_19 1281 * Reserved: HW should fill with 0, FW should ignore. 1282 * 1283 * bb_length 1284 * Indicates the number of bytes of baseband information for 1285 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF 1286 * which indicates that this is not a normal PPDU but rather 1287 * contains baseband debug information. 1288 * 1289 * reserved_20 1290 * Reserved: HW should fill with 0, FW should ignore. 1291 * 1292 * ppdu_done 1293 * PPDU end status is only valid when ppdu_done bit is set. 1294 * Every time HW sets this bit in memory FW/SW must clear this 1295 * bit in memory. FW will initialize all the ppdu_done dword 1296 * to 0. 1297 */ 1298 1299#define FW_RX_DESC_INFO0_DISCARD BIT(0) 1300#define FW_RX_DESC_INFO0_FORWARD BIT(1) 1301#define FW_RX_DESC_INFO0_INSPECT BIT(5) 1302#define FW_RX_DESC_INFO0_EXT_MASK 0xC0 1303#define FW_RX_DESC_INFO0_EXT_LSB 6 1304 1305struct fw_rx_desc_base { 1306 u8 info0; 1307} __packed; 1308 1309#define FW_RX_DESC_FLAGS_FIRST_MSDU (1 << 0) 1310#define FW_RX_DESC_FLAGS_LAST_MSDU (1 << 1) 1311#define FW_RX_DESC_C3_FAILED (1 << 2) 1312#define FW_RX_DESC_C4_FAILED (1 << 3) 1313#define FW_RX_DESC_IPV6 (1 << 4) 1314#define FW_RX_DESC_TCP (1 << 5) 1315#define FW_RX_DESC_UDP (1 << 6) 1316 1317struct fw_rx_desc_hl { 1318 union { 1319 struct { 1320 u8 discard:1, 1321 forward:1, 1322 any_err:1, 1323 dup_err:1, 1324 reserved:1, 1325 inspect:1, 1326 extension:2; 1327 } bits; 1328 u8 info0; 1329 } u; 1330 1331 u8 version; 1332 u8 len; 1333 u8 flags; 1334} __packed; 1335 1336#endif /* _RX_DESC_H_ */ 1337