1// SPDX-License-Identifier: GPL-2.0-or-later 2/* Freescale QUICC Engine HDLC Device Driver 3 * 4 * Copyright 2016 Freescale Semiconductor Inc. 5 */ 6 7#include <linux/delay.h> 8#include <linux/dma-mapping.h> 9#include <linux/hdlc.h> 10#include <linux/init.h> 11#include <linux/interrupt.h> 12#include <linux/io.h> 13#include <linux/irq.h> 14#include <linux/kernel.h> 15#include <linux/module.h> 16#include <linux/netdevice.h> 17#include <linux/of_address.h> 18#include <linux/of_irq.h> 19#include <linux/of_platform.h> 20#include <linux/platform_device.h> 21#include <linux/sched.h> 22#include <linux/skbuff.h> 23#include <linux/slab.h> 24#include <linux/spinlock.h> 25#include <linux/stddef.h> 26#include <soc/fsl/qe/qe_tdm.h> 27#include <uapi/linux/if_arp.h> 28 29#include "fsl_ucc_hdlc.h" 30 31#define DRV_DESC "Freescale QE UCC HDLC Driver" 32#define DRV_NAME "ucc_hdlc" 33 34#define TDM_PPPOHT_SLIC_MAXIN 35#define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S) 36 37static int uhdlc_close(struct net_device *dev); 38 39static struct ucc_tdm_info utdm_primary_info = { 40 .uf_info = { 41 .tsa = 0, 42 .cdp = 0, 43 .cds = 1, 44 .ctsp = 1, 45 .ctss = 1, 46 .revd = 0, 47 .urfs = 256, 48 .utfs = 256, 49 .urfet = 128, 50 .urfset = 192, 51 .utfet = 128, 52 .utftt = 0x40, 53 .ufpt = 256, 54 .mode = UCC_FAST_PROTOCOL_MODE_HDLC, 55 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 56 .tenc = UCC_FAST_TX_ENCODING_NRZ, 57 .renc = UCC_FAST_RX_ENCODING_NRZ, 58 .tcrc = UCC_FAST_16_BIT_CRC, 59 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 60 }, 61 62 .si_info = { 63#ifdef TDM_PPPOHT_SLIC_MAXIN 64 .simr_rfsd = 1, 65 .simr_tfsd = 2, 66#else 67 .simr_rfsd = 0, 68 .simr_tfsd = 0, 69#endif 70 .simr_crt = 0, 71 .simr_sl = 0, 72 .simr_ce = 1, 73 .simr_fe = 1, 74 .simr_gm = 0, 75 }, 76}; 77 78static struct ucc_tdm_info utdm_info[UCC_MAX_NUM]; 79 80static int uhdlc_init(struct ucc_hdlc_private *priv) 81{ 82 struct ucc_tdm_info *ut_info; 83 struct ucc_fast_info *uf_info; 84 u32 cecr_subblock; 85 u16 bd_status; 86 int ret, i; 87 void *bd_buffer; 88 dma_addr_t bd_dma_addr; 89 s32 riptr; 90 s32 tiptr; 91 u32 gumr; 92 93 ut_info = priv->ut_info; 94 uf_info = &ut_info->uf_info; 95 96 if (priv->tsa) { 97 uf_info->tsa = 1; 98 uf_info->ctsp = 1; 99 uf_info->cds = 1; 100 uf_info->ctss = 1; 101 } else { 102 uf_info->cds = 0; 103 uf_info->ctsp = 0; 104 uf_info->ctss = 0; 105 } 106 107 /* This sets HPM register in CMXUCR register which configures a 108 * open drain connected HDLC bus 109 */ 110 if (priv->hdlc_bus) 111 uf_info->brkpt_support = 1; 112 113 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF | 114 UCC_HDLC_UCCE_TXB) << 16); 115 116 ret = ucc_fast_init(uf_info, &priv->uccf); 117 if (ret) { 118 dev_err(priv->dev, "Failed to init uccf."); 119 return ret; 120 } 121 122 priv->uf_regs = priv->uccf->uf_regs; 123 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 124 125 /* Loopback mode */ 126 if (priv->loopback) { 127 dev_info(priv->dev, "Loopback Mode\n"); 128 /* use the same clock when work in loopback */ 129 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1); 130 131 gumr = ioread32be(&priv->uf_regs->gumr); 132 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS | 133 UCC_FAST_GUMR_TCI); 134 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN); 135 iowrite32be(gumr, &priv->uf_regs->gumr); 136 } 137 138 /* Initialize SI */ 139 if (priv->tsa) 140 ucc_tdm_init(priv->utdm, priv->ut_info); 141 142 /* Write to QE CECR, UCCx channel to Stop Transmission */ 143 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 144 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock, 145 QE_CR_PROTOCOL_UNSPECIFIED, 0); 146 147 /* Set UPSMR normal mode (need fixed)*/ 148 iowrite32be(0, &priv->uf_regs->upsmr); 149 150 /* hdlc_bus mode */ 151 if (priv->hdlc_bus) { 152 u32 upsmr; 153 154 dev_info(priv->dev, "HDLC bus Mode\n"); 155 upsmr = ioread32be(&priv->uf_regs->upsmr); 156 157 /* bus mode and retransmit enable, with collision window 158 * set to 8 bytes 159 */ 160 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS | 161 UCC_HDLC_UPSMR_CW8; 162 iowrite32be(upsmr, &priv->uf_regs->upsmr); 163 164 /* explicitly disable CDS & CTSP */ 165 gumr = ioread32be(&priv->uf_regs->gumr); 166 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP); 167 /* set automatic sync to explicitly ignore CD signal */ 168 gumr |= UCC_FAST_GUMR_SYNL_AUTO; 169 iowrite32be(gumr, &priv->uf_regs->gumr); 170 } 171 172 priv->rx_ring_size = RX_BD_RING_LEN; 173 priv->tx_ring_size = TX_BD_RING_LEN; 174 /* Alloc Rx BD */ 175 priv->rx_bd_base = dma_alloc_coherent(priv->dev, 176 RX_BD_RING_LEN * sizeof(struct qe_bd), 177 &priv->dma_rx_bd, GFP_KERNEL); 178 179 if (!priv->rx_bd_base) { 180 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n"); 181 ret = -ENOMEM; 182 goto free_uccf; 183 } 184 185 /* Alloc Tx BD */ 186 priv->tx_bd_base = dma_alloc_coherent(priv->dev, 187 TX_BD_RING_LEN * sizeof(struct qe_bd), 188 &priv->dma_tx_bd, GFP_KERNEL); 189 190 if (!priv->tx_bd_base) { 191 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n"); 192 ret = -ENOMEM; 193 goto free_rx_bd; 194 } 195 196 /* Alloc parameter ram for ucc hdlc */ 197 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param), 198 ALIGNMENT_OF_UCC_HDLC_PRAM); 199 200 if (priv->ucc_pram_offset < 0) { 201 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n"); 202 ret = -ENOMEM; 203 goto free_tx_bd; 204 } 205 206 priv->rx_skbuff = kcalloc(priv->rx_ring_size, 207 sizeof(*priv->rx_skbuff), 208 GFP_KERNEL); 209 if (!priv->rx_skbuff) { 210 ret = -ENOMEM; 211 goto free_ucc_pram; 212 } 213 214 priv->tx_skbuff = kcalloc(priv->tx_ring_size, 215 sizeof(*priv->tx_skbuff), 216 GFP_KERNEL); 217 if (!priv->tx_skbuff) { 218 ret = -ENOMEM; 219 goto free_rx_skbuff; 220 } 221 222 priv->skb_curtx = 0; 223 priv->skb_dirtytx = 0; 224 priv->curtx_bd = priv->tx_bd_base; 225 priv->dirty_tx = priv->tx_bd_base; 226 priv->currx_bd = priv->rx_bd_base; 227 priv->currx_bdnum = 0; 228 229 /* init parameter base */ 230 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 231 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, 232 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); 233 234 priv->ucc_pram = (struct ucc_hdlc_param __iomem *) 235 qe_muram_addr(priv->ucc_pram_offset); 236 237 /* Zero out parameter ram */ 238 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param)); 239 240 /* Alloc riptr, tiptr */ 241 riptr = qe_muram_alloc(32, 32); 242 if (riptr < 0) { 243 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n"); 244 ret = -ENOMEM; 245 goto free_tx_skbuff; 246 } 247 248 tiptr = qe_muram_alloc(32, 32); 249 if (tiptr < 0) { 250 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n"); 251 ret = -ENOMEM; 252 goto free_riptr; 253 } 254 if (riptr != (u16)riptr || tiptr != (u16)tiptr) { 255 dev_err(priv->dev, "MURAM allocation out of addressable range\n"); 256 ret = -ENOMEM; 257 goto free_tiptr; 258 } 259 260 /* Set RIPTR, TIPTR */ 261 iowrite16be(riptr, &priv->ucc_pram->riptr); 262 iowrite16be(tiptr, &priv->ucc_pram->tiptr); 263 264 /* Set MRBLR */ 265 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr); 266 267 /* Set RBASE, TBASE */ 268 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase); 269 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase); 270 271 /* Set RSTATE, TSTATE */ 272 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate); 273 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate); 274 275 /* Set C_MASK, C_PRES for 16bit CRC */ 276 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask); 277 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres); 278 279 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr); 280 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr); 281 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt); 282 iowrite16be(priv->hmask, &priv->ucc_pram->hmask); 283 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1); 284 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2); 285 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3); 286 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4); 287 288 /* Get BD buffer */ 289 bd_buffer = dma_alloc_coherent(priv->dev, 290 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH, 291 &bd_dma_addr, GFP_KERNEL); 292 293 if (!bd_buffer) { 294 dev_err(priv->dev, "Could not allocate buffer descriptors\n"); 295 ret = -ENOMEM; 296 goto free_tiptr; 297 } 298 299 priv->rx_buffer = bd_buffer; 300 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; 301 302 priv->dma_rx_addr = bd_dma_addr; 303 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; 304 305 for (i = 0; i < RX_BD_RING_LEN; i++) { 306 if (i < (RX_BD_RING_LEN - 1)) 307 bd_status = R_E_S | R_I_S; 308 else 309 bd_status = R_E_S | R_I_S | R_W_S; 310 311 priv->rx_bd_base[i].status = cpu_to_be16(bd_status); 312 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH); 313 } 314 315 for (i = 0; i < TX_BD_RING_LEN; i++) { 316 if (i < (TX_BD_RING_LEN - 1)) 317 bd_status = T_I_S | T_TC_S; 318 else 319 bd_status = T_I_S | T_TC_S | T_W_S; 320 321 priv->tx_bd_base[i].status = cpu_to_be16(bd_status); 322 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH); 323 } 324 dma_wmb(); 325 326 return 0; 327 328free_tiptr: 329 qe_muram_free(tiptr); 330free_riptr: 331 qe_muram_free(riptr); 332free_tx_skbuff: 333 kfree(priv->tx_skbuff); 334free_rx_skbuff: 335 kfree(priv->rx_skbuff); 336free_ucc_pram: 337 qe_muram_free(priv->ucc_pram_offset); 338free_tx_bd: 339 dma_free_coherent(priv->dev, 340 TX_BD_RING_LEN * sizeof(struct qe_bd), 341 priv->tx_bd_base, priv->dma_tx_bd); 342free_rx_bd: 343 dma_free_coherent(priv->dev, 344 RX_BD_RING_LEN * sizeof(struct qe_bd), 345 priv->rx_bd_base, priv->dma_rx_bd); 346free_uccf: 347 ucc_fast_free(priv->uccf); 348 349 return ret; 350} 351 352static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev) 353{ 354 hdlc_device *hdlc = dev_to_hdlc(dev); 355 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv; 356 struct qe_bd *bd; 357 u16 bd_status; 358 unsigned long flags; 359 __be16 *proto_head; 360 361 switch (dev->type) { 362 case ARPHRD_RAWHDLC: 363 if (skb_headroom(skb) < HDLC_HEAD_LEN) { 364 dev->stats.tx_dropped++; 365 dev_kfree_skb(skb); 366 netdev_err(dev, "No enough space for hdlc head\n"); 367 return -ENOMEM; 368 } 369 370 skb_push(skb, HDLC_HEAD_LEN); 371 372 proto_head = (__be16 *)skb->data; 373 *proto_head = htons(DEFAULT_HDLC_HEAD); 374 375 dev->stats.tx_bytes += skb->len; 376 break; 377 378 case ARPHRD_PPP: 379 proto_head = (__be16 *)skb->data; 380 if (*proto_head != htons(DEFAULT_PPP_HEAD)) { 381 dev->stats.tx_dropped++; 382 dev_kfree_skb(skb); 383 netdev_err(dev, "Wrong ppp header\n"); 384 return -ENOMEM; 385 } 386 387 dev->stats.tx_bytes += skb->len; 388 break; 389 390 case ARPHRD_ETHER: 391 dev->stats.tx_bytes += skb->len; 392 break; 393 394 default: 395 dev->stats.tx_dropped++; 396 dev_kfree_skb(skb); 397 return -ENOMEM; 398 } 399 netdev_sent_queue(dev, skb->len); 400 spin_lock_irqsave(&priv->lock, flags); 401 402 dma_rmb(); 403 /* Start from the next BD that should be filled */ 404 bd = priv->curtx_bd; 405 bd_status = be16_to_cpu(bd->status); 406 /* Save the skb pointer so we can free it later */ 407 priv->tx_skbuff[priv->skb_curtx] = skb; 408 409 /* Update the current skb pointer (wrapping if this was the last) */ 410 priv->skb_curtx = 411 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); 412 413 /* copy skb data to tx buffer for sdma processing */ 414 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr), 415 skb->data, skb->len); 416 417 /* set bd status and length */ 418 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S; 419 420 bd->length = cpu_to_be16(skb->len); 421 bd->status = cpu_to_be16(bd_status); 422 423 /* Move to next BD in the ring */ 424 if (!(bd_status & T_W_S)) 425 bd += 1; 426 else 427 bd = priv->tx_bd_base; 428 429 if (bd == priv->dirty_tx) { 430 if (!netif_queue_stopped(dev)) 431 netif_stop_queue(dev); 432 } 433 434 priv->curtx_bd = bd; 435 436 spin_unlock_irqrestore(&priv->lock, flags); 437 438 return NETDEV_TX_OK; 439} 440 441static int hdlc_tx_restart(struct ucc_hdlc_private *priv) 442{ 443 u32 cecr_subblock; 444 445 cecr_subblock = 446 ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num); 447 448 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, 449 QE_CR_PROTOCOL_UNSPECIFIED, 0); 450 return 0; 451} 452 453static int hdlc_tx_done(struct ucc_hdlc_private *priv) 454{ 455 /* Start from the next BD that should be filled */ 456 struct net_device *dev = priv->ndev; 457 unsigned int bytes_sent = 0; 458 int howmany = 0; 459 struct qe_bd *bd; /* BD pointer */ 460 u16 bd_status; 461 int tx_restart = 0; 462 463 dma_rmb(); 464 bd = priv->dirty_tx; 465 bd_status = be16_to_cpu(bd->status); 466 467 /* Normal processing. */ 468 while ((bd_status & T_R_S) == 0) { 469 struct sk_buff *skb; 470 471 if (bd_status & T_UN_S) { /* Underrun */ 472 dev->stats.tx_fifo_errors++; 473 tx_restart = 1; 474 } 475 if (bd_status & T_CT_S) { /* Carrier lost */ 476 dev->stats.tx_carrier_errors++; 477 tx_restart = 1; 478 } 479 480 /* BD contains already transmitted buffer. */ 481 /* Handle the transmitted buffer and release */ 482 /* the BD to be used with the current frame */ 483 484 skb = priv->tx_skbuff[priv->skb_dirtytx]; 485 if (!skb) 486 break; 487 howmany++; 488 bytes_sent += skb->len; 489 dev->stats.tx_packets++; 490 memset(priv->tx_buffer + 491 (be32_to_cpu(bd->buf) - priv->dma_tx_addr), 492 0, skb->len); 493 dev_consume_skb_irq(skb); 494 495 priv->tx_skbuff[priv->skb_dirtytx] = NULL; 496 priv->skb_dirtytx = 497 (priv->skb_dirtytx + 498 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); 499 500 /* We freed a buffer, so now we can restart transmission */ 501 if (netif_queue_stopped(dev)) 502 netif_wake_queue(dev); 503 504 /* Advance the confirmation BD pointer */ 505 if (!(bd_status & T_W_S)) 506 bd += 1; 507 else 508 bd = priv->tx_bd_base; 509 bd_status = be16_to_cpu(bd->status); 510 } 511 priv->dirty_tx = bd; 512 513 if (tx_restart) 514 hdlc_tx_restart(priv); 515 516 netdev_completed_queue(dev, howmany, bytes_sent); 517 return 0; 518} 519 520static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit) 521{ 522 struct net_device *dev = priv->ndev; 523 struct sk_buff *skb = NULL; 524 hdlc_device *hdlc = dev_to_hdlc(dev); 525 struct qe_bd *bd; 526 u16 bd_status; 527 u16 length, howmany = 0; 528 u8 *bdbuffer; 529 530 dma_rmb(); 531 bd = priv->currx_bd; 532 bd_status = be16_to_cpu(bd->status); 533 534 /* while there are received buffers and BD is full (~R_E) */ 535 while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) { 536 if (bd_status & (RX_BD_ERRORS)) { 537 dev->stats.rx_errors++; 538 539 if (bd_status & R_CD_S) 540 dev->stats.collisions++; 541 if (bd_status & R_OV_S) 542 dev->stats.rx_fifo_errors++; 543 if (bd_status & R_CR_S) 544 dev->stats.rx_crc_errors++; 545 if (bd_status & R_AB_S) 546 dev->stats.rx_over_errors++; 547 if (bd_status & R_NO_S) 548 dev->stats.rx_frame_errors++; 549 if (bd_status & R_LG_S) 550 dev->stats.rx_length_errors++; 551 552 goto recycle; 553 } 554 bdbuffer = priv->rx_buffer + 555 (priv->currx_bdnum * MAX_RX_BUF_LENGTH); 556 length = be16_to_cpu(bd->length); 557 558 switch (dev->type) { 559 case ARPHRD_RAWHDLC: 560 bdbuffer += HDLC_HEAD_LEN; 561 length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE); 562 563 skb = dev_alloc_skb(length); 564 if (!skb) { 565 dev->stats.rx_dropped++; 566 return -ENOMEM; 567 } 568 569 skb_put(skb, length); 570 skb->len = length; 571 skb->dev = dev; 572 memcpy(skb->data, bdbuffer, length); 573 break; 574 575 case ARPHRD_PPP: 576 case ARPHRD_ETHER: 577 length -= HDLC_CRC_SIZE; 578 579 skb = dev_alloc_skb(length); 580 if (!skb) { 581 dev->stats.rx_dropped++; 582 return -ENOMEM; 583 } 584 585 skb_put(skb, length); 586 skb->len = length; 587 skb->dev = dev; 588 memcpy(skb->data, bdbuffer, length); 589 break; 590 } 591 592 dev->stats.rx_packets++; 593 dev->stats.rx_bytes += skb->len; 594 howmany++; 595 if (hdlc->proto) 596 skb->protocol = hdlc_type_trans(skb, dev); 597 netif_receive_skb(skb); 598 599recycle: 600 bd->status = cpu_to_be16((bd_status & R_W_S) | R_E_S | R_I_S); 601 602 /* update to point at the next bd */ 603 if (bd_status & R_W_S) { 604 priv->currx_bdnum = 0; 605 bd = priv->rx_bd_base; 606 } else { 607 if (priv->currx_bdnum < (RX_BD_RING_LEN - 1)) 608 priv->currx_bdnum += 1; 609 else 610 priv->currx_bdnum = RX_BD_RING_LEN - 1; 611 612 bd += 1; 613 } 614 615 bd_status = be16_to_cpu(bd->status); 616 } 617 dma_rmb(); 618 619 priv->currx_bd = bd; 620 return howmany; 621} 622 623static int ucc_hdlc_poll(struct napi_struct *napi, int budget) 624{ 625 struct ucc_hdlc_private *priv = container_of(napi, 626 struct ucc_hdlc_private, 627 napi); 628 int howmany; 629 630 /* Tx event processing */ 631 spin_lock(&priv->lock); 632 hdlc_tx_done(priv); 633 spin_unlock(&priv->lock); 634 635 howmany = 0; 636 howmany += hdlc_rx_done(priv, budget - howmany); 637 638 if (howmany < budget) { 639 napi_complete_done(napi, howmany); 640 qe_setbits_be32(priv->uccf->p_uccm, 641 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16); 642 } 643 644 return howmany; 645} 646 647static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id) 648{ 649 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id; 650 struct net_device *dev = priv->ndev; 651 struct ucc_fast_private *uccf; 652 u32 ucce; 653 u32 uccm; 654 655 uccf = priv->uccf; 656 657 ucce = ioread32be(uccf->p_ucce); 658 uccm = ioread32be(uccf->p_uccm); 659 ucce &= uccm; 660 iowrite32be(ucce, uccf->p_ucce); 661 if (!ucce) 662 return IRQ_NONE; 663 664 if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) { 665 if (napi_schedule_prep(&priv->napi)) { 666 uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) 667 << 16); 668 iowrite32be(uccm, uccf->p_uccm); 669 __napi_schedule(&priv->napi); 670 } 671 } 672 673 /* Errors and other events */ 674 if (ucce >> 16 & UCC_HDLC_UCCE_BSY) 675 dev->stats.rx_missed_errors++; 676 if (ucce >> 16 & UCC_HDLC_UCCE_TXE) 677 dev->stats.tx_errors++; 678 679 return IRQ_HANDLED; 680} 681 682static int uhdlc_ioctl(struct net_device *dev, struct if_settings *ifs) 683{ 684 const size_t size = sizeof(te1_settings); 685 te1_settings line; 686 struct ucc_hdlc_private *priv = netdev_priv(dev); 687 688 switch (ifs->type) { 689 case IF_GET_IFACE: 690 ifs->type = IF_IFACE_E1; 691 if (ifs->size < size) { 692 ifs->size = size; /* data size wanted */ 693 return -ENOBUFS; 694 } 695 memset(&line, 0, sizeof(line)); 696 line.clock_type = priv->clocking; 697 698 if (copy_to_user(ifs->ifs_ifsu.sync, &line, size)) 699 return -EFAULT; 700 return 0; 701 702 default: 703 return hdlc_ioctl(dev, ifs); 704 } 705} 706 707static int uhdlc_open(struct net_device *dev) 708{ 709 u32 cecr_subblock; 710 hdlc_device *hdlc = dev_to_hdlc(dev); 711 struct ucc_hdlc_private *priv = hdlc->priv; 712 struct ucc_tdm *utdm = priv->utdm; 713 int rc = 0; 714 715 if (priv->hdlc_busy != 1) { 716 if (request_irq(priv->ut_info->uf_info.irq, 717 ucc_hdlc_irq_handler, 0, "hdlc", priv)) 718 return -ENODEV; 719 720 cecr_subblock = ucc_fast_get_qe_cr_subblock( 721 priv->ut_info->uf_info.ucc_num); 722 723 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 724 QE_CR_PROTOCOL_UNSPECIFIED, 0); 725 726 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 727 728 /* Enable the TDM port */ 729 if (priv->tsa) 730 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); 731 732 priv->hdlc_busy = 1; 733 netif_device_attach(priv->ndev); 734 napi_enable(&priv->napi); 735 netdev_reset_queue(dev); 736 netif_start_queue(dev); 737 738 rc = hdlc_open(dev); 739 if (rc) 740 uhdlc_close(dev); 741 } 742 743 return rc; 744} 745 746static void uhdlc_memclean(struct ucc_hdlc_private *priv) 747{ 748 qe_muram_free(ioread16be(&priv->ucc_pram->riptr)); 749 qe_muram_free(ioread16be(&priv->ucc_pram->tiptr)); 750 751 if (priv->rx_bd_base) { 752 dma_free_coherent(priv->dev, 753 RX_BD_RING_LEN * sizeof(struct qe_bd), 754 priv->rx_bd_base, priv->dma_rx_bd); 755 756 priv->rx_bd_base = NULL; 757 priv->dma_rx_bd = 0; 758 } 759 760 if (priv->tx_bd_base) { 761 dma_free_coherent(priv->dev, 762 TX_BD_RING_LEN * sizeof(struct qe_bd), 763 priv->tx_bd_base, priv->dma_tx_bd); 764 765 priv->tx_bd_base = NULL; 766 priv->dma_tx_bd = 0; 767 } 768 769 if (priv->ucc_pram) { 770 qe_muram_free(priv->ucc_pram_offset); 771 priv->ucc_pram = NULL; 772 priv->ucc_pram_offset = 0; 773 } 774 775 kfree(priv->rx_skbuff); 776 priv->rx_skbuff = NULL; 777 778 kfree(priv->tx_skbuff); 779 priv->tx_skbuff = NULL; 780 781 if (priv->uf_regs) { 782 iounmap(priv->uf_regs); 783 priv->uf_regs = NULL; 784 } 785 786 if (priv->uccf) { 787 ucc_fast_free(priv->uccf); 788 priv->uccf = NULL; 789 } 790 791 if (priv->rx_buffer) { 792 dma_free_coherent(priv->dev, 793 RX_BD_RING_LEN * MAX_RX_BUF_LENGTH, 794 priv->rx_buffer, priv->dma_rx_addr); 795 priv->rx_buffer = NULL; 796 priv->dma_rx_addr = 0; 797 } 798 799 if (priv->tx_buffer) { 800 dma_free_coherent(priv->dev, 801 TX_BD_RING_LEN * MAX_RX_BUF_LENGTH, 802 priv->tx_buffer, priv->dma_tx_addr); 803 priv->tx_buffer = NULL; 804 priv->dma_tx_addr = 0; 805 } 806} 807 808static int uhdlc_close(struct net_device *dev) 809{ 810 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; 811 struct ucc_tdm *utdm = priv->utdm; 812 u32 cecr_subblock; 813 814 napi_disable(&priv->napi); 815 cecr_subblock = ucc_fast_get_qe_cr_subblock( 816 priv->ut_info->uf_info.ucc_num); 817 818 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 819 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 820 qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock, 821 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 822 823 if (priv->tsa) 824 qe_clrbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); 825 826 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 827 828 free_irq(priv->ut_info->uf_info.irq, priv); 829 netif_stop_queue(dev); 830 netdev_reset_queue(dev); 831 priv->hdlc_busy = 0; 832 833 hdlc_close(dev); 834 835 return 0; 836} 837 838static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding, 839 unsigned short parity) 840{ 841 struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; 842 843 if (encoding != ENCODING_NRZ && 844 encoding != ENCODING_NRZI) 845 return -EINVAL; 846 847 if (parity != PARITY_NONE && 848 parity != PARITY_CRC32_PR1_CCITT && 849 parity != PARITY_CRC16_PR0_CCITT && 850 parity != PARITY_CRC16_PR1_CCITT) 851 return -EINVAL; 852 853 priv->encoding = encoding; 854 priv->parity = parity; 855 856 return 0; 857} 858 859#ifdef CONFIG_PM 860static void store_clk_config(struct ucc_hdlc_private *priv) 861{ 862 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx; 863 864 /* store si clk */ 865 priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h); 866 priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l); 867 868 /* store si sync */ 869 priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr); 870 871 /* store ucc clk */ 872 memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32)); 873} 874 875static void resume_clk_config(struct ucc_hdlc_private *priv) 876{ 877 struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx; 878 879 memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32)); 880 881 iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h); 882 iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l); 883 884 iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr); 885} 886 887static int uhdlc_suspend(struct device *dev) 888{ 889 struct ucc_hdlc_private *priv = dev_get_drvdata(dev); 890 struct ucc_fast __iomem *uf_regs; 891 892 if (!priv) 893 return -EINVAL; 894 895 if (!netif_running(priv->ndev)) 896 return 0; 897 898 netif_device_detach(priv->ndev); 899 napi_disable(&priv->napi); 900 901 uf_regs = priv->uf_regs; 902 903 /* backup gumr guemr*/ 904 priv->gumr = ioread32be(&uf_regs->gumr); 905 priv->guemr = ioread8(&uf_regs->guemr); 906 907 priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak), 908 GFP_KERNEL); 909 if (!priv->ucc_pram_bak) 910 return -ENOMEM; 911 912 /* backup HDLC parameter */ 913 memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram, 914 sizeof(struct ucc_hdlc_param)); 915 916 /* store the clk configuration */ 917 store_clk_config(priv); 918 919 /* save power */ 920 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 921 922 return 0; 923} 924 925static int uhdlc_resume(struct device *dev) 926{ 927 struct ucc_hdlc_private *priv = dev_get_drvdata(dev); 928 struct ucc_tdm *utdm; 929 struct ucc_tdm_info *ut_info; 930 struct ucc_fast __iomem *uf_regs; 931 struct ucc_fast_private *uccf; 932 struct ucc_fast_info *uf_info; 933 int i; 934 u32 cecr_subblock; 935 u16 bd_status; 936 937 if (!priv) 938 return -EINVAL; 939 940 if (!netif_running(priv->ndev)) 941 return 0; 942 943 utdm = priv->utdm; 944 ut_info = priv->ut_info; 945 uf_info = &ut_info->uf_info; 946 uf_regs = priv->uf_regs; 947 uccf = priv->uccf; 948 949 /* restore gumr guemr */ 950 iowrite8(priv->guemr, &uf_regs->guemr); 951 iowrite32be(priv->gumr, &uf_regs->gumr); 952 953 /* Set Virtual Fifo registers */ 954 iowrite16be(uf_info->urfs, &uf_regs->urfs); 955 iowrite16be(uf_info->urfet, &uf_regs->urfet); 956 iowrite16be(uf_info->urfset, &uf_regs->urfset); 957 iowrite16be(uf_info->utfs, &uf_regs->utfs); 958 iowrite16be(uf_info->utfet, &uf_regs->utfet); 959 iowrite16be(uf_info->utftt, &uf_regs->utftt); 960 /* utfb, urfb are offsets from MURAM base */ 961 iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb); 962 iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb); 963 964 /* Rx Tx and sync clock routing */ 965 resume_clk_config(priv); 966 967 iowrite32be(uf_info->uccm_mask, &uf_regs->uccm); 968 iowrite32be(0xffffffff, &uf_regs->ucce); 969 970 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 971 972 /* rebuild SIRAM */ 973 if (priv->tsa) 974 ucc_tdm_init(priv->utdm, priv->ut_info); 975 976 /* Write to QE CECR, UCCx channel to Stop Transmission */ 977 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 978 qe_issue_cmd(QE_STOP_TX, cecr_subblock, 979 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 980 981 /* Set UPSMR normal mode */ 982 iowrite32be(0, &uf_regs->upsmr); 983 984 /* init parameter base */ 985 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); 986 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, 987 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); 988 989 priv->ucc_pram = (struct ucc_hdlc_param __iomem *) 990 qe_muram_addr(priv->ucc_pram_offset); 991 992 /* restore ucc parameter */ 993 memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak, 994 sizeof(struct ucc_hdlc_param)); 995 kfree(priv->ucc_pram_bak); 996 997 /* rebuild BD entry */ 998 for (i = 0; i < RX_BD_RING_LEN; i++) { 999 if (i < (RX_BD_RING_LEN - 1)) 1000 bd_status = R_E_S | R_I_S; 1001 else 1002 bd_status = R_E_S | R_I_S | R_W_S; 1003 1004 priv->rx_bd_base[i].status = cpu_to_be16(bd_status); 1005 priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH); 1006 } 1007 1008 for (i = 0; i < TX_BD_RING_LEN; i++) { 1009 if (i < (TX_BD_RING_LEN - 1)) 1010 bd_status = T_I_S | T_TC_S; 1011 else 1012 bd_status = T_I_S | T_TC_S | T_W_S; 1013 1014 priv->tx_bd_base[i].status = cpu_to_be16(bd_status); 1015 priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH); 1016 } 1017 dma_wmb(); 1018 1019 /* if hdlc is busy enable TX and RX */ 1020 if (priv->hdlc_busy == 1) { 1021 cecr_subblock = ucc_fast_get_qe_cr_subblock( 1022 priv->ut_info->uf_info.ucc_num); 1023 1024 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, 1025 (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); 1026 1027 ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); 1028 1029 /* Enable the TDM port */ 1030 if (priv->tsa) 1031 qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port); 1032 } 1033 1034 napi_enable(&priv->napi); 1035 netif_device_attach(priv->ndev); 1036 1037 return 0; 1038} 1039 1040static const struct dev_pm_ops uhdlc_pm_ops = { 1041 .suspend = uhdlc_suspend, 1042 .resume = uhdlc_resume, 1043 .freeze = uhdlc_suspend, 1044 .thaw = uhdlc_resume, 1045}; 1046 1047#define HDLC_PM_OPS (&uhdlc_pm_ops) 1048 1049#else 1050 1051#define HDLC_PM_OPS NULL 1052 1053#endif 1054static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1055{ 1056 netdev_err(ndev, "%s\n", __func__); 1057} 1058 1059static const struct net_device_ops uhdlc_ops = { 1060 .ndo_open = uhdlc_open, 1061 .ndo_stop = uhdlc_close, 1062 .ndo_start_xmit = hdlc_start_xmit, 1063 .ndo_siocwandev = uhdlc_ioctl, 1064 .ndo_tx_timeout = uhdlc_tx_timeout, 1065}; 1066 1067static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr) 1068{ 1069 struct device_node *np; 1070 struct platform_device *pdev; 1071 struct resource *res; 1072 static int siram_init_flag; 1073 int ret = 0; 1074 1075 np = of_find_compatible_node(NULL, NULL, name); 1076 if (!np) 1077 return -EINVAL; 1078 1079 pdev = of_find_device_by_node(np); 1080 if (!pdev) { 1081 pr_err("%pOFn: failed to lookup pdev\n", np); 1082 of_node_put(np); 1083 return -EINVAL; 1084 } 1085 1086 of_node_put(np); 1087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1088 if (!res) { 1089 ret = -EINVAL; 1090 goto error_put_device; 1091 } 1092 *ptr = ioremap(res->start, resource_size(res)); 1093 if (!*ptr) { 1094 ret = -ENOMEM; 1095 goto error_put_device; 1096 } 1097 1098 /* We've remapped the addresses, and we don't need the device any 1099 * more, so we should release it. 1100 */ 1101 put_device(&pdev->dev); 1102 1103 if (init_flag && siram_init_flag == 0) { 1104 memset_io(*ptr, 0, resource_size(res)); 1105 siram_init_flag = 1; 1106 } 1107 return 0; 1108 1109error_put_device: 1110 put_device(&pdev->dev); 1111 1112 return ret; 1113} 1114 1115static int ucc_hdlc_probe(struct platform_device *pdev) 1116{ 1117 struct device_node *np = pdev->dev.of_node; 1118 struct ucc_hdlc_private *uhdlc_priv = NULL; 1119 struct ucc_tdm_info *ut_info; 1120 struct ucc_tdm *utdm = NULL; 1121 struct resource res; 1122 struct net_device *dev; 1123 hdlc_device *hdlc; 1124 int ucc_num; 1125 const char *sprop; 1126 int ret; 1127 u32 val; 1128 1129 ret = of_property_read_u32_index(np, "cell-index", 0, &val); 1130 if (ret) { 1131 dev_err(&pdev->dev, "Invalid ucc property\n"); 1132 return -ENODEV; 1133 } 1134 1135 ucc_num = val - 1; 1136 if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) { 1137 dev_err(&pdev->dev, ": Invalid UCC num\n"); 1138 return -EINVAL; 1139 } 1140 1141 memcpy(&utdm_info[ucc_num], &utdm_primary_info, 1142 sizeof(utdm_primary_info)); 1143 1144 ut_info = &utdm_info[ucc_num]; 1145 ut_info->uf_info.ucc_num = ucc_num; 1146 1147 sprop = of_get_property(np, "rx-clock-name", NULL); 1148 if (sprop) { 1149 ut_info->uf_info.rx_clock = qe_clock_source(sprop); 1150 if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) || 1151 (ut_info->uf_info.rx_clock > QE_CLK24)) { 1152 dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); 1153 return -EINVAL; 1154 } 1155 } else { 1156 dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); 1157 return -EINVAL; 1158 } 1159 1160 sprop = of_get_property(np, "tx-clock-name", NULL); 1161 if (sprop) { 1162 ut_info->uf_info.tx_clock = qe_clock_source(sprop); 1163 if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) || 1164 (ut_info->uf_info.tx_clock > QE_CLK24)) { 1165 dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); 1166 return -EINVAL; 1167 } 1168 } else { 1169 dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); 1170 return -EINVAL; 1171 } 1172 1173 ret = of_address_to_resource(np, 0, &res); 1174 if (ret) 1175 return -EINVAL; 1176 1177 ut_info->uf_info.regs = res.start; 1178 ut_info->uf_info.irq = irq_of_parse_and_map(np, 0); 1179 1180 uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL); 1181 if (!uhdlc_priv) 1182 return -ENOMEM; 1183 1184 dev_set_drvdata(&pdev->dev, uhdlc_priv); 1185 uhdlc_priv->dev = &pdev->dev; 1186 uhdlc_priv->ut_info = ut_info; 1187 1188 uhdlc_priv->tsa = of_property_read_bool(np, "fsl,tdm-interface"); 1189 uhdlc_priv->loopback = of_property_read_bool(np, "fsl,ucc-internal-loopback"); 1190 uhdlc_priv->hdlc_bus = of_property_read_bool(np, "fsl,hdlc-bus"); 1191 1192 if (uhdlc_priv->tsa == 1) { 1193 utdm = kzalloc(sizeof(*utdm), GFP_KERNEL); 1194 if (!utdm) { 1195 ret = -ENOMEM; 1196 dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n"); 1197 goto free_uhdlc_priv; 1198 } 1199 uhdlc_priv->utdm = utdm; 1200 ret = ucc_of_parse_tdm(np, utdm, ut_info); 1201 if (ret) 1202 goto free_utdm; 1203 1204 ret = hdlc_map_iomem("fsl,t1040-qe-si", 0, 1205 (void __iomem **)&utdm->si_regs); 1206 if (ret) 1207 goto free_utdm; 1208 ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1, 1209 (void __iomem **)&utdm->siram); 1210 if (ret) 1211 goto unmap_si_regs; 1212 } 1213 1214 if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask)) 1215 uhdlc_priv->hmask = DEFAULT_ADDR_MASK; 1216 1217 ret = uhdlc_init(uhdlc_priv); 1218 if (ret) { 1219 dev_err(&pdev->dev, "Failed to init uhdlc\n"); 1220 goto undo_uhdlc_init; 1221 } 1222 1223 dev = alloc_hdlcdev(uhdlc_priv); 1224 if (!dev) { 1225 ret = -ENOMEM; 1226 pr_err("ucc_hdlc: unable to allocate memory\n"); 1227 goto undo_uhdlc_init; 1228 } 1229 1230 uhdlc_priv->ndev = dev; 1231 hdlc = dev_to_hdlc(dev); 1232 dev->tx_queue_len = 16; 1233 dev->netdev_ops = &uhdlc_ops; 1234 dev->watchdog_timeo = 2 * HZ; 1235 hdlc->attach = ucc_hdlc_attach; 1236 hdlc->xmit = ucc_hdlc_tx; 1237 netif_napi_add_weight(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32); 1238 if (register_hdlc_device(dev)) { 1239 ret = -ENOBUFS; 1240 pr_err("ucc_hdlc: unable to register hdlc device\n"); 1241 goto free_dev; 1242 } 1243 1244 return 0; 1245 1246free_dev: 1247 free_netdev(dev); 1248undo_uhdlc_init: 1249 if (utdm) 1250 iounmap(utdm->siram); 1251unmap_si_regs: 1252 if (utdm) 1253 iounmap(utdm->si_regs); 1254free_utdm: 1255 if (uhdlc_priv->tsa) 1256 kfree(utdm); 1257free_uhdlc_priv: 1258 kfree(uhdlc_priv); 1259 return ret; 1260} 1261 1262static void ucc_hdlc_remove(struct platform_device *pdev) 1263{ 1264 struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev); 1265 1266 uhdlc_memclean(priv); 1267 1268 if (priv->utdm->si_regs) { 1269 iounmap(priv->utdm->si_regs); 1270 priv->utdm->si_regs = NULL; 1271 } 1272 1273 if (priv->utdm->siram) { 1274 iounmap(priv->utdm->siram); 1275 priv->utdm->siram = NULL; 1276 } 1277 kfree(priv); 1278 1279 dev_info(&pdev->dev, "UCC based hdlc module removed\n"); 1280} 1281 1282static const struct of_device_id fsl_ucc_hdlc_of_match[] = { 1283 { 1284 .compatible = "fsl,ucc-hdlc", 1285 }, 1286 {}, 1287}; 1288 1289MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match); 1290 1291static struct platform_driver ucc_hdlc_driver = { 1292 .probe = ucc_hdlc_probe, 1293 .remove_new = ucc_hdlc_remove, 1294 .driver = { 1295 .name = DRV_NAME, 1296 .pm = HDLC_PM_OPS, 1297 .of_match_table = fsl_ucc_hdlc_of_match, 1298 }, 1299}; 1300 1301module_platform_driver(ucc_hdlc_driver); 1302MODULE_LICENSE("GPL"); 1303MODULE_DESCRIPTION(DRV_DESC); 1304