1/* SPDX-License-Identifier: GPL-2.0 */
2/* HWMON driver for Aquantia PHY
3 *
4 * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
5 * Author: Andrew Lunn <andrew@lunn.ch>
6 * Author: Heiner Kallweit <hkallweit1@gmail.com>
7 */
8
9#include <linux/device.h>
10#include <linux/phy.h>
11
12/* Vendor specific 1, MDIO_MMD_VEND1 */
13#define VEND1_GLOBAL_SC				0x0
14#define VEND1_GLOBAL_SC_SOFT_RESET		BIT(15)
15#define VEND1_GLOBAL_SC_LOW_POWER		BIT(11)
16
17#define VEND1_GLOBAL_FW_ID			0x0020
18#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
19#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
20
21#define VEND1_GLOBAL_MAILBOX_INTERFACE1			0x0200
22#define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE		BIT(15)
23#define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE		BIT(14)
24#define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET	BIT(12)
25#define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY		BIT(8)
26
27#define VEND1_GLOBAL_MAILBOX_INTERFACE2			0x0201
28#define VEND1_GLOBAL_MAILBOX_INTERFACE3			0x0202
29#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK	GENMASK(15, 0)
30#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16))
31#define VEND1_GLOBAL_MAILBOX_INTERFACE4			0x0203
32#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK	GENMASK(15, 2)
33#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))
34
35#define VEND1_GLOBAL_MAILBOX_INTERFACE5			0x0204
36#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK	GENMASK(15, 0)
37#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16))
38#define VEND1_GLOBAL_MAILBOX_INTERFACE6			0x0205
39#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK	GENMASK(15, 0)
40#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))
41
42/* The following registers all have similar layouts; first the registers... */
43#define VEND1_GLOBAL_CFG_10M			0x0310
44#define VEND1_GLOBAL_CFG_100M			0x031b
45#define VEND1_GLOBAL_CFG_1G			0x031c
46#define VEND1_GLOBAL_CFG_2_5G			0x031d
47#define VEND1_GLOBAL_CFG_5G			0x031e
48#define VEND1_GLOBAL_CFG_10G			0x031f
49/* ...and now the fields */
50#define VEND1_GLOBAL_CFG_SERDES_MODE		GENMASK(2, 0)
51#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI	0
52#define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII	3
53#define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII	4
54#define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G	6
55#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
56#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
57#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
58#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
59
60/* Vendor specific 1, MDIO_MMD_VEND2 */
61#define VEND1_GLOBAL_CONTROL2			0xc001
62#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST	BIT(15)
63#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD	BIT(6)
64#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL	BIT(0)
65
66#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
67#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
68#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
69#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
70#define VEND1_THERMAL_STAT1			0xc820
71#define VEND1_THERMAL_STAT2			0xc821
72#define VEND1_THERMAL_STAT2_VALID		BIT(0)
73#define VEND1_GENERAL_STAT1			0xc830
74#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)
75#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)
76#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)
77#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)
78
79#define VEND1_GLOBAL_GEN_STAT2			0xc831
80#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)
81
82#define VEND1_GLOBAL_RSVD_STAT1			0xc885
83#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
84#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
85
86#define VEND1_GLOBAL_RSVD_STAT9			0xc88d
87#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
88#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
89
90#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
91#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
92
93#define VEND1_GLOBAL_INT_STD_MASK		0xff00
94#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)
95#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)
96#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)
97#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)
98#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)
99#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)
100#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)
101#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)
102#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)
103#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)
104#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
105
106#define VEND1_GLOBAL_INT_VEND_MASK		0xff01
107#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)
108#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)
109#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)
110#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)
111#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)
112#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)
113#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
114#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
115
116#if IS_REACHABLE(CONFIG_HWMON)
117int aqr_hwmon_probe(struct phy_device *phydev);
118#else
119static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
120#endif
121
122int aqr_firmware_load(struct phy_device *phydev);
123