1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * DaVinci Ethernet Medium Access Controller 4 * 5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine 6 * 7 * Copyright (C) 2009 Texas Instruments. 8 * 9 * --------------------------------------------------------------------------- 10 * History: 11 * 0-5 A number of folks worked on this driver in bits and pieces but the major 12 * contribution came from Suraj Iyer and Anant Gole 13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions 14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features, 15 * PHY layer usage 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/sched.h> 21#include <linux/string.h> 22#include <linux/timer.h> 23#include <linux/errno.h> 24#include <linux/in.h> 25#include <linux/ioport.h> 26#include <linux/slab.h> 27#include <linux/mm.h> 28#include <linux/interrupt.h> 29#include <linux/init.h> 30#include <linux/netdevice.h> 31#include <linux/etherdevice.h> 32#include <linux/skbuff.h> 33#include <linux/ethtool.h> 34#include <linux/highmem.h> 35#include <linux/proc_fs.h> 36#include <linux/ctype.h> 37#include <linux/spinlock.h> 38#include <linux/dma-mapping.h> 39#include <linux/clk.h> 40#include <linux/platform_device.h> 41#include <linux/property.h> 42#include <linux/regmap.h> 43#include <linux/semaphore.h> 44#include <linux/phy.h> 45#include <linux/bitops.h> 46#include <linux/io.h> 47#include <linux/uaccess.h> 48#include <linux/pm_runtime.h> 49#include <linux/davinci_emac.h> 50#include <linux/of.h> 51#include <linux/of_mdio.h> 52#include <linux/of_net.h> 53#include <linux/mfd/syscon.h> 54 55#include <asm/irq.h> 56#include <asm/page.h> 57 58#include "cpsw.h" 59#include "davinci_cpdma.h" 60 61static int debug_level; 62module_param(debug_level, int, 0); 63MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 64 65/* Netif debug messages possible */ 66#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ 67 NETIF_MSG_PROBE | \ 68 NETIF_MSG_LINK | \ 69 NETIF_MSG_TIMER | \ 70 NETIF_MSG_IFDOWN | \ 71 NETIF_MSG_IFUP | \ 72 NETIF_MSG_RX_ERR | \ 73 NETIF_MSG_TX_ERR | \ 74 NETIF_MSG_TX_QUEUED | \ 75 NETIF_MSG_INTR | \ 76 NETIF_MSG_TX_DONE | \ 77 NETIF_MSG_RX_STATUS | \ 78 NETIF_MSG_PKTDATA | \ 79 NETIF_MSG_HW | \ 80 NETIF_MSG_WOL) 81 82/* version info */ 83#define EMAC_MAJOR_VERSION 6 84#define EMAC_MINOR_VERSION 1 85#define EMAC_MODULE_VERSION "6.1" 86MODULE_VERSION(EMAC_MODULE_VERSION); 87static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 88 89/* Configuration items */ 90#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ 91#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 92#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 93#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 94#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 95#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 96#define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ 97#define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ 98#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 99#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 100#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 101#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 102 103#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 104#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 105 106#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 107#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 108#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 109#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 110#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 111#define EMAC_DEF_RX_NUM_DESC (128) 112#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 113#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 114 115/* Buffer descriptor parameters */ 116#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 117#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 118 119/* EMAC register related defines */ 120#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 121#define EMAC_NUM_MULTICAST_BITS (64) 122#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 123#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 124#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 125#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 126#define EMAC_INT_MASK_CLEAR (0xFF) 127 128/* RX MBP register bit positions */ 129#define EMAC_RXMBP_PASSCRC_MASK BIT(30) 130#define EMAC_RXMBP_QOSEN_MASK BIT(29) 131#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 132#define EMAC_RXMBP_CMFEN_MASK BIT(24) 133#define EMAC_RXMBP_CSFEN_MASK BIT(23) 134#define EMAC_RXMBP_CEFEN_MASK BIT(22) 135#define EMAC_RXMBP_CAFEN_MASK BIT(21) 136#define EMAC_RXMBP_PROMCH_SHIFT (16) 137#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 138#define EMAC_RXMBP_BROADEN_MASK BIT(13) 139#define EMAC_RXMBP_BROADCH_SHIFT (8) 140#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 141#define EMAC_RXMBP_MULTIEN_MASK BIT(5) 142#define EMAC_RXMBP_MULTICH_SHIFT (0) 143#define EMAC_RXMBP_MULTICH_MASK (0x7) 144#define EMAC_RXMBP_CHMASK (0x7) 145 146/* EMAC register definitions/bit maps used */ 147# define EMAC_MBP_RXPROMISC (0x00200000) 148# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 149# define EMAC_MBP_RXBCAST (0x00002000) 150# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 151# define EMAC_MBP_RXMCAST (0x00000020) 152# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 153 154/* EMAC mac_control register */ 155#define EMAC_MACCONTROL_TXPTYPE BIT(9) 156#define EMAC_MACCONTROL_TXPACEEN BIT(6) 157#define EMAC_MACCONTROL_GMIIEN BIT(5) 158#define EMAC_MACCONTROL_GIGABITEN BIT(7) 159#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 160#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 161 162/* GIGABIT MODE related bits */ 163#define EMAC_DM646X_MACCONTORL_GIG BIT(7) 164#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 165 166/* EMAC mac_status register */ 167#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 168#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 169#define EMAC_MACSTATUS_TXERRCH_MASK (0x70000) 170#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 171#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 172#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 173#define EMAC_MACSTATUS_RXERRCH_MASK (0x700) 174#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 175 176/* EMAC RX register masks */ 177#define EMAC_RX_MAX_LEN_MASK (0xFFFF) 178#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 179 180/* MAC_IN_VECTOR (0x180) register bit fields */ 181#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 182#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 183#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 184#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 185 186/** NOTE:: For DM646x the IN_VECTOR has changed */ 187#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 188#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 189#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 190#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 191 192/* CPPI bit positions */ 193#define EMAC_CPPI_SOP_BIT BIT(31) 194#define EMAC_CPPI_EOP_BIT BIT(30) 195#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 196#define EMAC_CPPI_EOQ_BIT BIT(28) 197#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 198#define EMAC_CPPI_PASS_CRC_BIT BIT(26) 199#define EMAC_RX_BD_BUF_SIZE (0xFFFF) 200#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 201#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 202 203/* Max hardware defines */ 204#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 205#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 206 207/* EMAC Peripheral Device Register Memory Layout structure */ 208#define EMAC_MACINVECTOR 0x90 209 210#define EMAC_DM646X_MACEOIVECTOR 0x94 211 212#define EMAC_MACINTSTATRAW 0xB0 213#define EMAC_MACINTSTATMASKED 0xB4 214#define EMAC_MACINTMASKSET 0xB8 215#define EMAC_MACINTMASKCLEAR 0xBC 216 217#define EMAC_RXMBPENABLE 0x100 218#define EMAC_RXUNICASTSET 0x104 219#define EMAC_RXUNICASTCLEAR 0x108 220#define EMAC_RXMAXLEN 0x10C 221#define EMAC_RXBUFFEROFFSET 0x110 222#define EMAC_RXFILTERLOWTHRESH 0x114 223 224#define EMAC_MACCONTROL 0x160 225#define EMAC_MACSTATUS 0x164 226#define EMAC_EMCONTROL 0x168 227#define EMAC_FIFOCONTROL 0x16C 228#define EMAC_MACCONFIG 0x170 229#define EMAC_SOFTRESET 0x174 230#define EMAC_MACSRCADDRLO 0x1D0 231#define EMAC_MACSRCADDRHI 0x1D4 232#define EMAC_MACHASH1 0x1D8 233#define EMAC_MACHASH2 0x1DC 234#define EMAC_MACADDRLO 0x500 235#define EMAC_MACADDRHI 0x504 236#define EMAC_MACINDEX 0x508 237 238/* EMAC statistics registers */ 239#define EMAC_RXGOODFRAMES 0x200 240#define EMAC_RXBCASTFRAMES 0x204 241#define EMAC_RXMCASTFRAMES 0x208 242#define EMAC_RXPAUSEFRAMES 0x20C 243#define EMAC_RXCRCERRORS 0x210 244#define EMAC_RXALIGNCODEERRORS 0x214 245#define EMAC_RXOVERSIZED 0x218 246#define EMAC_RXJABBER 0x21C 247#define EMAC_RXUNDERSIZED 0x220 248#define EMAC_RXFRAGMENTS 0x224 249#define EMAC_RXFILTERED 0x228 250#define EMAC_RXQOSFILTERED 0x22C 251#define EMAC_RXOCTETS 0x230 252#define EMAC_TXGOODFRAMES 0x234 253#define EMAC_TXBCASTFRAMES 0x238 254#define EMAC_TXMCASTFRAMES 0x23C 255#define EMAC_TXPAUSEFRAMES 0x240 256#define EMAC_TXDEFERRED 0x244 257#define EMAC_TXCOLLISION 0x248 258#define EMAC_TXSINGLECOLL 0x24C 259#define EMAC_TXMULTICOLL 0x250 260#define EMAC_TXEXCESSIVECOLL 0x254 261#define EMAC_TXLATECOLL 0x258 262#define EMAC_TXUNDERRUN 0x25C 263#define EMAC_TXCARRIERSENSE 0x260 264#define EMAC_TXOCTETS 0x264 265#define EMAC_NETOCTETS 0x280 266#define EMAC_RXSOFOVERRUNS 0x284 267#define EMAC_RXMOFOVERRUNS 0x288 268#define EMAC_RXDMAOVERRUNS 0x28C 269 270/* EMAC DM644x control registers */ 271#define EMAC_CTRL_EWCTL (0x4) 272#define EMAC_CTRL_EWINTTCNT (0x8) 273 274/* EMAC DM644x control module masks */ 275#define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF 276#define EMAC_DM644X_INTMIN_INTVL 0x1 277#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 278 279/* EMAC DM646X control module registers */ 280#define EMAC_DM646X_CMINTCTRL 0x0C 281#define EMAC_DM646X_CMRXINTEN 0x14 282#define EMAC_DM646X_CMTXINTEN 0x18 283#define EMAC_DM646X_CMRXINTMAX 0x70 284#define EMAC_DM646X_CMTXINTMAX 0x74 285 286/* EMAC DM646X control module masks */ 287#define EMAC_DM646X_INTPACEEN (0x3 << 16) 288#define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) 289#define EMAC_DM646X_CMINTMAX_CNT 63 290#define EMAC_DM646X_CMINTMIN_CNT 2 291#define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) 292#define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) 293 294 295/* EMAC EOI codes for C0 */ 296#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 297#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 298 299/* EMAC Stats Clear Mask */ 300#define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 301 302/* emac_priv: EMAC private data structure 303 * 304 * EMAC adapter private data structure 305 */ 306struct emac_priv { 307 u32 msg_enable; 308 struct net_device *ndev; 309 struct platform_device *pdev; 310 struct napi_struct napi; 311 char mac_addr[6]; 312 void __iomem *remap_addr; 313 u32 emac_base_phys; 314 void __iomem *emac_base; 315 void __iomem *ctrl_base; 316 struct cpdma_ctlr *dma; 317 struct cpdma_chan *txchan; 318 struct cpdma_chan *rxchan; 319 u32 link; /* 1=link on, 0=link off */ 320 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 321 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 322 u32 rx_buf_size; 323 u32 isr_count; 324 u32 coal_intvl; 325 u32 bus_freq_mhz; 326 u8 rmii_en; 327 u8 version; 328 u32 mac_hash1; 329 u32 mac_hash2; 330 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 331 u32 rx_addr_type; 332 const char *phy_id; 333 struct device_node *phy_node; 334 spinlock_t lock; 335 /*platform specific members*/ 336 void (*int_enable) (void); 337 void (*int_disable) (void); 338}; 339 340/* EMAC TX Host Error description strings */ 341static char *emac_txhost_errcodes[16] = { 342 "No error", "SOP error", "Ownership bit not set in SOP buffer", 343 "Zero Next Buffer Descriptor Pointer Without EOP", 344 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", 345 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 346 "Reserved", "Reserved", "Reserved", "Reserved" 347}; 348 349/* EMAC RX Host Error description strings */ 350static char *emac_rxhost_errcodes[16] = { 351 "No error", "Reserved", "Ownership bit not set in input buffer", 352 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", 353 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 354 "Reserved", "Reserved", "Reserved", "Reserved" 355}; 356 357/* Helper macros */ 358#define emac_read(reg) ioread32(priv->emac_base + (reg)) 359#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) 360 361#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 362#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 363 364/** 365 * emac_get_drvinfo - Get EMAC driver information 366 * @ndev: The DaVinci EMAC network adapter 367 * @info: ethtool info structure containing name and version 368 * 369 * Returns EMAC driver information (name and version) 370 * 371 */ 372static void emac_get_drvinfo(struct net_device *ndev, 373 struct ethtool_drvinfo *info) 374{ 375 strscpy(info->driver, emac_version_string, sizeof(info->driver)); 376 strscpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version)); 377} 378 379/** 380 * emac_get_coalesce - Get interrupt coalesce settings for this device 381 * @ndev : The DaVinci EMAC network adapter 382 * @coal : ethtool coalesce settings structure 383 * @kernel_coal: ethtool CQE mode setting structure 384 * @extack: extack for reporting error messages 385 * 386 * Fetch the current interrupt coalesce settings 387 * 388 */ 389static int emac_get_coalesce(struct net_device *ndev, 390 struct ethtool_coalesce *coal, 391 struct kernel_ethtool_coalesce *kernel_coal, 392 struct netlink_ext_ack *extack) 393{ 394 struct emac_priv *priv = netdev_priv(ndev); 395 396 coal->rx_coalesce_usecs = priv->coal_intvl; 397 return 0; 398 399} 400 401/** 402 * emac_set_coalesce - Set interrupt coalesce settings for this device 403 * @ndev : The DaVinci EMAC network adapter 404 * @coal : ethtool coalesce settings structure 405 * @kernel_coal: ethtool CQE mode setting structure 406 * @extack: extack for reporting error messages 407 * 408 * Set interrupt coalesce parameters 409 * 410 */ 411static int emac_set_coalesce(struct net_device *ndev, 412 struct ethtool_coalesce *coal, 413 struct kernel_ethtool_coalesce *kernel_coal, 414 struct netlink_ext_ack *extack) 415{ 416 struct emac_priv *priv = netdev_priv(ndev); 417 u32 int_ctrl, num_interrupts = 0; 418 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; 419 420 if (!coal->rx_coalesce_usecs) { 421 priv->coal_intvl = 0; 422 423 switch (priv->version) { 424 case EMAC_VERSION_2: 425 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0); 426 break; 427 default: 428 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0); 429 break; 430 } 431 432 return 0; 433 } 434 435 coal_intvl = coal->rx_coalesce_usecs; 436 437 switch (priv->version) { 438 case EMAC_VERSION_2: 439 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); 440 prescale = priv->bus_freq_mhz * 4; 441 442 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) 443 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; 444 445 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { 446 /* 447 * Interrupt pacer works with 4us Pulse, we can 448 * throttle further by dilating the 4us pulse. 449 */ 450 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; 451 452 if (addnl_dvdr > 1) { 453 prescale *= addnl_dvdr; 454 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL 455 * addnl_dvdr)) 456 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL 457 * addnl_dvdr); 458 } else { 459 addnl_dvdr = 1; 460 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; 461 } 462 } 463 464 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 465 466 int_ctrl |= EMAC_DM646X_INTPACEEN; 467 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); 468 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); 469 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); 470 471 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); 472 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); 473 474 break; 475 default: 476 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); 477 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); 478 prescale = coal_intvl * priv->bus_freq_mhz; 479 if (prescale > EMAC_DM644X_EWINTCNT_MASK) { 480 prescale = EMAC_DM644X_EWINTCNT_MASK; 481 coal_intvl = prescale / priv->bus_freq_mhz; 482 } 483 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); 484 485 break; 486 } 487 488 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); 489 priv->coal_intvl = coal_intvl; 490 491 return 0; 492 493} 494 495 496/* ethtool_ops: DaVinci EMAC Ethtool structure 497 * 498 * Ethtool support for EMAC adapter 499 */ 500static const struct ethtool_ops ethtool_ops = { 501 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, 502 .get_drvinfo = emac_get_drvinfo, 503 .get_link = ethtool_op_get_link, 504 .get_coalesce = emac_get_coalesce, 505 .set_coalesce = emac_set_coalesce, 506 .get_ts_info = ethtool_op_get_ts_info, 507 .get_link_ksettings = phy_ethtool_get_link_ksettings, 508 .set_link_ksettings = phy_ethtool_set_link_ksettings, 509}; 510 511/** 512 * emac_update_phystatus - Update Phy status 513 * @priv: The DaVinci EMAC private adapter structure 514 * 515 * Updates phy status and takes action for network queue if required 516 * based upon link status 517 * 518 */ 519static void emac_update_phystatus(struct emac_priv *priv) 520{ 521 u32 mac_control; 522 u32 new_duplex; 523 u32 cur_duplex; 524 struct net_device *ndev = priv->ndev; 525 526 mac_control = emac_read(EMAC_MACCONTROL); 527 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 528 DUPLEX_FULL : DUPLEX_HALF; 529 if (ndev->phydev) 530 new_duplex = ndev->phydev->duplex; 531 else 532 new_duplex = DUPLEX_FULL; 533 534 /* We get called only if link has changed (speed/duplex/status) */ 535 if ((priv->link) && (new_duplex != cur_duplex)) { 536 priv->duplex = new_duplex; 537 if (DUPLEX_FULL == priv->duplex) 538 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); 539 else 540 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); 541 } 542 543 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { 544 mac_control = emac_read(EMAC_MACCONTROL); 545 mac_control |= (EMAC_DM646X_MACCONTORL_GIG | 546 EMAC_DM646X_MACCONTORL_GIGFORCE); 547 } else { 548 /* Clear the GIG bit and GIGFORCE bit */ 549 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | 550 EMAC_DM646X_MACCONTORL_GIG); 551 552 if (priv->rmii_en && (priv->speed == SPEED_100)) 553 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; 554 else 555 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; 556 } 557 558 /* Update mac_control if changed */ 559 emac_write(EMAC_MACCONTROL, mac_control); 560 561 if (priv->link) { 562 /* link ON */ 563 if (!netif_carrier_ok(ndev)) 564 netif_carrier_on(ndev); 565 /* reactivate the transmit queue if it is stopped */ 566 if (netif_running(ndev) && netif_queue_stopped(ndev)) 567 netif_wake_queue(ndev); 568 } else { 569 /* link OFF */ 570 if (netif_carrier_ok(ndev)) 571 netif_carrier_off(ndev); 572 if (!netif_queue_stopped(ndev)) 573 netif_stop_queue(ndev); 574 } 575} 576 577/** 578 * hash_get - Calculate hash value from mac address 579 * @addr: mac address to delete from hash table 580 * 581 * Calculates hash value from mac address 582 * 583 */ 584static u32 hash_get(u8 *addr) 585{ 586 u32 hash; 587 u8 tmpval; 588 int cnt; 589 hash = 0; 590 591 for (cnt = 0; cnt < 2; cnt++) { 592 tmpval = *addr++; 593 hash ^= (tmpval >> 2) ^ (tmpval << 4); 594 tmpval = *addr++; 595 hash ^= (tmpval >> 4) ^ (tmpval << 2); 596 tmpval = *addr++; 597 hash ^= (tmpval >> 6) ^ (tmpval); 598 } 599 600 return hash & 0x3F; 601} 602 603/** 604 * emac_hash_add - Hash function to add mac addr from hash table 605 * @priv: The DaVinci EMAC private adapter structure 606 * @mac_addr: mac address to delete from hash table 607 * 608 * Adds mac address to the internal hash table 609 * 610 */ 611static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr) 612{ 613 struct device *emac_dev = &priv->ndev->dev; 614 u32 rc = 0; 615 u32 hash_bit; 616 u32 hash_value = hash_get(mac_addr); 617 618 if (hash_value >= EMAC_NUM_MULTICAST_BITS) { 619 if (netif_msg_drv(priv)) { 620 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\ 621 "Hash %08x, should not be greater than %08x", 622 hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); 623 } 624 return -1; 625 } 626 627 /* set the hash bit only if not previously set */ 628 if (priv->multicast_hash_cnt[hash_value] == 0) { 629 rc = 1; /* hash value changed */ 630 if (hash_value < 32) { 631 hash_bit = BIT(hash_value); 632 priv->mac_hash1 |= hash_bit; 633 } else { 634 hash_bit = BIT((hash_value - 32)); 635 priv->mac_hash2 |= hash_bit; 636 } 637 } 638 639 /* incr counter for num of mcast addr's mapped to "this" hash bit */ 640 ++priv->multicast_hash_cnt[hash_value]; 641 642 return rc; 643} 644 645/** 646 * emac_hash_del - Hash function to delete mac addr from hash table 647 * @priv: The DaVinci EMAC private adapter structure 648 * @mac_addr: mac address to delete from hash table 649 * 650 * Removes mac address from the internal hash table 651 * 652 */ 653static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr) 654{ 655 u32 hash_value; 656 u32 hash_bit; 657 658 hash_value = hash_get(mac_addr); 659 if (priv->multicast_hash_cnt[hash_value] > 0) { 660 /* dec cntr for num of mcast addr's mapped to this hash bit */ 661 --priv->multicast_hash_cnt[hash_value]; 662 } 663 664 /* if counter still > 0, at least one multicast address refers 665 * to this hash bit. so return 0 */ 666 if (priv->multicast_hash_cnt[hash_value] > 0) 667 return 0; 668 669 if (hash_value < 32) { 670 hash_bit = BIT(hash_value); 671 priv->mac_hash1 &= ~hash_bit; 672 } else { 673 hash_bit = BIT((hash_value - 32)); 674 priv->mac_hash2 &= ~hash_bit; 675 } 676 677 /* return 1 to indicate change in mac_hash registers reqd */ 678 return 1; 679} 680 681/* EMAC multicast operation */ 682#define EMAC_MULTICAST_ADD 0 683#define EMAC_MULTICAST_DEL 1 684#define EMAC_ALL_MULTI_SET 2 685#define EMAC_ALL_MULTI_CLR 3 686 687/** 688 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) 689 * @priv: The DaVinci EMAC private adapter structure 690 * @action: multicast operation to perform 691 * @mac_addr: mac address to set 692 * 693 * Set multicast addresses in EMAC adapter - internal function 694 * 695 */ 696static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) 697{ 698 struct device *emac_dev = &priv->ndev->dev; 699 int update = -1; 700 701 switch (action) { 702 case EMAC_MULTICAST_ADD: 703 update = emac_hash_add(priv, mac_addr); 704 break; 705 case EMAC_MULTICAST_DEL: 706 update = emac_hash_del(priv, mac_addr); 707 break; 708 case EMAC_ALL_MULTI_SET: 709 update = 1; 710 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; 711 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; 712 break; 713 case EMAC_ALL_MULTI_CLR: 714 update = 1; 715 priv->mac_hash1 = 0; 716 priv->mac_hash2 = 0; 717 memset(&(priv->multicast_hash_cnt[0]), 0, 718 sizeof(priv->multicast_hash_cnt[0]) * 719 EMAC_NUM_MULTICAST_BITS); 720 break; 721 default: 722 if (netif_msg_drv(priv)) 723 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ 724 ": bad operation %d", action); 725 break; 726 } 727 728 /* write to the hardware only if the register status chances */ 729 if (update > 0) { 730 emac_write(EMAC_MACHASH1, priv->mac_hash1); 731 emac_write(EMAC_MACHASH2, priv->mac_hash2); 732 } 733} 734 735/** 736 * emac_dev_mcast_set - Set multicast address in the EMAC adapter 737 * @ndev: The DaVinci EMAC network adapter 738 * 739 * Set multicast addresses in EMAC adapter 740 * 741 */ 742static void emac_dev_mcast_set(struct net_device *ndev) 743{ 744 u32 mbp_enable; 745 struct emac_priv *priv = netdev_priv(ndev); 746 747 mbp_enable = emac_read(EMAC_RXMBPENABLE); 748 if (ndev->flags & IFF_PROMISC) { 749 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); 750 mbp_enable |= (EMAC_MBP_RXPROMISC); 751 } else { 752 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 753 if ((ndev->flags & IFF_ALLMULTI) || 754 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { 755 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 756 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 757 } else if (!netdev_mc_empty(ndev)) { 758 struct netdev_hw_addr *ha; 759 760 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 761 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 762 /* program multicast address list into EMAC hardware */ 763 netdev_for_each_mc_addr(ha, ndev) { 764 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 765 (u8 *) ha->addr); 766 } 767 } else { 768 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 769 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 770 } 771 } 772 /* Set mbp config register */ 773 emac_write(EMAC_RXMBPENABLE, mbp_enable); 774} 775 776/************************************************************************* 777 * EMAC Hardware manipulation 778 *************************************************************************/ 779 780/** 781 * emac_int_disable - Disable EMAC module interrupt (from adapter) 782 * @priv: The DaVinci EMAC private adapter structure 783 * 784 * Disable EMAC interrupt on the adapter 785 * 786 */ 787static void emac_int_disable(struct emac_priv *priv) 788{ 789 if (priv->version == EMAC_VERSION_2) { 790 unsigned long flags; 791 792 local_irq_save(flags); 793 794 /* Program C0_Int_En to zero to turn off 795 * interrupts to the CPU */ 796 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 797 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 798 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 799 if (priv->int_disable) 800 priv->int_disable(); 801 802 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 803 804 /* ack rxen only then a new pulse will be generated */ 805 emac_write(EMAC_DM646X_MACEOIVECTOR, 806 EMAC_DM646X_MAC_EOI_C0_RXEN); 807 808 /* ack txen- only then a new pulse will be generated */ 809 emac_write(EMAC_DM646X_MACEOIVECTOR, 810 EMAC_DM646X_MAC_EOI_C0_TXEN); 811 812 local_irq_restore(flags); 813 814 } else { 815 /* Set DM644x control registers for interrupt control */ 816 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); 817 } 818} 819 820/** 821 * emac_int_enable - Enable EMAC module interrupt (from adapter) 822 * @priv: The DaVinci EMAC private adapter structure 823 * 824 * Enable EMAC interrupt on the adapter 825 * 826 */ 827static void emac_int_enable(struct emac_priv *priv) 828{ 829 if (priv->version == EMAC_VERSION_2) { 830 if (priv->int_enable) 831 priv->int_enable(); 832 833 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 834 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 835 836 /* In addition to turning on interrupt Enable, we need 837 * ack by writing appropriate values to the EOI 838 * register */ 839 840 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 841 } else { 842 /* Set DM644x control registers for interrupt control */ 843 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); 844 } 845} 846 847/** 848 * emac_irq - EMAC interrupt handler 849 * @irq: interrupt number 850 * @dev_id: EMAC network adapter data structure ptr 851 * 852 * EMAC Interrupt handler - we only schedule NAPI and not process any packets 853 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function 854 * 855 * Returns interrupt handled condition 856 */ 857static irqreturn_t emac_irq(int irq, void *dev_id) 858{ 859 struct net_device *ndev = (struct net_device *)dev_id; 860 struct emac_priv *priv = netdev_priv(ndev); 861 862 ++priv->isr_count; 863 if (likely(netif_running(priv->ndev))) { 864 emac_int_disable(priv); 865 napi_schedule(&priv->napi); 866 } else { 867 /* we are closing down, so dont process anything */ 868 } 869 return IRQ_HANDLED; 870} 871 872static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) 873{ 874 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); 875 if (WARN_ON(!skb)) 876 return NULL; 877 skb_reserve(skb, NET_IP_ALIGN); 878 return skb; 879} 880 881static void emac_rx_handler(void *token, int len, int status) 882{ 883 struct sk_buff *skb = token; 884 struct net_device *ndev = skb->dev; 885 struct emac_priv *priv = netdev_priv(ndev); 886 struct device *emac_dev = &ndev->dev; 887 int ret; 888 889 /* free and bail if we are shutting down */ 890 if (unlikely(!netif_running(ndev))) { 891 dev_kfree_skb_any(skb); 892 return; 893 } 894 895 /* recycle on receive error */ 896 if (status < 0) { 897 ndev->stats.rx_errors++; 898 goto recycle; 899 } 900 901 /* feed received packet up the stack */ 902 skb_put(skb, len); 903 skb->protocol = eth_type_trans(skb, ndev); 904 netif_receive_skb(skb); 905 ndev->stats.rx_bytes += len; 906 ndev->stats.rx_packets++; 907 908 /* alloc a new packet for receive */ 909 skb = emac_rx_alloc(priv); 910 if (!skb) { 911 if (netif_msg_rx_err(priv) && net_ratelimit()) 912 dev_err(emac_dev, "failed rx buffer alloc\n"); 913 return; 914 } 915 916recycle: 917 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 918 skb_tailroom(skb), 0); 919 920 WARN_ON(ret == -ENOMEM); 921 if (unlikely(ret < 0)) 922 dev_kfree_skb_any(skb); 923} 924 925static void emac_tx_handler(void *token, int len, int status) 926{ 927 struct sk_buff *skb = token; 928 struct net_device *ndev = skb->dev; 929 930 /* Check whether the queue is stopped due to stalled tx dma, if the 931 * queue is stopped then start the queue as we have free desc for tx 932 */ 933 if (unlikely(netif_queue_stopped(ndev))) 934 netif_wake_queue(ndev); 935 ndev->stats.tx_packets++; 936 ndev->stats.tx_bytes += len; 937 dev_kfree_skb_any(skb); 938} 939 940/** 941 * emac_dev_xmit - EMAC Transmit function 942 * @skb: SKB pointer 943 * @ndev: The DaVinci EMAC network adapter 944 * 945 * Called by the system to transmit a packet - we queue the packet in 946 * EMAC hardware transmit queue 947 * 948 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) 949 */ 950static netdev_tx_t emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) 951{ 952 struct device *emac_dev = &ndev->dev; 953 int ret_code; 954 struct emac_priv *priv = netdev_priv(ndev); 955 956 /* If no link, return */ 957 if (unlikely(!priv->link)) { 958 if (netif_msg_tx_err(priv) && net_ratelimit()) 959 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 960 goto fail_tx; 961 } 962 963 ret_code = skb_put_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); 964 if (unlikely(ret_code < 0)) { 965 if (netif_msg_tx_err(priv) && net_ratelimit()) 966 dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); 967 goto fail_tx; 968 } 969 970 skb_tx_timestamp(skb); 971 972 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, 973 0); 974 if (unlikely(ret_code != 0)) { 975 if (netif_msg_tx_err(priv) && net_ratelimit()) 976 dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); 977 goto fail_tx; 978 } 979 980 /* If there is no more tx desc left free then we need to 981 * tell the kernel to stop sending us tx frames. 982 */ 983 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan))) 984 netif_stop_queue(ndev); 985 986 return NETDEV_TX_OK; 987 988fail_tx: 989 ndev->stats.tx_dropped++; 990 netif_stop_queue(ndev); 991 return NETDEV_TX_BUSY; 992} 993 994/** 995 * emac_dev_tx_timeout - EMAC Transmit timeout function 996 * @ndev: The DaVinci EMAC network adapter 997 * @txqueue: the index of the hung transmit queue 998 * 999 * Called when system detects that a skb timeout period has expired 1000 * potentially due to a fault in the adapter in not being able to send 1001 * it out on the wire. We teardown the TX channel assuming a hardware 1002 * error and re-initialize the TX channel for hardware operation 1003 * 1004 */ 1005static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1006{ 1007 struct emac_priv *priv = netdev_priv(ndev); 1008 struct device *emac_dev = &ndev->dev; 1009 1010 if (netif_msg_tx_err(priv)) 1011 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1012 1013 ndev->stats.tx_errors++; 1014 emac_int_disable(priv); 1015 cpdma_chan_stop(priv->txchan); 1016 cpdma_chan_start(priv->txchan); 1017 emac_int_enable(priv); 1018} 1019 1020/** 1021 * emac_set_type0addr - Set EMAC Type0 mac address 1022 * @priv: The DaVinci EMAC private adapter structure 1023 * @ch: RX channel number 1024 * @mac_addr: MAC address to set in device 1025 * 1026 * Called internally to set Type0 mac address of the adapter (Device) 1027 * 1028 * Returns success (0) or appropriate error code (none as of now) 1029 */ 1030static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1031{ 1032 u32 val; 1033 val = ((mac_addr[5] << 8) | (mac_addr[4])); 1034 emac_write(EMAC_MACSRCADDRLO, val); 1035 1036 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1037 (mac_addr[1] << 8) | (mac_addr[0])); 1038 emac_write(EMAC_MACSRCADDRHI, val); 1039 val = emac_read(EMAC_RXUNICASTSET); 1040 val |= BIT(ch); 1041 emac_write(EMAC_RXUNICASTSET, val); 1042 val = emac_read(EMAC_RXUNICASTCLEAR); 1043 val &= ~BIT(ch); 1044 emac_write(EMAC_RXUNICASTCLEAR, val); 1045} 1046 1047/** 1048 * emac_set_type1addr - Set EMAC Type1 mac address 1049 * @priv: The DaVinci EMAC private adapter structure 1050 * @ch: RX channel number 1051 * @mac_addr: MAC address to set in device 1052 * 1053 * Called internally to set Type1 mac address of the adapter (Device) 1054 * 1055 * Returns success (0) or appropriate error code (none as of now) 1056 */ 1057static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1058{ 1059 u32 val; 1060 emac_write(EMAC_MACINDEX, ch); 1061 val = ((mac_addr[5] << 8) | mac_addr[4]); 1062 emac_write(EMAC_MACADDRLO, val); 1063 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1064 (mac_addr[1] << 8) | (mac_addr[0])); 1065 emac_write(EMAC_MACADDRHI, val); 1066 emac_set_type0addr(priv, ch, mac_addr); 1067} 1068 1069/** 1070 * emac_set_type2addr - Set EMAC Type2 mac address 1071 * @priv: The DaVinci EMAC private adapter structure 1072 * @ch: RX channel number 1073 * @mac_addr: MAC address to set in device 1074 * @index: index into RX address entries 1075 * @match: match parameter for RX address matching logic 1076 * 1077 * Called internally to set Type2 mac address of the adapter (Device) 1078 * 1079 * Returns success (0) or appropriate error code (none as of now) 1080 */ 1081static void emac_set_type2addr(struct emac_priv *priv, u32 ch, 1082 char *mac_addr, int index, int match) 1083{ 1084 u32 val; 1085 emac_write(EMAC_MACINDEX, index); 1086 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1087 (mac_addr[1] << 8) | (mac_addr[0])); 1088 emac_write(EMAC_MACADDRHI, val); 1089 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ 1090 (match << 19) | BIT(20)); 1091 emac_write(EMAC_MACADDRLO, val); 1092 emac_set_type0addr(priv, ch, mac_addr); 1093} 1094 1095/** 1096 * emac_setmac - Set mac address in the adapter (internal function) 1097 * @priv: The DaVinci EMAC private adapter structure 1098 * @ch: RX channel number 1099 * @mac_addr: MAC address to set in device 1100 * 1101 * Called internally to set the mac address of the adapter (Device) 1102 * 1103 * Returns success (0) or appropriate error code (none as of now) 1104 */ 1105static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) 1106{ 1107 struct device *emac_dev = &priv->ndev->dev; 1108 1109 if (priv->rx_addr_type == 0) { 1110 emac_set_type0addr(priv, ch, mac_addr); 1111 } else if (priv->rx_addr_type == 1) { 1112 u32 cnt; 1113 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) 1114 emac_set_type1addr(priv, ch, mac_addr); 1115 } else if (priv->rx_addr_type == 2) { 1116 emac_set_type2addr(priv, ch, mac_addr, ch, 1); 1117 emac_set_type0addr(priv, ch, mac_addr); 1118 } else { 1119 if (netif_msg_drv(priv)) 1120 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); 1121 } 1122} 1123 1124/** 1125 * emac_dev_setmac_addr - Set mac address in the adapter 1126 * @ndev: The DaVinci EMAC network adapter 1127 * @addr: MAC address to set in device 1128 * 1129 * Called by the system to set the mac address of the adapter (Device) 1130 * 1131 * Returns success (0) or appropriate error code (none as of now) 1132 */ 1133static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1134{ 1135 struct emac_priv *priv = netdev_priv(ndev); 1136 struct device *emac_dev = &priv->ndev->dev; 1137 struct sockaddr *sa = addr; 1138 1139 if (!is_valid_ether_addr(sa->sa_data)) 1140 return -EADDRNOTAVAIL; 1141 1142 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1143 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1144 eth_hw_addr_set(ndev, sa->sa_data); 1145 1146 /* MAC address is configured only after the interface is enabled. */ 1147 if (netif_running(ndev)) { 1148 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1149 } 1150 1151 if (netif_msg_drv(priv)) 1152 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1153 priv->mac_addr); 1154 1155 return 0; 1156} 1157 1158/** 1159 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception 1160 * @priv: The DaVinci EMAC private adapter structure 1161 * 1162 * Enables EMAC hardware for packet processing - enables PHY, enables RX 1163 * for packet reception and enables device interrupts and then NAPI 1164 * 1165 * Returns success (0) or appropriate error code (none right now) 1166 */ 1167static int emac_hw_enable(struct emac_priv *priv) 1168{ 1169 u32 val, mbp_enable, mac_control; 1170 1171 /* Soft reset */ 1172 emac_write(EMAC_SOFTRESET, 1); 1173 while (emac_read(EMAC_SOFTRESET)) 1174 cpu_relax(); 1175 1176 /* Disable interrupt & Set pacing for more interrupts initially */ 1177 emac_int_disable(priv); 1178 1179 /* Full duplex enable bit set when auto negotiation happens */ 1180 mac_control = 1181 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | 1182 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | 1183 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | 1184 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); 1185 emac_write(EMAC_MACCONTROL, mac_control); 1186 1187 mbp_enable = 1188 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | 1189 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | 1190 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | 1191 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | 1192 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | 1193 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | 1194 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | 1195 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ 1196 EMAC_RXMBP_PROMCH_SHIFT) | 1197 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | 1198 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ 1199 EMAC_RXMBP_BROADCH_SHIFT) | 1200 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | 1201 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ 1202 EMAC_RXMBP_MULTICH_SHIFT)); 1203 emac_write(EMAC_RXMBPENABLE, mbp_enable); 1204 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & 1205 EMAC_RX_MAX_LEN_MASK)); 1206 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & 1207 EMAC_RX_BUFFER_OFFSET_MASK)); 1208 emac_write(EMAC_RXFILTERLOWTHRESH, 0); 1209 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1210 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1211 1212 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1213 1214 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1215 1216 /* Enable MII */ 1217 val = emac_read(EMAC_MACCONTROL); 1218 val |= (EMAC_MACCONTROL_GMIIEN); 1219 emac_write(EMAC_MACCONTROL, val); 1220 1221 /* Enable NAPI and interrupts */ 1222 napi_enable(&priv->napi); 1223 emac_int_enable(priv); 1224 return 0; 1225 1226} 1227 1228/** 1229 * emac_poll - EMAC NAPI Poll function 1230 * @napi: pointer to the napi_struct containing The DaVinci EMAC network adapter 1231 * @budget: Number of receive packets to process (as told by NAPI layer) 1232 * 1233 * NAPI Poll function implemented to process packets as per budget. We check 1234 * the type of interrupt on the device and accordingly call the TX or RX 1235 * packet processing functions. We follow the budget for RX processing and 1236 * also put a cap on number of TX pkts processed through config param. The 1237 * NAPI schedule function is called if more packets pending. 1238 * 1239 * Returns number of packets received (in most cases; else TX pkts - rarely) 1240 */ 1241static int emac_poll(struct napi_struct *napi, int budget) 1242{ 1243 unsigned int mask; 1244 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 1245 struct net_device *ndev = priv->ndev; 1246 struct device *emac_dev = &ndev->dev; 1247 u32 status = 0; 1248 u32 num_rx_pkts = 0; 1249 1250 /* Check interrupt vectors and call packet processing */ 1251 status = emac_read(EMAC_MACINVECTOR); 1252 1253 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; 1254 1255 if (priv->version == EMAC_VERSION_2) 1256 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1257 1258 if (status & mask) { 1259 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE); 1260 } /* TX processing */ 1261 1262 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1263 1264 if (priv->version == EMAC_VERSION_2) 1265 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1266 1267 if (status & mask) { 1268 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); 1269 } /* RX processing */ 1270 1271 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1272 if (priv->version == EMAC_VERSION_2) 1273 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; 1274 1275 if (unlikely(status & mask)) { 1276 u32 ch, cause; 1277 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); 1278 netif_stop_queue(ndev); 1279 napi_disable(&priv->napi); 1280 1281 status = emac_read(EMAC_MACSTATUS); 1282 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> 1283 EMAC_MACSTATUS_TXERRCODE_SHIFT); 1284 if (cause) { 1285 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> 1286 EMAC_MACSTATUS_TXERRCH_SHIFT); 1287 if (net_ratelimit()) { 1288 dev_err(emac_dev, "TX Host error %s on ch=%d\n", 1289 &emac_txhost_errcodes[cause][0], ch); 1290 } 1291 } 1292 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> 1293 EMAC_MACSTATUS_RXERRCODE_SHIFT); 1294 if (cause) { 1295 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> 1296 EMAC_MACSTATUS_RXERRCH_SHIFT); 1297 if (netif_msg_hw(priv) && net_ratelimit()) 1298 dev_err(emac_dev, "RX Host error %s on ch=%d\n", 1299 &emac_rxhost_errcodes[cause][0], ch); 1300 } 1301 } else if (num_rx_pkts < budget) { 1302 napi_complete_done(napi, num_rx_pkts); 1303 emac_int_enable(priv); 1304 } 1305 1306 return num_rx_pkts; 1307} 1308 1309#ifdef CONFIG_NET_POLL_CONTROLLER 1310/** 1311 * emac_poll_controller - EMAC Poll controller function 1312 * @ndev: The DaVinci EMAC network adapter 1313 * 1314 * Polled functionality used by netconsole and others in non interrupt mode 1315 * 1316 */ 1317static void emac_poll_controller(struct net_device *ndev) 1318{ 1319 struct emac_priv *priv = netdev_priv(ndev); 1320 1321 emac_int_disable(priv); 1322 emac_irq(ndev->irq, ndev); 1323 emac_int_enable(priv); 1324} 1325#endif 1326 1327static void emac_adjust_link(struct net_device *ndev) 1328{ 1329 struct emac_priv *priv = netdev_priv(ndev); 1330 struct phy_device *phydev = ndev->phydev; 1331 unsigned long flags; 1332 int new_state = 0; 1333 1334 spin_lock_irqsave(&priv->lock, flags); 1335 1336 if (phydev->link) { 1337 /* check the mode of operation - full/half duplex */ 1338 if (phydev->duplex != priv->duplex) { 1339 new_state = 1; 1340 priv->duplex = phydev->duplex; 1341 } 1342 if (phydev->speed != priv->speed) { 1343 new_state = 1; 1344 priv->speed = phydev->speed; 1345 } 1346 if (!priv->link) { 1347 new_state = 1; 1348 priv->link = 1; 1349 } 1350 1351 } else if (priv->link) { 1352 new_state = 1; 1353 priv->link = 0; 1354 priv->speed = 0; 1355 priv->duplex = ~0; 1356 } 1357 if (new_state) { 1358 emac_update_phystatus(priv); 1359 phy_print_status(ndev->phydev); 1360 } 1361 1362 spin_unlock_irqrestore(&priv->lock, flags); 1363} 1364 1365/************************************************************************* 1366 * Linux Driver Model 1367 *************************************************************************/ 1368 1369/** 1370 * emac_devioctl - EMAC adapter ioctl 1371 * @ndev: The DaVinci EMAC network adapter 1372 * @ifrq: request parameter 1373 * @cmd: command parameter 1374 * 1375 * EMAC driver ioctl function 1376 * 1377 * Returns success(0) or appropriate error code 1378 */ 1379static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) 1380{ 1381 if (!(netif_running(ndev))) 1382 return -EINVAL; 1383 1384 /* TODO: Add phy read and write and private statistics get feature */ 1385 1386 if (ndev->phydev) 1387 return phy_mii_ioctl(ndev->phydev, ifrq, cmd); 1388 else 1389 return -EOPNOTSUPP; 1390} 1391 1392static int match_first_device(struct device *dev, const void *data) 1393{ 1394 if (dev->parent && dev->parent->of_node) 1395 return of_device_is_compatible(dev->parent->of_node, 1396 "ti,davinci_mdio"); 1397 1398 return !strncmp(dev_name(dev), "davinci_mdio", 12); 1399} 1400 1401/** 1402 * emac_dev_open - EMAC device open 1403 * @ndev: The DaVinci EMAC network adapter 1404 * 1405 * Called when system wants to start the interface. We init TX/RX channels 1406 * and enable the hardware for packet reception/transmission and start the 1407 * network queue. 1408 * 1409 * Returns 0 for a successful open, or appropriate error code 1410 */ 1411static int emac_dev_open(struct net_device *ndev) 1412{ 1413 struct device *emac_dev = &ndev->dev; 1414 struct resource *res; 1415 int q, m, ret; 1416 int res_num = 0, irq_num = 0; 1417 int i = 0; 1418 struct emac_priv *priv = netdev_priv(ndev); 1419 struct phy_device *phydev = NULL; 1420 struct device *phy = NULL; 1421 1422 ret = pm_runtime_resume_and_get(&priv->pdev->dev); 1423 if (ret < 0) { 1424 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1425 __func__, ret); 1426 return ret; 1427 } 1428 1429 netif_carrier_off(ndev); 1430 eth_hw_addr_set(ndev, priv->mac_addr); 1431 1432 /* Configuration items */ 1433 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1434 1435 priv->mac_hash1 = 0; 1436 priv->mac_hash2 = 0; 1437 emac_write(EMAC_MACHASH1, 0); 1438 emac_write(EMAC_MACHASH2, 0); 1439 1440 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { 1441 struct sk_buff *skb = emac_rx_alloc(priv); 1442 1443 if (!skb) 1444 break; 1445 1446 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data, 1447 skb_tailroom(skb), 0); 1448 if (WARN_ON(ret < 0)) 1449 break; 1450 } 1451 1452 /* Request IRQ */ 1453 if (dev_of_node(&priv->pdev->dev)) { 1454 while ((ret = platform_get_irq_optional(priv->pdev, res_num)) != -ENXIO) { 1455 if (ret < 0) 1456 goto rollback; 1457 1458 ret = request_irq(ret, emac_irq, 0, ndev->name, ndev); 1459 if (ret) { 1460 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed\n"); 1461 goto rollback; 1462 } 1463 res_num++; 1464 } 1465 } else { 1466 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, res_num))) { 1467 for (irq_num = res->start; irq_num <= res->end; irq_num++) { 1468 ret = request_irq(irq_num, emac_irq, 0, ndev->name, ndev); 1469 if (ret) { 1470 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed\n"); 1471 goto rollback; 1472 } 1473 } 1474 res_num++; 1475 } 1476 /* prepare counters for rollback in case of an error */ 1477 res_num--; 1478 irq_num--; 1479 } 1480 1481 /* Start/Enable EMAC hardware */ 1482 emac_hw_enable(priv); 1483 1484 /* Enable Interrupt pacing if configured */ 1485 if (priv->coal_intvl != 0) { 1486 struct ethtool_coalesce coal; 1487 1488 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1489 emac_set_coalesce(ndev, &coal, NULL, NULL); 1490 } 1491 1492 cpdma_ctlr_start(priv->dma); 1493 1494 if (priv->phy_node) { 1495 phydev = of_phy_connect(ndev, priv->phy_node, 1496 &emac_adjust_link, 0, 0); 1497 if (!phydev) { 1498 dev_err(emac_dev, "could not connect to phy %pOF\n", 1499 priv->phy_node); 1500 ret = -ENODEV; 1501 goto err; 1502 } 1503 } 1504 1505 /* use the first phy on the bus if pdata did not give us a phy id */ 1506 if (!phydev && !priv->phy_id) { 1507 /* NOTE: we can't use bus_find_device_by_name() here because 1508 * the device name is not guaranteed to be 'davinci_mdio'. On 1509 * some systems it can be 'davinci_mdio.0' so we need to use 1510 * strncmp() against the first part of the string to correctly 1511 * match it. 1512 */ 1513 phy = bus_find_device(&mdio_bus_type, NULL, NULL, 1514 match_first_device); 1515 if (phy) { 1516 priv->phy_id = dev_name(phy); 1517 if (!priv->phy_id || !*priv->phy_id) 1518 put_device(phy); 1519 } 1520 } 1521 1522 if (!phydev && priv->phy_id && *priv->phy_id) { 1523 phydev = phy_connect(ndev, priv->phy_id, 1524 &emac_adjust_link, 1525 PHY_INTERFACE_MODE_MII); 1526 put_device(phy); /* reference taken by bus_find_device */ 1527 if (IS_ERR(phydev)) { 1528 dev_err(emac_dev, "could not connect to phy %s\n", 1529 priv->phy_id); 1530 ret = PTR_ERR(phydev); 1531 goto err; 1532 } 1533 1534 priv->link = 0; 1535 priv->speed = 0; 1536 priv->duplex = ~0; 1537 1538 phy_attached_info(phydev); 1539 } 1540 1541 if (!phydev) { 1542 /* No PHY , fix the link, speed and duplex settings */ 1543 dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); 1544 priv->link = 1; 1545 priv->speed = SPEED_100; 1546 priv->duplex = DUPLEX_FULL; 1547 emac_update_phystatus(priv); 1548 } 1549 1550 if (netif_msg_drv(priv)) 1551 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1552 1553 if (phydev) 1554 phy_start(phydev); 1555 1556 return 0; 1557 1558err: 1559 emac_int_disable(priv); 1560 napi_disable(&priv->napi); 1561 1562rollback: 1563 if (dev_of_node(&priv->pdev->dev)) { 1564 for (q = res_num - 1; q >= 0; q--) { 1565 irq_num = platform_get_irq(priv->pdev, q); 1566 if (irq_num > 0) 1567 free_irq(irq_num, ndev); 1568 } 1569 } else { 1570 for (q = res_num; q >= 0; q--) { 1571 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q); 1572 /* at the first iteration, irq_num is already set to the 1573 * right value 1574 */ 1575 if (q != res_num) 1576 irq_num = res->end; 1577 1578 for (m = irq_num; m >= res->start; m--) 1579 free_irq(m, ndev); 1580 } 1581 } 1582 cpdma_ctlr_stop(priv->dma); 1583 pm_runtime_put(&priv->pdev->dev); 1584 return ret; 1585} 1586 1587/** 1588 * emac_dev_stop - EMAC device stop 1589 * @ndev: The DaVinci EMAC network adapter 1590 * 1591 * Called when system wants to stop or down the interface. We stop the network 1592 * queue, disable interrupts and cleanup TX/RX channels. 1593 * 1594 * We return the statistics in net_device_stats structure pulled from emac 1595 */ 1596static int emac_dev_stop(struct net_device *ndev) 1597{ 1598 struct resource *res; 1599 int i = 0; 1600 int irq_num; 1601 struct emac_priv *priv = netdev_priv(ndev); 1602 struct device *emac_dev = &ndev->dev; 1603 int ret = 0; 1604 1605 /* inform the upper layers. */ 1606 netif_stop_queue(ndev); 1607 napi_disable(&priv->napi); 1608 1609 netif_carrier_off(ndev); 1610 emac_int_disable(priv); 1611 cpdma_ctlr_stop(priv->dma); 1612 emac_write(EMAC_SOFTRESET, 1); 1613 1614 if (ndev->phydev) 1615 phy_disconnect(ndev->phydev); 1616 1617 /* Free IRQ */ 1618 if (dev_of_node(&priv->pdev->dev)) { 1619 do { 1620 ret = platform_get_irq_optional(priv->pdev, i); 1621 if (ret < 0 && ret != -ENXIO) 1622 break; 1623 if (ret > 0) { 1624 free_irq(ret, priv->ndev); 1625 } else { 1626 ret = 0; 1627 break; 1628 } 1629 } while (++i); 1630 } else { 1631 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { 1632 for (irq_num = res->start; irq_num <= res->end; irq_num++) 1633 free_irq(irq_num, priv->ndev); 1634 i++; 1635 } 1636 } 1637 1638 if (netif_msg_drv(priv)) 1639 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); 1640 1641 pm_runtime_put(&priv->pdev->dev); 1642 return ret; 1643} 1644 1645/** 1646 * emac_dev_getnetstats - EMAC get statistics function 1647 * @ndev: The DaVinci EMAC network adapter 1648 * 1649 * Called when system wants to get statistics from the device. 1650 * 1651 * We return the statistics in net_device_stats structure pulled from emac 1652 */ 1653static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 1654{ 1655 struct emac_priv *priv = netdev_priv(ndev); 1656 u32 mac_control; 1657 u32 stats_clear_mask; 1658 int err; 1659 1660 err = pm_runtime_resume_and_get(&priv->pdev->dev); 1661 if (err < 0) { 1662 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1663 __func__, err); 1664 return &ndev->stats; 1665 } 1666 1667 /* update emac hardware stats and reset the registers*/ 1668 1669 mac_control = emac_read(EMAC_MACCONTROL); 1670 1671 if (mac_control & EMAC_MACCONTROL_GMIIEN) 1672 stats_clear_mask = EMAC_STATS_CLR_MASK; 1673 else 1674 stats_clear_mask = 0; 1675 1676 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 1677 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); 1678 1679 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + 1680 emac_read(EMAC_TXSINGLECOLL) + 1681 emac_read(EMAC_TXMULTICOLL)); 1682 emac_write(EMAC_TXCOLLISION, stats_clear_mask); 1683 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); 1684 emac_write(EMAC_TXMULTICOLL, stats_clear_mask); 1685 1686 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 1687 emac_read(EMAC_RXJABBER) + 1688 emac_read(EMAC_RXUNDERSIZED)); 1689 emac_write(EMAC_RXOVERSIZED, stats_clear_mask); 1690 emac_write(EMAC_RXJABBER, stats_clear_mask); 1691 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); 1692 1693 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 1694 emac_read(EMAC_RXMOFOVERRUNS)); 1695 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); 1696 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); 1697 1698 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 1699 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); 1700 1701 ndev->stats.tx_carrier_errors += 1702 emac_read(EMAC_TXCARRIERSENSE); 1703 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1704 1705 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); 1706 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1707 1708 pm_runtime_put(&priv->pdev->dev); 1709 1710 return &ndev->stats; 1711} 1712 1713static const struct net_device_ops emac_netdev_ops = { 1714 .ndo_open = emac_dev_open, 1715 .ndo_stop = emac_dev_stop, 1716 .ndo_start_xmit = emac_dev_xmit, 1717 .ndo_set_rx_mode = emac_dev_mcast_set, 1718 .ndo_set_mac_address = emac_dev_setmac_addr, 1719 .ndo_eth_ioctl = emac_devioctl, 1720 .ndo_tx_timeout = emac_dev_tx_timeout, 1721 .ndo_get_stats = emac_dev_getnetstats, 1722#ifdef CONFIG_NET_POLL_CONTROLLER 1723 .ndo_poll_controller = emac_poll_controller, 1724#endif 1725}; 1726 1727static struct emac_platform_data * 1728davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) 1729{ 1730 struct device_node *np; 1731 const struct emac_platform_data *auxdata; 1732 struct emac_platform_data *pdata = NULL; 1733 1734 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 1735 return dev_get_platdata(&pdev->dev); 1736 1737 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1738 if (!pdata) 1739 return NULL; 1740 1741 np = pdev->dev.of_node; 1742 pdata->version = EMAC_VERSION_2; 1743 1744 if (!is_valid_ether_addr(pdata->mac_addr)) 1745 of_get_mac_address(np, pdata->mac_addr); 1746 1747 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", 1748 &pdata->ctrl_reg_offset); 1749 1750 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", 1751 &pdata->ctrl_mod_reg_offset); 1752 1753 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", 1754 &pdata->ctrl_ram_offset); 1755 1756 of_property_read_u32(np, "ti,davinci-ctrl-ram-size", 1757 &pdata->ctrl_ram_size); 1758 1759 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en); 1760 1761 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram"); 1762 1763 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 1764 if (!priv->phy_node) { 1765 if (!of_phy_is_fixed_link(np)) 1766 pdata->phy_id = NULL; 1767 else if (of_phy_register_fixed_link(np) >= 0) 1768 priv->phy_node = of_node_get(np); 1769 } 1770 1771 auxdata = pdev->dev.platform_data; 1772 if (auxdata) { 1773 pdata->interrupt_enable = auxdata->interrupt_enable; 1774 pdata->interrupt_disable = auxdata->interrupt_disable; 1775 } 1776 1777 auxdata = device_get_match_data(&pdev->dev); 1778 if (auxdata) { 1779 pdata->version = auxdata->version; 1780 pdata->hw_ram_addr = auxdata->hw_ram_addr; 1781 } 1782 1783 return pdata; 1784} 1785 1786static int davinci_emac_try_get_mac(struct platform_device *pdev, 1787 int instance, u8 *mac_addr) 1788{ 1789 if (!pdev->dev.of_node) 1790 return -EINVAL; 1791 1792 return ti_cm_get_macid(&pdev->dev, instance, mac_addr); 1793} 1794 1795/** 1796 * davinci_emac_probe - EMAC device probe 1797 * @pdev: The DaVinci EMAC device that we are removing 1798 * 1799 * Called when probing for emac devicesr. We get details of instances and 1800 * resource information from platform init and register a network device 1801 * and allocate resources necessary for driver to perform 1802 */ 1803static int davinci_emac_probe(struct platform_device *pdev) 1804{ 1805 struct device_node *np = pdev->dev.of_node; 1806 int rc = 0; 1807 struct resource *res, *res_ctrl; 1808 struct net_device *ndev; 1809 struct emac_priv *priv; 1810 unsigned long hw_ram_addr; 1811 struct emac_platform_data *pdata; 1812 struct cpdma_params dma_params; 1813 struct clk *emac_clk; 1814 unsigned long emac_bus_frequency; 1815 1816 1817 /* obtain emac clock from kernel */ 1818 emac_clk = devm_clk_get(&pdev->dev, NULL); 1819 if (IS_ERR(emac_clk)) { 1820 dev_err(&pdev->dev, "failed to get EMAC clock\n"); 1821 return -EBUSY; 1822 } 1823 emac_bus_frequency = clk_get_rate(emac_clk); 1824 devm_clk_put(&pdev->dev, emac_clk); 1825 1826 /* TODO: Probe PHY here if possible */ 1827 1828 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1829 if (!ndev) 1830 return -ENOMEM; 1831 1832 platform_set_drvdata(pdev, ndev); 1833 priv = netdev_priv(ndev); 1834 priv->pdev = pdev; 1835 priv->ndev = ndev; 1836 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1837 1838 spin_lock_init(&priv->lock); 1839 1840 pdata = davinci_emac_of_get_pdata(pdev, priv); 1841 if (!pdata) { 1842 dev_err(&pdev->dev, "no platform data\n"); 1843 rc = -ENODEV; 1844 goto err_free_netdev; 1845 } 1846 1847 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1848 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN); 1849 priv->phy_id = pdata->phy_id; 1850 priv->rmii_en = pdata->rmii_en; 1851 priv->version = pdata->version; 1852 priv->int_enable = pdata->interrupt_enable; 1853 priv->int_disable = pdata->interrupt_disable; 1854 1855 priv->coal_intvl = 0; 1856 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); 1857 1858 /* Get EMAC platform data */ 1859 priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1860 if (IS_ERR(priv->remap_addr)) { 1861 rc = PTR_ERR(priv->remap_addr); 1862 goto no_pdata; 1863 } 1864 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1865 1866 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1867 if (res_ctrl) { 1868 priv->ctrl_base = 1869 devm_ioremap_resource(&pdev->dev, res_ctrl); 1870 if (IS_ERR(priv->ctrl_base)) { 1871 rc = PTR_ERR(priv->ctrl_base); 1872 goto no_pdata; 1873 } 1874 } else { 1875 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1876 } 1877 1878 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; 1879 ndev->base_addr = (unsigned long)priv->remap_addr; 1880 1881 hw_ram_addr = pdata->hw_ram_addr; 1882 if (!hw_ram_addr) 1883 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; 1884 1885 memset(&dma_params, 0, sizeof(dma_params)); 1886 dma_params.dev = &pdev->dev; 1887 dma_params.dmaregs = priv->emac_base; 1888 dma_params.rxthresh = priv->emac_base + 0x120; 1889 dma_params.rxfree = priv->emac_base + 0x140; 1890 dma_params.txhdp = priv->emac_base + 0x600; 1891 dma_params.rxhdp = priv->emac_base + 0x620; 1892 dma_params.txcp = priv->emac_base + 0x640; 1893 dma_params.rxcp = priv->emac_base + 0x660; 1894 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; 1895 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; 1896 dma_params.desc_hw_addr = hw_ram_addr; 1897 dma_params.desc_mem_size = pdata->ctrl_ram_size; 1898 dma_params.desc_align = 16; 1899 1900 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : 1901 (u32 __force)res->start + pdata->ctrl_ram_offset; 1902 1903 priv->dma = cpdma_ctlr_create(&dma_params); 1904 if (!priv->dma) { 1905 dev_err(&pdev->dev, "error initializing DMA\n"); 1906 rc = -ENOMEM; 1907 goto no_pdata; 1908 } 1909 1910 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH, 1911 emac_tx_handler, 0); 1912 if (IS_ERR(priv->txchan)) { 1913 dev_err(&pdev->dev, "error initializing tx dma channel\n"); 1914 rc = PTR_ERR(priv->txchan); 1915 goto err_free_dma; 1916 } 1917 1918 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH, 1919 emac_rx_handler, 1); 1920 if (IS_ERR(priv->rxchan)) { 1921 dev_err(&pdev->dev, "error initializing rx dma channel\n"); 1922 rc = PTR_ERR(priv->rxchan); 1923 goto err_free_txchan; 1924 } 1925 1926 rc = platform_get_irq(pdev, 0); 1927 if (rc < 0) 1928 goto err_free_rxchan; 1929 ndev->irq = rc; 1930 1931 /* If the MAC address is not present, read the registers from the SoC */ 1932 if (!is_valid_ether_addr(priv->mac_addr)) { 1933 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr); 1934 if (!rc) 1935 eth_hw_addr_set(ndev, priv->mac_addr); 1936 1937 if (!is_valid_ether_addr(priv->mac_addr)) { 1938 /* Use random MAC if still none obtained. */ 1939 eth_hw_addr_random(ndev); 1940 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); 1941 dev_warn(&pdev->dev, "using random MAC addr: %pM\n", 1942 priv->mac_addr); 1943 } 1944 } 1945 ndev->netdev_ops = &emac_netdev_ops; 1946 ndev->ethtool_ops = ðtool_ops; 1947 netif_napi_add(ndev, &priv->napi, emac_poll); 1948 1949 pm_runtime_enable(&pdev->dev); 1950 rc = pm_runtime_resume_and_get(&pdev->dev); 1951 if (rc < 0) { 1952 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n", 1953 __func__, rc); 1954 goto err_napi_del; 1955 } 1956 1957 /* register the network device */ 1958 SET_NETDEV_DEV(ndev, &pdev->dev); 1959 rc = register_netdev(ndev); 1960 if (rc) { 1961 dev_err(&pdev->dev, "error in register_netdev\n"); 1962 rc = -ENODEV; 1963 pm_runtime_put(&pdev->dev); 1964 goto err_napi_del; 1965 } 1966 1967 1968 if (netif_msg_probe(priv)) { 1969 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device " 1970 "(regs: %pa, irq: %d)\n", 1971 &priv->emac_base_phys, ndev->irq); 1972 } 1973 pm_runtime_put(&pdev->dev); 1974 1975 return 0; 1976 1977err_napi_del: 1978 netif_napi_del(&priv->napi); 1979err_free_rxchan: 1980 cpdma_chan_destroy(priv->rxchan); 1981err_free_txchan: 1982 cpdma_chan_destroy(priv->txchan); 1983err_free_dma: 1984 cpdma_ctlr_destroy(priv->dma); 1985no_pdata: 1986 if (of_phy_is_fixed_link(np)) 1987 of_phy_deregister_fixed_link(np); 1988 of_node_put(priv->phy_node); 1989err_free_netdev: 1990 free_netdev(ndev); 1991 return rc; 1992} 1993 1994/** 1995 * davinci_emac_remove - EMAC device remove 1996 * @pdev: The DaVinci EMAC device that we are removing 1997 * 1998 * Called when removing the device driver. We disable clock usage and release 1999 * the resources taken up by the driver and unregister network device 2000 */ 2001static void davinci_emac_remove(struct platform_device *pdev) 2002{ 2003 struct net_device *ndev = platform_get_drvdata(pdev); 2004 struct emac_priv *priv = netdev_priv(ndev); 2005 struct device_node *np = pdev->dev.of_node; 2006 2007 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); 2008 2009 if (priv->txchan) 2010 cpdma_chan_destroy(priv->txchan); 2011 if (priv->rxchan) 2012 cpdma_chan_destroy(priv->rxchan); 2013 cpdma_ctlr_destroy(priv->dma); 2014 2015 unregister_netdev(ndev); 2016 of_node_put(priv->phy_node); 2017 pm_runtime_disable(&pdev->dev); 2018 if (of_phy_is_fixed_link(np)) 2019 of_phy_deregister_fixed_link(np); 2020 free_netdev(ndev); 2021} 2022 2023static int davinci_emac_suspend(struct device *dev) 2024{ 2025 struct net_device *ndev = dev_get_drvdata(dev); 2026 2027 if (netif_running(ndev)) 2028 emac_dev_stop(ndev); 2029 2030 return 0; 2031} 2032 2033static int davinci_emac_resume(struct device *dev) 2034{ 2035 struct net_device *ndev = dev_get_drvdata(dev); 2036 2037 if (netif_running(ndev)) 2038 emac_dev_open(ndev); 2039 2040 return 0; 2041} 2042 2043static const struct dev_pm_ops davinci_emac_pm_ops = { 2044 .suspend = davinci_emac_suspend, 2045 .resume = davinci_emac_resume, 2046}; 2047 2048static const struct emac_platform_data am3517_emac_data = { 2049 .version = EMAC_VERSION_2, 2050 .hw_ram_addr = 0x01e20000, 2051}; 2052 2053static const struct emac_platform_data dm816_emac_data = { 2054 .version = EMAC_VERSION_2, 2055}; 2056 2057static const struct of_device_id davinci_emac_of_match[] = { 2058 {.compatible = "ti,davinci-dm6467-emac", }, 2059 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, }, 2060 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, }, 2061 {}, 2062}; 2063MODULE_DEVICE_TABLE(of, davinci_emac_of_match); 2064 2065/* davinci_emac_driver: EMAC platform driver structure */ 2066static struct platform_driver davinci_emac_driver = { 2067 .driver = { 2068 .name = "davinci_emac", 2069 .pm = &davinci_emac_pm_ops, 2070 .of_match_table = davinci_emac_of_match, 2071 }, 2072 .probe = davinci_emac_probe, 2073 .remove_new = davinci_emac_remove, 2074}; 2075 2076/** 2077 * davinci_emac_init - EMAC driver module init 2078 * 2079 * Called when initializing the driver. We register the driver with 2080 * the platform. 2081 */ 2082static int __init davinci_emac_init(void) 2083{ 2084 return platform_driver_register(&davinci_emac_driver); 2085} 2086late_initcall(davinci_emac_init); 2087 2088/** 2089 * davinci_emac_exit - EMAC driver module exit 2090 * 2091 * Called when exiting the driver completely. We unregister the driver with 2092 * the platform and exit 2093 */ 2094static void __exit davinci_emac_exit(void) 2095{ 2096 platform_driver_unregister(&davinci_emac_driver); 2097} 2098module_exit(davinci_emac_exit); 2099 2100MODULE_LICENSE("GPL"); 2101MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); 2102MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); 2103MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); 2104