1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $ 3 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver. 4 * 5 * Copyright (C) 2004 Sun Microsystems Inc. 6 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com) 7 * 8 * vendor id: 0x108E (Sun Microsystems, Inc.) 9 * device id: 0xabba (Cassini) 10 * revision ids: 0x01 = Cassini 11 * 0x02 = Cassini rev 2 12 * 0x10 = Cassini+ 13 * 0x11 = Cassini+ 0.2u 14 * 15 * vendor id: 0x100b (National Semiconductor) 16 * device id: 0x0035 (DP83065/Saturn) 17 * revision ids: 0x30 = Saturn B2 18 * 19 * rings are all offset from 0. 20 * 21 * there are two clock domains: 22 * PCI: 33/66MHz clock 23 * chip: 125MHz clock 24 */ 25 26#ifndef _CASSINI_H 27#define _CASSINI_H 28 29/* cassini register map: 2M memory mapped in 32-bit memory space accessible as 30 * 32-bit words. there is no i/o port access. REG_ addresses are 31 * shared between cassini and cassini+. REG_PLUS_ addresses only 32 * appear in cassini+. REG_MINUS_ addresses only appear in cassini. 33 */ 34#define CAS_ID_REV2 0x02 35#define CAS_ID_REVPLUS 0x10 36#define CAS_ID_REVPLUS02u 0x11 37#define CAS_ID_REVSATURNB2 0x30 38 39/** global resources **/ 40 41/* this register sets the weights for the weighted round robin arbiter. e.g., 42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit 43 * for its next turn to access the pci bus. 44 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8 45 * DEFAULT: 0x0, SIZE: 5 bits 46 */ 47#define REG_CAWR 0x0004 /* core arbitration weight */ 48#define CAWR_RX_DMA_WEIGHT_SHIFT 0 49#define CAWR_RX_DMA_WEIGHT_MASK 0x03 /* [0:1] */ 50#define CAWR_TX_DMA_WEIGHT_SHIFT 2 51#define CAWR_TX_DMA_WEIGHT_MASK 0x0C /* [3:2] */ 52#define CAWR_RR_DIS 0x10 /* [4] */ 53 54/* if enabled, BIM can send bursts across PCI bus > cacheline size. burst 55 * sizes determined by length of packet or descriptor transfer and the 56 * max length allowed by the target. 57 * DEFAULT: 0x0, SIZE: 1 bit 58 */ 59#define REG_INF_BURST 0x0008 /* infinite burst enable reg */ 60#define INF_BURST_EN 0x1 /* enable */ 61 62/* top level interrupts [0-9] are auto-cleared to 0 when the status 63 * register is read. second level interrupts [13 - 18] are cleared at 64 * the source. tx completion register 3 is replicated in [19 - 31] 65 * DEFAULT: 0x00000000, SIZE: 29 bits 66 */ 67#define REG_INTR_STATUS 0x000C /* interrupt status register */ 68#define INTR_TX_INTME 0x00000001 /* frame w/ INT ME desc bit set 69 xferred from host queue to 70 TX FIFO */ 71#define INTR_TX_ALL 0x00000002 /* all xmit frames xferred into 72 TX FIFO. i.e., 73 TX Kick == TX complete. if 74 PACED_MODE set, then TX FIFO 75 also empty */ 76#define INTR_TX_DONE 0x00000004 /* any frame xferred into tx 77 FIFO */ 78#define INTR_TX_TAG_ERROR 0x00000008 /* TX FIFO tag framing 79 corrupted. FATAL ERROR */ 80#define INTR_RX_DONE 0x00000010 /* at least 1 frame xferred 81 from RX FIFO to host mem. 82 RX completion reg updated. 83 may be delayed by recv 84 intr blanking. */ 85#define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers. 86 RX Kick == RX complete */ 87#define INTR_RX_TAG_ERROR 0x00000040 /* RX FIFO tag framing 88 corrupted. FATAL ERROR */ 89#define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion 90 ring to post descriptors. 91 RX complete head incr to 92 almost reach RX complete 93 tail */ 94#define INTR_RX_BUF_AE 0x00000100 /* less than the 95 programmable threshold # 96 of free descr avail for 97 hw use */ 98#define INTR_RX_COMP_AF 0x00000200 /* less than the 99 programmable threshold # 100 of descr spaces for hw 101 use in completion descr 102 ring */ 103#define INTR_RX_LEN_MISMATCH 0x00000400 /* len field from MAC != 104 len of non-reassembly pkt 105 from fifo during DMA or 106 header parser provides TCP 107 header and payload size > 108 MAC packet size. 109 FATAL ERROR */ 110#define INTR_SUMMARY 0x00001000 /* summary interrupt bit. this 111 bit will be set if an interrupt 112 generated on the pci bus. useful 113 when driver is polling for 114 interrupts */ 115#define INTR_PCS_STATUS 0x00002000 /* PCS interrupt status register */ 116#define INTR_TX_MAC_STATUS 0x00004000 /* TX MAC status register has at 117 least 1 unmasked interrupt set */ 118#define INTR_RX_MAC_STATUS 0x00008000 /* RX MAC status register has at 119 least 1 unmasked interrupt set */ 120#define INTR_MAC_CTRL_STATUS 0x00010000 /* MAC control status register has 121 at least 1 unmasked interrupt 122 set */ 123#define INTR_MIF_STATUS 0x00020000 /* MIF status register has at least 124 1 unmasked interrupt set */ 125#define INTR_PCI_ERROR_STATUS 0x00040000 /* PCI error status register in the 126 BIF has at least 1 unmasked 127 interrupt set */ 128#define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion 129 3 reg data */ 130#define INTR_TX_COMP_3_SHIFT 19 131#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \ 132 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \ 133 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \ 134 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \ 135 INTR_MAC_CTRL_STATUS) 136 137/* determines which status events will cause an interrupt. layout same 138 * as REG_INTR_STATUS. 139 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits 140 */ 141#define REG_INTR_MASK 0x0010 /* Interrupt mask */ 142 143/* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS. 144 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK. 145 * DEFAULT: 0x00000000, SIZE: 12 bits 146 */ 147#define REG_ALIAS_CLEAR 0x0014 /* alias clear mask 148 (used w/ status alias) */ 149/* same as REG_INTR_STATUS except that only bits cleared are those selected by 150 * REG_ALIAS_CLEAR 151 * DEFAULT: 0x00000000, SIZE: 29 bits 152 */ 153#define REG_INTR_STATUS_ALIAS 0x001C /* interrupt status alias 154 (selective clear) */ 155 156/* DEFAULT: 0x0, SIZE: 3 bits */ 157#define REG_PCI_ERR_STATUS 0x1000 /* PCI error status */ 158#define PCI_ERR_BADACK 0x01 /* reserved in Cassini+. 159 set if no ACK64# during ABS64 cycle 160 in Cassini. */ 161#define PCI_ERR_DTRTO 0x02 /* delayed xaction timeout. set if 162 no read retry after 2^15 clocks */ 163#define PCI_ERR_OTHER 0x04 /* other PCI errors */ 164#define PCI_ERR_BIM_DMA_WRITE 0x08 /* BIM received 0 count DMA write req. 165 unused in Cassini. */ 166#define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req. 167 unused in Cassini. */ 168#define PCI_ERR_BIM_DMA_TIMEOUT 0x20 /* BIM received 255 retries during 169 DMA. unused in cassini. */ 170 171/* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event 172 * causes an interrupt to be generated. 173 * DEFAULT: 0x7, SIZE: 3 bits 174 */ 175#define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */ 176 177/* used to configure PCI related parameters that are not in PCI config space. 178 * DEFAULT: 0bxx000, SIZE: 5 bits 179 */ 180#define REG_BIM_CFG 0x1008 /* BIM Configuration */ 181#define BIM_CFG_RESERVED0 0x001 /* reserved */ 182#define BIM_CFG_RESERVED1 0x002 /* reserved */ 183#define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */ 184#define BIM_CFG_66MHZ 0x008 /* (ro) 1 = 66MHz, 0 = < 66MHz */ 185#define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */ 186#define BIM_CFG_DPAR_INTR_ENABLE 0x020 /* detected parity err enable */ 187#define BIM_CFG_RMA_INTR_ENABLE 0x040 /* master abort intr enable */ 188#define BIM_CFG_RTA_INTR_ENABLE 0x080 /* target abort intr enable */ 189#define BIM_CFG_RESERVED2 0x100 /* reserved */ 190#define BIM_CFG_BIM_DISABLE 0x200 /* stop BIM DMA. use before global 191 reset. reserved in Cassini. */ 192#define BIM_CFG_BIM_STATUS 0x400 /* (ro) 1 = BIM DMA suspended. 193 reserved in Cassini. */ 194#define BIM_CFG_PERROR_BLOCK 0x800 /* block PERR# to pci bus. def: 0. 195 reserved in Cassini. */ 196 197/* DEFAULT: 0x00000000, SIZE: 32 bits */ 198#define REG_BIM_DIAG 0x100C /* BIM Diagnostic */ 199#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00 /* PCI master controller state 200 machine bits [21:0] */ 201#define BIM_DIAG_BRST_SM_MASK 0x7F /* PCI burst controller state 202 machine bits [6:0] */ 203 204/* writing to SW_RESET_TX and SW_RESET_RX will issue a global 205 * reset. poll until TX and RX read back as 0's for completion. 206 */ 207#define REG_SW_RESET 0x1010 /* Software reset */ 208#define SW_RESET_TX 0x00000001 /* reset TX DMA engine. poll until 209 cleared to 0. */ 210#define SW_RESET_RX 0x00000002 /* reset RX DMA engine. poll until 211 cleared to 0. */ 212#define SW_RESET_RSTOUT 0x00000004 /* force RSTOUT# pin active (low). 213 resets PHY and anything else 214 connected to RSTOUT#. RSTOUT# 215 is also activated by local PCI 216 reset when hot-swap is being 217 done. */ 218#define SW_RESET_BLOCK_PCS_SLINK 0x00000008 /* if a global reset is done with 219 this bit set, PCS and SLINK 220 modules won't be reset. 221 i.e., link won't drop. */ 222#define SW_RESET_BREQ_SM_MASK 0x00007F00 /* breq state machine [6:0] */ 223#define SW_RESET_PCIARB_SM_MASK 0x00070000 /* pci arbitration state bits: 224 0b000: ARB_IDLE1 225 0b001: ARB_IDLE2 226 0b010: ARB_WB_ACK 227 0b011: ARB_WB_WAT 228 0b100: ARB_RB_ACK 229 0b101: ARB_RB_WAT 230 0b110: ARB_RB_END 231 0b111: ARB_WB_END */ 232#define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits: 233 0b00: RD_PCI_WAT 234 0b01: RD_PCI_RDY 235 0b11: RD_PCI_ACK */ 236#define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits: 237 0b00: AD_IDL_RX 238 0b01: AD_ACK_RX 239 0b10: AD_ACK_TX 240 0b11: AD_IDL_TX */ 241#define SW_RESET_WRPCI_SM_MASK 0x06000000 /* write pci state bits 242 0b00: WR_PCI_WAT 243 0b01: WR_PCI_RDY 244 0b11: WR_PCI_ACK */ 245#define SW_RESET_WRARB_SM_MASK 0x38000000 /* write arbitration state bits: 246 0b000: ARB_IDLE1 247 0b001: ARB_IDLE2 248 0b010: ARB_TX_ACK 249 0b011: ARB_TX_WAT 250 0b100: ARB_RX_ACK 251 0b110: ARB_RX_WAT */ 252 253/* Cassini only. 64-bit register used to check PCI datapath. when read, 254 * value written has both lower and upper 32-bit halves rotated to the right 255 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF 256 */ 257#define REG_MINUS_BIM_DATAPATH_TEST 0x1018 /* Cassini: BIM datapath test 258 Cassini+: reserved */ 259 260/* output enables are provided for each device's chip select and for the rest 261 * of the outputs from cassini to its local bus devices. two sw programmable 262 * bits are connected to general purpus control/status bits. 263 * DEFAULT: 0x7 264 */ 265#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device 266 output EN. default: 0x7 */ 267#define BIM_LOCAL_DEV_PAD 0x01 /* address bus, RW signal, and 268 OE signal output enable on the 269 local bus interface. these 270 are shared between both local 271 bus devices. tristate when 0. */ 272#define BIM_LOCAL_DEV_PROM 0x02 /* PROM chip select */ 273#define BIM_LOCAL_DEV_EXT 0x04 /* secondary local bus device chip 274 select output enable */ 275#define BIM_LOCAL_DEV_SOFT_0 0x08 /* sw programmable ctrl bit 0 */ 276#define BIM_LOCAL_DEV_SOFT_1 0x10 /* sw programmable ctrl bit 1 */ 277#define BIM_LOCAL_DEV_HW_RESET 0x20 /* internal hw reset. Cassini+ only. */ 278 279/* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR 280 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI. 281 * _DATA_HI should be the last access of the sequence. 282 * DEFAULT: undefined 283 */ 284#define REG_BIM_BUFFER_ADDR 0x1024 /* BIM buffer address. for 285 purposes. */ 286#define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */ 287#define BIM_BUFFER_WR_SELECT 0x40 /* write buffer access = 1 288 read buffer access = 0 */ 289/* DEFAULT: undefined */ 290#define REG_BIM_BUFFER_DATA_LOW 0x1028 /* BIM buffer data low */ 291#define REG_BIM_BUFFER_DATA_HI 0x102C /* BIM buffer data high */ 292 293/* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer. 294 * bit auto-clears when done with status read from _SUMMARY and _PASS bits. 295 */ 296#define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST 297 control/status */ 298#define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */ 299#define BIM_RAM_BIST_WR_START 0x02 /* start BIST for BIM write buffer. 300 Cassini only. reserved in 301 Cassini+. */ 302#define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read 303 buffer. */ 304#define BIM_RAM_BIST_WR_PASS 0x08 /* summary BIST pass status for write 305 buffer. Cassini only. reserved 306 in Cassini+. */ 307#define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */ 308#define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */ 309#define BIM_RAM_BIST_WR_LOW_PASS 0x40 /* write low bank passes BIST. 310 Cassini only. reserved in 311 Cassini+. */ 312#define BIM_RAM_BIST_WR_HI_PASS 0x80 /* write high bank passes BIST. 313 Cassini only. reserved in 314 Cassini+. */ 315 316/* ASUN: i'm not sure what this does as it's not in the spec. 317 * DEFAULT: 0xFC 318 */ 319#define REG_BIM_DIAG_MUX 0x1030 /* BIM diagnostic probe mux 320 select register */ 321 322/* enable probe monitoring mode and select data appearing on the P_A* bus. bit 323 * values for _SEL_HI_MASK and _SEL_LOW_MASK: 324 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w, 325 * wtc empty r, post pci) 326 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp, 327 * pci rpkt comp, txdma wr req, txdma wr ack, 328 * txdma wr rdy, txdma wr xfr done) 329 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd, 330 * rd arb state, rd pci state) 331 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state, 332 * wrpci state) 333 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8] 334 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24] 335 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40] 336 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56] 337 * the following are not available in Cassini: 338 * 0xc: rx probe[7:0] 0xd: tx probe[7:0] 339 * 0xe: hp probe[7:0] 0xf: mac probe[7:0] 340 */ 341#define REG_PLUS_PROBE_MUX_SELECT 0x1034 /* Cassini+: PROBE MUX SELECT */ 342#define PROBE_MUX_EN 0x80000000 /* allow probe signals to be 343 driven on local bus P_A[15:0] 344 for debugging */ 345#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00 /* select sub module probe signals: 346 0x03 = mac[1:0] 347 0x0C = rx[1:0] 348 0x30 = tx[1:0] 349 0xC0 = hp[1:0] */ 350#define PROBE_MUX_SEL_HI_MASK 0x000000F0 /* select which module to appear 351 on P_A[15:8]. see above for 352 values. */ 353#define PROBE_MUX_SEL_LOW_MASK 0x0000000F /* select which module to appear 354 on P_A[7:0]. see above for 355 values. */ 356 357/* values mean the same thing as REG_INTR_MASK excep that it's for INTB. 358 DEFAULT: 0x1F */ 359#define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask 360 register 2 for INTB */ 361#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16) 362/* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to 363 * all of the alternate (2-4) INTR registers while _1 corresponds to only 364 * _MASK_1 and _STATUS_1 registers. 365 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers 366 */ 367#define INTR_RX_DONE_ALT 0x01 368#define INTR_RX_COMP_FULL_ALT 0x02 369#define INTR_RX_COMP_AF_ALT 0x04 370#define INTR_RX_BUF_UNAVAIL_1 0x08 371#define INTR_RX_BUF_AE_1 0x10 /* almost empty */ 372#define INTRN_MASK_RX_EN 0x80 373#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \ 374 INTR_RX_COMP_FULL_ALT | \ 375 INTR_RX_COMP_AF_ALT | \ 376 INTR_RX_BUF_UNAVAIL_1 | \ 377 INTR_RX_BUF_AE_1) 378#define REG_PLUS_INTR_STATUS_1 0x103C /* Cassini+: interrupt status 379 register 2 for INTB. default: 0x1F */ 380#define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16) 381#define INTR_STATUS_ALT_INTX_EN 0x80 /* generate INTX when one of the 382 flags are set. enables desc ring. */ 383 384#define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask 385 register 2 for INTB */ 386#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16) 387 388#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044 /* Cassini+: interrupt status 389 register alias 2 for INTB */ 390#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16) 391 392#define REG_SATURN_PCFG 0x106c /* pin configuration register for 393 integrated macphy */ 394 395#define SATURN_PCFG_TLA 0x00000001 /* 1 = phy actled */ 396#define SATURN_PCFG_FLA 0x00000002 /* 1 = phy link10led */ 397#define SATURN_PCFG_CLA 0x00000004 /* 1 = phy link100led */ 398#define SATURN_PCFG_LLA 0x00000008 /* 1 = phy link1000led */ 399#define SATURN_PCFG_RLA 0x00000010 /* 1 = phy duplexled */ 400#define SATURN_PCFG_PDS 0x00000020 /* phy debug mode. 401 0 = normal */ 402#define SATURN_PCFG_MTP 0x00000080 /* test point select */ 403#define SATURN_PCFG_GMO 0x00000100 /* GMII observe. 1 = 404 GMII on SERDES pins for 405 monitoring. */ 406#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all 407 pins configed as outputs. 408 for power saving when using 409 internal phy. */ 410#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl 411 polarity from strapping 412 value. 413 1 = mac core led ctrl 414 polarity active low. */ 415 416 417/** transmit dma registers **/ 418#define MAX_TX_RINGS_SHIFT 2 419#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT) 420#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1) 421 422/* TX configuration. 423 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8 424 * DEFAULT: 0x3F000001 425 */ 426#define REG_TX_CFG 0x2004 /* TX config */ 427#define TX_CFG_DMA_EN 0x00000001 /* enable TX DMA. if cleared, DMA 428 will stop after xfer of current 429 buffer has been completed. */ 430#define TX_CFG_FIFO_PIO_SEL 0x00000002 /* TX DMA FIFO can be 431 accessed w/ FIFO addr 432 and data registers. 433 TX DMA should be 434 disabled. */ 435#define TX_CFG_DESC_RING0_MASK 0x0000003C /* # desc entries in 436 ring 1. */ 437#define TX_CFG_DESC_RING0_SHIFT 2 438#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4) 439#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4) 440#define TX_CFG_PACED_MODE 0x00100000 /* TX_ALL only set after 441 TX FIFO becomes empty. 442 if 0, TX_ALL set 443 if descr queue empty. */ 444#define TX_CFG_DMA_RDPIPE_DIS 0x01000000 /* always set to 1 */ 445#define TX_CFG_COMPWB_Q1 0x02000000 /* completion writeback happens at 446 the end of every packet kicked 447 through Q1. */ 448#define TX_CFG_COMPWB_Q2 0x04000000 /* completion writeback happens at 449 the end of every packet kicked 450 through Q2. */ 451#define TX_CFG_COMPWB_Q3 0x08000000 /* completion writeback happens at 452 the end of every packet kicked 453 through Q3 */ 454#define TX_CFG_COMPWB_Q4 0x10000000 /* completion writeback happens at 455 the end of every packet kicked 456 through Q4 */ 457#define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion 458 writeback */ 459#define TX_CFG_CTX_SEL_MASK 0xC0000000 /* selects tx test port 460 connection 461 0b00: tx mac req, 462 tx mac retry req, 463 tx ack and tx tag. 464 0b01: txdma rd req, 465 txdma rd ack, 466 txdma rd rdy, 467 txdma rd type0 468 0b11: txdma wr req, 469 txdma wr ack, 470 txdma wr rdy, 471 txdma wr xfr done. */ 472#define TX_CFG_CTX_SEL_SHIFT 30 473 474/* 11-bit counters that point to next location in FIFO to be loaded/retrieved. 475 * used for diagnostics only. 476 */ 477#define REG_TX_FIFO_WRITE_PTR 0x2014 /* TX FIFO write pointer */ 478#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018 /* TX FIFO shadow write 479 pointer. temp hold reg. 480 diagnostics only. */ 481#define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */ 482#define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read 483 pointer */ 484 485/* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */ 486#define REG_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO packet counter */ 487 488/* current state of all state machines in TX */ 489#define REG_TX_SM_1 0x2028 /* TX state machine reg #1 */ 490#define TX_SM_1_CHAIN_MASK 0x000003FF /* chaining state machine */ 491#define TX_SM_1_CSUM_MASK 0x00000C00 /* checksum state machine */ 492#define TX_SM_1_FIFO_LOAD_MASK 0x0003F000 /* FIFO load state machine. 493 = 0x01 when TX disabled. */ 494#define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000 /* FIFO unload state machine */ 495#define TX_SM_1_CACHE_MASK 0x03C00000 /* desc. prefetch cache controller 496 state machine */ 497#define TX_SM_1_CBQ_ARB_MASK 0xF8000000 /* CBQ arbiter state machine */ 498 499#define REG_TX_SM_2 0x202C /* TX state machine reg #2 */ 500#define TX_SM_2_COMP_WB_MASK 0x07 /* completion writeback sm */ 501#define TX_SM_2_SUB_LOAD_MASK 0x38 /* sub load state machine */ 502#define TX_SM_2_KICK_MASK 0xC0 /* kick state machine */ 503 504/* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented 505 * while the upper 23 bits are taken from the TX descriptor 506 */ 507#define REG_TX_DATA_PTR_LOW 0x2030 /* TX data pointer low */ 508#define REG_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */ 509 510/* 13 bit registers written by driver w/ descriptor value that follows 511 * last valid xmit descriptor. kick # and complete # values are used by 512 * the xmit dma engine to control tx descr fetching. if > 1 valid 513 * tx descr is available within the cache line being read, cassini will 514 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro. 515 */ 516#define REG_TX_KICK0 0x2038 /* TX kick reg #1 */ 517#define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4) 518#define REG_TX_COMP0 0x2048 /* TX completion reg #1 */ 519#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4) 520 521/* values of TX_COMPLETE_1-4 are written. each completion register 522 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment. 523 * NOTE: completion reg values are only written back prior to TX_INTME and 524 * TX_ALL interrupts. at all other times, the most up-to-date index values 525 * should be obtained from the REG_TX_COMPLETE_# registers. 526 * here's the layout: 527 * offset from base addr completion # byte 528 * 0 TX_COMPLETE_1_MSB 529 * 1 TX_COMPLETE_1_LSB 530 * 2 TX_COMPLETE_2_MSB 531 * 3 TX_COMPLETE_2_LSB 532 * 4 TX_COMPLETE_3_MSB 533 * 5 TX_COMPLETE_3_LSB 534 * 6 TX_COMPLETE_4_MSB 535 * 7 TX_COMPLETE_4_LSB 536 */ 537#define TX_COMPWB_SIZE 8 538#define REG_TX_COMPWB_DB_LOW 0x2058 /* TX completion write back 539 base low */ 540#define REG_TX_COMPWB_DB_HI 0x205C /* TX completion write back 541 base high */ 542#define TX_COMPWB_MSB_MASK 0x00000000000000FFULL 543#define TX_COMPWB_MSB_SHIFT 0 544#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL 545#define TX_COMPWB_LSB_SHIFT 8 546#define TX_COMPWB_NEXT(x) ((x) >> 16) 547 548/* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must 549 * be 2KB-aligned. */ 550#define REG_TX_DB0_LOW 0x2060 /* TX descriptor base low #1 */ 551#define REG_TX_DB0_HI 0x2064 /* TX descriptor base hi #1 */ 552#define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8) 553#define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8) 554 555/* 16-bit registers hold weights for the weighted round-robin of the 556 * four CBQ TX descr rings. weights correspond to # bytes xferred from 557 * host to TXFIFO in a round of WRR arbitration. can be set 558 * dynamically with new weights set upon completion of the current 559 * packet transfer from host memory to TXFIFO. a dummy write to any of 560 * these registers causes a queue1 pre-emption with all historical bw 561 * deficit data reset to 0 (useful when congestion requires a 562 * pre-emption/re-allocation of network bandwidth 563 */ 564#define REG_TX_MAXBURST_0 0x2080 /* TX MaxBurst #1 */ 565#define REG_TX_MAXBURST_1 0x2084 /* TX MaxBurst #2 */ 566#define REG_TX_MAXBURST_2 0x2088 /* TX MaxBurst #3 */ 567#define REG_TX_MAXBURST_3 0x208C /* TX MaxBurst #4 */ 568 569/* diagnostics access to any TX FIFO location. every access is 65 570 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit. 571 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag 572 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if 573 * TX FIFO data integrity is desired, TX DMA should be 574 * disabled. _DATA_HI_Tx should be the last access of the sequence. 575 */ 576#define REG_TX_FIFO_ADDR 0x2104 /* TX FIFO address */ 577#define REG_TX_FIFO_TAG 0x2108 /* TX FIFO tag */ 578#define REG_TX_FIFO_DATA_LOW 0x210C /* TX FIFO data low */ 579#define REG_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data high t1 */ 580#define REG_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data high t0 */ 581#define REG_TX_FIFO_SIZE 0x2118 /* (ro) TX FIFO size = 0x090 = 9KB */ 582 583/* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST 584 * passed for the specified memory 585 */ 586#define REG_TX_RAMBIST 0x211C /* TX RAMBIST control/status */ 587#define TX_RAMBIST_STATE 0x01C0 /* progress state of RAMBIST 588 controller state machine */ 589#define TX_RAMBIST_RAM33A_PASS 0x0020 /* RAM33A passed */ 590#define TX_RAMBIST_RAM32A_PASS 0x0010 /* RAM32A passed */ 591#define TX_RAMBIST_RAM33B_PASS 0x0008 /* RAM33B passed */ 592#define TX_RAMBIST_RAM32B_PASS 0x0004 /* RAM32B passed */ 593#define TX_RAMBIST_SUMMARY 0x0002 /* all RAM passed */ 594#define TX_RAMBIST_START 0x0001 /* write 1 to start BIST. self 595 clears on completion. */ 596 597/** receive dma registers **/ 598#define MAX_RX_DESC_RINGS 2 599#define MAX_RX_COMP_RINGS 4 600 601/* receive DMA channel configuration. default: 0x80910 602 * free ring size = (1 << n)*32 -> [32 - 8k] 603 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9 604 * DEFAULT: 0x80910 605 */ 606#define REG_RX_CFG 0x4000 /* RX config */ 607#define RX_CFG_DMA_EN 0x00000001 /* enable RX DMA. 0 stops 608 channel as soon as current 609 frame xfer has completed. 610 driver should disable MAC 611 for 200ms before disabling 612 RX */ 613#define RX_CFG_DESC_RING_MASK 0x0000001E /* # desc entries in RX 614 free desc ring. 615 def: 0x8 = 8k */ 616#define RX_CFG_DESC_RING_SHIFT 1 617#define RX_CFG_COMP_RING_MASK 0x000001E0 /* # desc entries in RX complete 618 ring. def: 0x8 = 32k */ 619#define RX_CFG_COMP_RING_SHIFT 5 620#define RX_CFG_BATCH_DIS 0x00000200 /* disable receive desc 621 batching. def: 0x0 = 622 enabled */ 623#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st 624 data byte of the packet 625 w/in 8 byte boundares. 626 this swivels the data 627 DMA'ed to header 628 buffers, jumbo buffers 629 when header split is not 630 requested and MTU sized 631 buffers. def: 0x2 */ 632#define RX_CFG_SWIVEL_SHIFT 10 633 634/* cassini+ only */ 635#define RX_CFG_DESC_RING1_MASK 0x000F0000 /* # of desc entries in 636 RX free desc ring 2. 637 def: 0x8 = 8k */ 638#define RX_CFG_DESC_RING1_SHIFT 16 639 640 641/* the page size register allows cassini chips to do the following with 642 * received data: 643 * [--------------------------------------------------------------] page 644 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad] 645 * |--------------| = PAGE_SIZE_BUFFER_STRIDE 646 * page = PAGE_SIZE 647 * offset = PAGE_SIZE_MTU_OFF 648 * for the above example, MTU_BUFFER_COUNT = 4. 649 * NOTE: as is apparent, you need to ensure that the following holds: 650 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE 651 * DEFAULT: 0x48002002 (8k pages) 652 */ 653#define REG_RX_PAGE_SIZE 0x4004 /* RX page size */ 654#define RX_PAGE_SIZE_MASK 0x00000003 /* size of pages pointed to 655 by receive descriptors. 656 if jumbo buffers are 657 supported the page size 658 should not be < 8k. 659 0b00 = 2k, 0b01 = 4k 660 0b10 = 8k, 0b11 = 16k 661 DEFAULT: 8k */ 662#define RX_PAGE_SIZE_SHIFT 0 663#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800 /* # of MTU buffers the hw 664 packs into a page. 665 DEFAULT: 4 */ 666#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11 667#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000 /* # of bytes that separate 668 each MTU buffer + 669 offset from each 670 other. 671 0b00 = 1k, 0b01 = 2k 672 0b10 = 4k, 0b11 = 8k 673 DEFAULT: 0x1 */ 674#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27 675#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000 /* offset in each page that 676 hw writes the MTU buffer 677 into. 678 0b00 = 0, 679 0b01 = 64 bytes 680 0b10 = 96, 0b11 = 128 681 DEFAULT: 0x1 */ 682#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30 683 684/* 11-bit counter points to next location in RX FIFO to be loaded/read. 685 * shadow write pointers enable retries in case of early receive aborts. 686 * DEFAULT: 0x0. generated on 64-bit boundaries. 687 */ 688#define REG_RX_FIFO_WRITE_PTR 0x4008 /* RX FIFO write pointer */ 689#define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */ 690#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010 /* RX IPP FIFO shadow write 691 pointer */ 692#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read 693 pointer */ 694#define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read 695 pointer. (8-bit counter) */ 696 697/* current state of RX DMA state engines + other info 698 * DEFAULT: 0x0 699 */ 700#define REG_RX_DEBUG 0x401C /* RX debug */ 701#define RX_DEBUG_LOAD_STATE_MASK 0x0000000F /* load state machine w/ MAC: 702 0x0 = idle, 0x1 = load_bop 703 0x2 = load 1, 0x3 = load 2 704 0x4 = load 3, 0x5 = load 4 705 0x6 = last detect 706 0x7 = wait req 707 0x8 = wait req statuss 1st 708 0x9 = load st 709 0xa = bubble mac 710 0xb = error */ 711#define RX_DEBUG_LM_STATE_MASK 0x00000070 /* load state machine w/ HP and 712 RX FIFO: 713 0x0 = idle, 0x1 = hp xfr 714 0x2 = wait hp ready 715 0x3 = wait flow code 716 0x4 = fifo xfer 717 0x5 = make status 718 0x6 = csum ready 719 0x7 = error */ 720#define RX_DEBUG_FC_STATE_MASK 0x000000180 /* flow control state machine 721 w/ MAC: 722 0x0 = idle 723 0x1 = wait xoff ack 724 0x2 = wait xon 725 0x3 = wait xon ack */ 726#define RX_DEBUG_DATA_STATE_MASK 0x000001E00 /* unload data state machine 727 states: 728 0x0 = idle data 729 0x1 = header begin 730 0x2 = xfer header 731 0x3 = xfer header ld 732 0x4 = mtu begin 733 0x5 = xfer mtu 734 0x6 = xfer mtu ld 735 0x7 = jumbo begin 736 0x8 = xfer jumbo 737 0x9 = xfer jumbo ld 738 0xa = reas begin 739 0xb = xfer reas 740 0xc = flush tag 741 0xd = xfer reas ld 742 0xe = error 743 0xf = bubble idle */ 744#define RX_DEBUG_DESC_STATE_MASK 0x0001E000 /* unload desc state machine 745 states: 746 0x0 = idle desc 747 0x1 = wait ack 748 0x9 = wait ack 2 749 0x2 = fetch desc 1 750 0xa = fetch desc 2 751 0x3 = load ptrs 752 0x4 = wait dma 753 0x5 = wait ack batch 754 0x6 = post batch 755 0x7 = xfr done */ 756#define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the 757 interrupt queue */ 758#define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000 /* interrupt write pointer 759 of the interrupt queue */ 760 761/* flow control frames are emitted using two PAUSE thresholds: 762 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg 763 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes. 764 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated 765 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames 766 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max 767 * value is 0x6F. 768 * DEFAULT: 0x00078 769 */ 770#define REG_RX_PAUSE_THRESH 0x4020 /* RX pause thresholds */ 771#define RX_PAUSE_THRESH_QUANTUM 64 772#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF /* XOFF PAUSE emitted when 773 RX FIFO occupancy > 774 value*64B */ 775#define RX_PAUSE_THRESH_OFF_SHIFT 0 776#define RX_PAUSE_THRESH_ON_MASK 0x001FF000 /* XON PAUSE emitted after 777 emitting XOFF PAUSE when RX 778 FIFO occupancy falls below 779 this value*64B. must be 780 < XOFF threshold. if = 781 RX_FIFO_SIZE< XON frames are 782 never emitted. */ 783#define RX_PAUSE_THRESH_ON_SHIFT 12 784 785/* 13-bit register used to control RX desc fetching and intr generation. if 4+ 786 * valid RX descriptors are available, Cassini will read 4 at a time. 787 * writing N means that all desc up to *but* excluding N are available. N must 788 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned. 789 * DEFAULT: 0 on reset 790 */ 791#define REG_RX_KICK 0x4024 /* RX kick reg */ 792 793/* 8KB aligned 64-bit pointer to the base of the RX free/completion rings. 794 * lower 13 bits of the low register are hard-wired to 0. 795 */ 796#define REG_RX_DB_LOW 0x4028 /* RX descriptor ring 797 base low */ 798#define REG_RX_DB_HI 0x402C /* RX descriptor ring 799 base hi */ 800#define REG_RX_CB_LOW 0x4030 /* RX completion ring 801 base low */ 802#define REG_RX_CB_HI 0x4034 /* RX completion ring 803 base hi */ 804/* 13-bit register indicate desc used by cassini for receive frames. used 805 * for diagnostic purposes. 806 * DEFAULT: 0 on reset 807 */ 808#define REG_RX_COMP 0x4038 /* (ro) RX completion */ 809 810/* HEAD and TAIL are used to control RX desc posting and interrupt 811 * generation. hw moves the head register to pass ownership to sw. sw 812 * moves the tail register to pass ownership back to hw. to give all 813 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no 814 * more entries are available, DMA will pause and an interrupt will be 815 * generated to indicate no more entries are available. sw can use 816 * this interrupt to reduce the # of times it must update the 817 * completion tail register. 818 * DEFAULT: 0 on reset 819 */ 820#define REG_RX_COMP_HEAD 0x403C /* RX completion head */ 821#define REG_RX_COMP_TAIL 0x4040 /* RX completion tail */ 822 823/* values used for receive interrupt blanking. loaded each time the ISR is read 824 * DEFAULT: 0x00000000 825 */ 826#define REG_RX_BLANK 0x4044 /* RX blanking register 827 for ISR read */ 828#define RX_BLANK_INTR_PKT_MASK 0x000001FF /* RX_DONE intr asserted if 829 this many sets of completion 830 writebacks (up to 2 packets) 831 occur since the last time 832 the ISR was read. 0 = no 833 packet blanking */ 834#define RX_BLANK_INTR_PKT_SHIFT 0 835#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000 /* RX_DONE interrupt asserted 836 if that many clocks were 837 counted since last time the 838 ISR was read. 839 each count is 512 core 840 clocks (125MHz). 0 = no 841 time blanking */ 842#define RX_BLANK_INTR_TIME_SHIFT 12 843 844/* values used for interrupt generation based on threshold values of how 845 * many free desc and completion entries are available for hw use. 846 * DEFAULT: 0x00000000 847 */ 848#define REG_RX_AE_THRESH 0x4048 /* RX almost empty 849 thresholds */ 850#define RX_AE_THRESH_FREE_MASK 0x00001FFF /* RX_BUF_AE will be 851 generated if # desc 852 avail for hw use <= 853 # */ 854#define RX_AE_THRESH_FREE_SHIFT 0 855#define RX_AE_THRESH_COMP_MASK 0x0FFFE000 /* RX_COMP_AE will be 856 generated if # of 857 completion entries 858 avail for hw use <= 859 # */ 860#define RX_AE_THRESH_COMP_SHIFT 13 861 862/* probabilities for random early drop (RED) thresholds on a FIFO threshold 863 * basis. probability should increase when the FIFO level increases. control 864 * packets are never dropped and not counted in stats. probability programmed 865 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped. 866 * DEFAULT: 0x00000000 867 */ 868#define REG_RX_RED 0x404C /* RX random early detect enable */ 869#define RX_RED_4K_6K_FIFO_MASK 0x000000FF /* 4KB < FIFO thresh < 6KB */ 870#define RX_RED_6K_8K_FIFO_MASK 0x0000FF00 /* 6KB < FIFO thresh < 8KB */ 871#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000 /* 8KB < FIFO thresh < 10KB */ 872#define RX_RED_10K_12K_FIFO_MASK 0xFF000000 /* 10KB < FIFO thresh < 12KB */ 873 874/* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO. 875 * RX control FIFO = # of packets in RX FIFO. 876 * DEFAULT: 0x0 877 */ 878#define REG_RX_FIFO_FULLNESS 0x4050 /* (ro) RX FIFO fullness */ 879#define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000 /* level w/ 8B granularity */ 880#define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00 /* level w/ 8B granularity */ 881#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF /* # packets in RX FIFO */ 882#define REG_RX_IPP_PACKET_COUNT 0x4054 /* RX IPP packet counter */ 883#define REG_RX_WORK_DMA_PTR_LOW 0x4058 /* RX working DMA ptr low */ 884#define REG_RX_WORK_DMA_PTR_HI 0x405C /* RX working DMA ptr 885 high */ 886 887/* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST 888 * START/COMPLETE is writeable. START will clear when the BIST has completed 889 * checking all 17 RAMS. 890 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0 891 */ 892#define REG_RX_BIST 0x4060 /* (ro) RX BIST */ 893#define RX_BIST_32A_PASS 0x80000000 /* RX FIFO 32A passed */ 894#define RX_BIST_33A_PASS 0x40000000 /* RX FIFO 33A passed */ 895#define RX_BIST_32B_PASS 0x20000000 /* RX FIFO 32B passed */ 896#define RX_BIST_33B_PASS 0x10000000 /* RX FIFO 33B passed */ 897#define RX_BIST_32C_PASS 0x08000000 /* RX FIFO 32C passed */ 898#define RX_BIST_33C_PASS 0x04000000 /* RX FIFO 33C passed */ 899#define RX_BIST_IPP_32A_PASS 0x02000000 /* RX IPP FIFO 33B passed */ 900#define RX_BIST_IPP_33A_PASS 0x01000000 /* RX IPP FIFO 33A passed */ 901#define RX_BIST_IPP_32B_PASS 0x00800000 /* RX IPP FIFO 32B passed */ 902#define RX_BIST_IPP_33B_PASS 0x00400000 /* RX IPP FIFO 33B passed */ 903#define RX_BIST_IPP_32C_PASS 0x00200000 /* RX IPP FIFO 32C passed */ 904#define RX_BIST_IPP_33C_PASS 0x00100000 /* RX IPP FIFO 33C passed */ 905#define RX_BIST_CTRL_32_PASS 0x00800000 /* RX CTRL FIFO 32 passed */ 906#define RX_BIST_CTRL_33_PASS 0x00400000 /* RX CTRL FIFO 33 passed */ 907#define RX_BIST_REAS_26A_PASS 0x00200000 /* RX Reas 26A passed */ 908#define RX_BIST_REAS_26B_PASS 0x00100000 /* RX Reas 26B passed */ 909#define RX_BIST_REAS_27_PASS 0x00080000 /* RX Reas 27 passed */ 910#define RX_BIST_STATE_MASK 0x00078000 /* BIST state machine */ 911#define RX_BIST_SUMMARY 0x00000002 /* when BIST complete, 912 summary pass bit 913 contains AND of BIST 914 results of all 16 915 RAMS */ 916#define RX_BIST_START 0x00000001 /* write 1 to start 917 BIST. self clears 918 on completion. */ 919 920/* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read 921 * from to retrieve packet control info. 922 * DEFAULT: 0 923 */ 924#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064 /* (ro) RX control FIFO 925 write ptr */ 926#define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read 927 ptr */ 928 929/* receive interrupt blanking. loaded each time interrupt alias register is 930 * read. 931 * DEFAULT: 0x0 932 */ 933#define REG_RX_BLANK_ALIAS_READ 0x406C /* RX blanking register for 934 alias read */ 935#define RX_BAR_INTR_PACKET_MASK 0x000001FF /* assert RX_DONE if # 936 completion writebacks 937 > # since last ISR 938 read. 0 = no 939 blanking. up to 2 940 packets per 941 completion wb. */ 942#define RX_BAR_INTR_TIME_MASK 0x3FFFF000 /* assert RX_DONE if # 943 clocks > # since last 944 ISR read. each count 945 is 512 core clocks 946 (125MHz). 0 = no 947 blanking. */ 948 949/* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed 950 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0 951 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset 952 * to normal operation after diagnostics, write to address location 0x0. 953 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should 954 * be the last write access of a write sequence. 955 * DEFAULT: undefined 956 */ 957#define REG_RX_FIFO_ADDR 0x4080 /* RX FIFO address */ 958#define REG_RX_FIFO_TAG 0x4084 /* RX FIFO tag */ 959#define REG_RX_FIFO_DATA_LOW 0x4088 /* RX FIFO data low */ 960#define REG_RX_FIFO_DATA_HI_T0 0x408C /* RX FIFO data high T0 */ 961#define REG_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data high T1 */ 962 963/* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of 964 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit 965 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control 966 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI 967 * should be last write access of the write sequence. 968 * DEFAULT: undefined 969 */ 970#define REG_RX_CTRL_FIFO_ADDR 0x4094 /* RX Control FIFO and 971 Batching FIFO addr */ 972#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098 /* RX Control FIFO data 973 low */ 974#define REG_RX_CTRL_FIFO_DATA_MID 0x409C /* RX Control FIFO data 975 mid */ 976#define REG_RX_CTRL_FIFO_DATA_HI 0x4100 /* RX Control FIFO data 977 hi and flow id */ 978#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001 /* upper bit of ctrl word */ 979#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E /* flow id */ 980 981/* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO. 982 * DEFAULT: undefined 983 */ 984#define REG_RX_IPP_FIFO_ADDR 0x4104 /* RX IPP FIFO address */ 985#define REG_RX_IPP_FIFO_TAG 0x4108 /* RX IPP FIFO tag */ 986#define REG_RX_IPP_FIFO_DATA_LOW 0x410C /* RX IPP FIFO data low */ 987#define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110 /* RX IPP FIFO data high 988 T0 */ 989#define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114 /* RX IPP FIFO data high 990 T1 */ 991 992/* 64-bit pointer to receive data buffer in host memory used for headers and 993 * small packets. MSB in high register. loaded by DMA state machine and 994 * increments as DMA writes receive data. only 50 LSB are incremented. top 995 * 13 bits taken from RX descriptor. 996 * DEFAULT: undefined 997 */ 998#define REG_RX_HEADER_PAGE_PTR_LOW 0x4118 /* (ro) RX header page ptr 999 low */ 1000#define REG_RX_HEADER_PAGE_PTR_HI 0x411C /* (ro) RX header page ptr 1001 high */ 1002#define REG_RX_MTU_PAGE_PTR_LOW 0x4120 /* (ro) RX MTU page pointer 1003 low */ 1004#define REG_RX_MTU_PAGE_PTR_HI 0x4124 /* (ro) RX MTU page pointer 1005 high */ 1006 1007/* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds 1008 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of 1009 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB. 1010 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set 1011 * to 0 for PIO access. DATA_HIGH should be last write of write sequence. 1012 * layout: 1013 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0] 1014 * DEFAULT: undefined 1015 */ 1016#define REG_RX_TABLE_ADDR 0x4128 /* RX reassembly DMA table 1017 address */ 1018#define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */ 1019 1020#define REG_RX_TABLE_DATA_LOW 0x412C /* RX reassembly DMA table 1021 data low */ 1022#define REG_RX_TABLE_DATA_MID 0x4130 /* RX reassembly DMA table 1023 data mid */ 1024#define REG_RX_TABLE_DATA_HI 0x4134 /* RX reassembly DMA table 1025 data high */ 1026 1027/* cassini+ only */ 1028/* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to 1029 * 0. same semantics as primary desc/complete rings. 1030 */ 1031#define REG_PLUS_RX_DB1_LOW 0x4200 /* RX descriptor ring 1032 2 base low */ 1033#define REG_PLUS_RX_DB1_HI 0x4204 /* RX descriptor ring 1034 2 base high */ 1035#define REG_PLUS_RX_CB1_LOW 0x4208 /* RX completion ring 1036 2 base low. 4 total */ 1037#define REG_PLUS_RX_CB1_HI 0x420C /* RX completion ring 1038 2 base high. 4 total */ 1039#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1)) 1040#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1)) 1041#define REG_PLUS_RX_KICK1 0x4220 /* RX Kick 2 register */ 1042#define REG_PLUS_RX_COMP1 0x4224 /* (ro) RX completion 2 1043 reg */ 1044#define REG_PLUS_RX_COMP1_HEAD 0x4228 /* (ro) RX completion 2 1045 head reg. 4 total. */ 1046#define REG_PLUS_RX_COMP1_TAIL 0x422C /* RX completion 2 1047 tail reg. 4 total. */ 1048#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1)) 1049#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1)) 1050#define REG_PLUS_RX_AE1_THRESH 0x4240 /* RX almost empty 2 1051 thresholds */ 1052#define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK 1053#define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT 1054 1055/** header parser registers **/ 1056 1057/* RX parser configuration register. 1058 * DEFAULT: 0x1651004 1059 */ 1060#define REG_HP_CFG 0x4140 /* header parser 1061 configuration reg */ 1062#define HP_CFG_PARSE_EN 0x00000001 /* enab header parsing */ 1063#define HP_CFG_NUM_CPU_MASK 0x000000FC /* # processors 1064 0 = 64. 0x3f = 63 */ 1065#define HP_CFG_NUM_CPU_SHIFT 2 1066#define HP_CFG_SYN_INC_MASK 0x00000100 /* SYN bit won't increment 1067 TCP seq # by one when 1068 stored in FDBM */ 1069#define HP_CFG_TCP_THRESH_MASK 0x000FFE00 /* # bytes of TCP data 1070 needed to be considered 1071 for reassembly */ 1072#define HP_CFG_TCP_THRESH_SHIFT 9 1073 1074/* access to RX Instruction RAM. 5-bit register/counter holds addr 1075 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI. 1076 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access 1077 * of sequence. 1078 * DEFAULT: undefined 1079 */ 1080#define REG_HP_INSTR_RAM_ADDR 0x4144 /* HP instruction RAM 1081 address */ 1082#define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */ 1083#define REG_HP_INSTR_RAM_DATA_LOW 0x4148 /* HP instruction RAM 1084 data low */ 1085#define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF 1086#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0 1087#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000 1088#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16 1089#define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000 1090#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20 1091#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000 1092#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22 1093#define REG_HP_INSTR_RAM_DATA_MID 0x414C /* HP instruction RAM 1094 data mid */ 1095#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003 1096#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0 1097#define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C 1098#define HP_INSTR_RAM_MID_OUTOP_SHIFT 2 1099#define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0 1100#define HP_INSTR_RAM_MID_FNEXT_SHIFT 6 1101#define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800 1102#define HP_INSTR_RAM_MID_FOFF_SHIFT 11 1103#define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000 1104#define HP_INSTR_RAM_MID_SNEXT_SHIFT 18 1105#define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000 1106#define HP_INSTR_RAM_MID_SOFF_SHIFT 23 1107#define HP_INSTR_RAM_MID_OP_MASK 0xC0000000 1108#define HP_INSTR_RAM_MID_OP_SHIFT 30 1109#define REG_HP_INSTR_RAM_DATA_HI 0x4150 /* HP instruction RAM 1110 data high */ 1111#define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF 1112#define HP_INSTR_RAM_HI_VAL_SHIFT 0 1113#define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000 1114#define HP_INSTR_RAM_HI_MASK_SHIFT 16 1115 1116/* PIO access into RX Header parser data RAM and flow database. 1117 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits. 1118 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM. 1119 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120] 1120 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access 1121 * flow database. 1122 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg 1123 * should be the last write access of the write sequence. 1124 * DEFAULT: undefined 1125 */ 1126#define REG_HP_DATA_RAM_FDB_ADDR 0x4154 /* HP data and FDB 1127 RAM address */ 1128#define HP_DATA_RAM_FDB_DATA_MASK 0x001F /* select 1 of 86 byte 1129 locations in header 1130 parser data ram to 1131 read/write */ 1132#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations 1133 in the flow database */ 1134#define REG_HP_DATA_RAM_DATA 0x4158 /* HP data RAM data */ 1135 1136/* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes 1137 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64] 1138 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0] 1139 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64] 1140 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0] 1141 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]} 1142 * FLOW_DB(10) = bit 0 has value for flow valid 1143 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0] 1144 */ 1145#define REG_HP_FLOW_DB0 0x415C /* HP flow database 1 reg */ 1146#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4) 1147 1148/* diagnostics for RX Header Parser block. 1149 * ASUN: the header parser state machine register is used for diagnostics 1150 * purposes. however, the spec doesn't have any details on it. 1151 */ 1152#define REG_HP_STATE_MACHINE 0x418C /* (ro) HP state machine */ 1153#define REG_HP_STATUS0 0x4190 /* (ro) HP status 1 */ 1154#define HP_STATUS0_SAP_MASK 0xFFFF0000 /* SAP */ 1155#define HP_STATUS0_L3_OFF_MASK 0x0000FE00 /* L3 offset */ 1156#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8 /* load balancing CPU 1157 number */ 1158#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007 /* HRP opcode */ 1159 1160#define REG_HP_STATUS1 0x4194 /* (ro) HP status 2 */ 1161#define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */ 1162#define HP_STATUS1_FLOWID_MASK 0x1F800000 /* flow id */ 1163#define HP_STATUS1_TCP_OFF_MASK 0x007F0000 /* tcp payload offset */ 1164#define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF /* tcp payload size */ 1165 1166#define REG_HP_STATUS2 0x4198 /* (ro) HP status 3 */ 1167#define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */ 1168#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000 /* checksum start 1169 start offset */ 1170#define HP_STATUS2_ACCUR1_MASK 0x000FE000 /* accu R1 */ 1171#define HP_STATUS2_FORCE_DROP 0x00001000 /* force drop */ 1172#define HP_STATUS2_BWO_REASSM 0x00000800 /* batching w/o 1173 reassembly */ 1174#define HP_STATUS2_JH_SPLIT_EN 0x00000400 /* jumbo header split 1175 enable */ 1176#define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload 1177 check */ 1178#define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length 1179 equal to zero */ 1180#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080 /* force tcp payload 1181 chk */ 1182#define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload 1183 threshold */ 1184#define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */ 1185#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010 /* control packet flag */ 1186#define HP_STATUS2_TCP_FLAG_CHECK 0x00000008 /* tcp flag check */ 1187#define HP_STATUS2_SYN_FLAG 0x00000004 /* syn flag */ 1188#define HP_STATUS2_TCP_CHECK 0x00000002 /* tcp payload chk */ 1189#define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */ 1190 1191/* BIST for header parser(HP) and flow database memories (FDBM). set _START 1192 * to start BIST. controller clears _START on completion. _START can also 1193 * be cleared to force termination of BIST. a bit set indicates that that 1194 * memory passed its BIST. 1195 */ 1196#define REG_HP_RAM_BIST 0x419C /* HP RAM BIST reg */ 1197#define HP_RAM_BIST_HP_DATA_PASS 0x80000000 /* HP data ram */ 1198#define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000 /* HP instr ram 0 */ 1199#define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000 /* HP instr ram 1 */ 1200#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000 /* HP instr ram 2 */ 1201#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000 /* FDBM aging RAM0 */ 1202#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000 /* FDBM aging RAM1 */ 1203#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000 /* FDBM flowid RAM0 1204 bank 0 */ 1205#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000 /* FDBM flowid RAM1 1206 bank 0 */ 1207#define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000 /* FDBM flowid RAM2 1208 bank 0 */ 1209#define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000 /* FDBM flowid RAM3 1210 bank 0 */ 1211#define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000 /* FDBM flowid RAM0 1212 bank 1 */ 1213#define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000 /* FDBM flowid RAM1 1214 bank 2 */ 1215#define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000 /* FDBM flowid RAM2 1216 bank 1 */ 1217#define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000 /* FDBM flowid RAM3 1218 bank 1 */ 1219#define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000 /* FDBM tcp sequence 1220 RAM */ 1221#define HP_RAM_BIST_SUMMARY 0x00000002 /* all BIST tests */ 1222#define HP_RAM_BIST_START 0x00000001 /* start/stop BIST */ 1223 1224 1225/** MAC registers. **/ 1226/* reset bits are set using a PIO write and self-cleared after the command 1227 * execution has completed. 1228 */ 1229#define REG_MAC_TX_RESET 0x6000 /* TX MAC software reset 1230 command (default: 0x0) */ 1231#define REG_MAC_RX_RESET 0x6004 /* RX MAC software reset 1232 command (default: 0x0) */ 1233/* execute a pause flow control frame transmission 1234 DEFAULT: 0x0XXXX */ 1235#define REG_MAC_SEND_PAUSE 0x6008 /* send pause command reg */ 1236#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF /* value of pause time 1237 to be sent on network 1238 in units of slot 1239 times */ 1240#define MAC_SEND_PAUSE_SEND 0x00010000 /* send pause flow ctrl 1241 frame on network */ 1242 1243/* bit set indicates that event occurred. auto-cleared when status register 1244 * is read and have corresponding mask bits in mask register. events will 1245 * trigger an interrupt if the corresponding mask bit is 0. 1246 * status register default: 0x00000000 1247 * mask register default = 0xFFFFFFFF on reset 1248 */ 1249#define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */ 1250#define MAC_TX_FRAME_XMIT 0x0001 /* successful frame 1251 transmision */ 1252#define MAC_TX_UNDERRUN 0x0002 /* terminated frame 1253 transmission due to 1254 data starvation in the 1255 xmit data path */ 1256#define MAC_TX_MAX_PACKET_ERR 0x0004 /* frame exceeds max allowed 1257 length passed to TX MAC 1258 by the DMA engine */ 1259#define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal 1260 collision counter */ 1261#define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive 1262 collision counter */ 1263#define MAC_TX_COLL_LATE 0x0020 /* rollover of the late 1264 collision counter */ 1265#define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first 1266 collision counter */ 1267#define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer 1268 timer */ 1269#define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak 1270 attempts counter */ 1271 1272#define REG_MAC_RX_STATUS 0x6014 /* RX MAC status reg */ 1273#define MAC_RX_FRAME_RECV 0x0001 /* successful receipt of 1274 a frame */ 1275#define MAC_RX_OVERFLOW 0x0002 /* dropped frame due to 1276 RX FIFO overflow */ 1277#define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame 1278 counter */ 1279#define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment 1280 error counter */ 1281#define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error 1282 counter */ 1283#define MAC_RX_LEN_ERR 0x0020 /* rollover of length 1284 error counter */ 1285#define MAC_RX_VIOL_ERR 0x0040 /* rollover of code 1286 violation error */ 1287 1288/* DEFAULT: 0xXXXX0000 on reset */ 1289#define REG_MAC_CTRL_STATUS 0x6018 /* MAC control status reg */ 1290#define MAC_CTRL_PAUSE_RECEIVED 0x00000001 /* successful 1291 reception of a 1292 pause control 1293 frame */ 1294#define MAC_CTRL_PAUSE_STATE 0x00000002 /* MAC has made a 1295 transition from 1296 "not paused" to 1297 "paused" */ 1298#define MAC_CTRL_NOPAUSE_STATE 0x00000004 /* MAC has made a 1299 transition from 1300 "paused" to "not 1301 paused" */ 1302#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000 /* value of pause time 1303 operand that was 1304 received in the last 1305 pause flow control 1306 frame */ 1307 1308/* layout identical to TX MAC[8:0] */ 1309#define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */ 1310/* layout identical to RX MAC[6:0] */ 1311#define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */ 1312/* layout identical to CTRL MAC[2:0] */ 1313#define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */ 1314 1315/* to ensure proper operation, CFG_EN must be cleared to 0 and a delay 1316 * imposed before writes to other bits in the TX_MAC_CFG register or any of 1317 * the MAC parameters is performed. delay dependent upon time required to 1318 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g., 1319 * the delay for a 1518-byte frame on a 100Mbps network is 125us. 1320 * alternatively, just poll TX_CFG_EN until it reads back as 0. 1321 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and 1322 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should 1323 * be 0x200 (slot time of 512 bytes) 1324 */ 1325#define REG_MAC_TX_CFG 0x6030 /* TX MAC config reg */ 1326#define MAC_TX_CFG_EN 0x0001 /* enable TX MAC. 0 will 1327 force TXMAC state 1328 machine to remain in 1329 idle state or to 1330 transition to idle state 1331 on completion of an 1332 ongoing packet. */ 1333#define MAC_TX_CFG_IGNORE_CARRIER 0x0002 /* disable CSMA/CD deferral 1334 process. set to 1 when 1335 full duplex and 0 when 1336 half duplex */ 1337#define MAC_TX_CFG_IGNORE_COLL 0x0004 /* disable CSMA/CD backoff 1338 algorithm. set to 1 when 1339 full duplex and 0 when 1340 half duplex */ 1341#define MAC_TX_CFG_IPG_EN 0x0008 /* enable extension of the 1342 Rx-to-TX IPG. after 1343 receiving a frame, TX 1344 MAC will reset its 1345 deferral process to 1346 carrier sense for the 1347 amount of time = IPG0 + 1348 IPG1 and commit to 1349 transmission for time 1350 specified in IPG2. when 1351 0 or when xmitting frames 1352 back-to-pack (Tx-to-Tx 1353 IPG), TX MAC ignores 1354 IPG0 and will only use 1355 IPG1 for deferral time. 1356 IPG2 still used. */ 1357#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010 /* TX MAC will not easily 1358 give up on frame 1359 xmission. if backoff 1360 algorithm reaches the 1361 ATTEMPT_LIMIT, it will 1362 clear attempts counter 1363 and continue trying to 1364 send the frame as 1365 specified by 1366 GIVE_UP_LIM. when 0, 1367 TX MAC will execute 1368 standard CSMA/CD prot. */ 1369#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020 /* when set, TX MAC will 1370 continue to try to xmit 1371 until successful. when 1372 0, TX MAC will continue 1373 to try xmitting until 1374 successful or backoff 1375 algorithm reaches 1376 ATTEMPT_LIMIT*16 */ 1377#define MAC_TX_CFG_NO_BACKOFF 0x0040 /* modify CSMA/CD to disable 1378 backoff algorithm. TX 1379 MAC will not back off 1380 after a xmission attempt 1381 that resulted in a 1382 collision. */ 1383#define MAC_TX_CFG_SLOW_DOWN 0x0080 /* modify CSMA/CD so that 1384 deferral process is reset 1385 in response to carrier 1386 sense during the entire 1387 duration of IPG. TX MAC 1388 will only commit to frame 1389 xmission after frame 1390 xmission has actually 1391 begun. */ 1392#define MAC_TX_CFG_NO_FCS 0x0100 /* TX MAC will not generate 1393 CRC for all xmitted 1394 packets. when clear, CRC 1395 generation is dependent 1396 upon NO_CRC bit in the 1397 xmit control word from 1398 TX DMA */ 1399#define MAC_TX_CFG_CARRIER_EXTEND 0x0200 /* enables xmit part of the 1400 carrier extension 1401 feature. this allows for 1402 longer collision domains 1403 by extending the carrier 1404 and collision window 1405 from the end of FCS until 1406 the end of the slot time 1407 if necessary. Required 1408 for half-duplex at 1Gbps, 1409 clear otherwise. */ 1410 1411/* when CRC is not stripped, reassembly packets will not contain the CRC. 1412 * these will be stripped by HRP because it reassembles layer 4 data, and the 1413 * CRC is layer 2. however, non-reassembly packets will still contain the CRC 1414 * when passed to the host. to ensure proper operation, need to wait 3.2ms 1415 * after clearing RX_CFG_EN before writing to any other RX MAC registers 1416 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears 1417 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same 1418 * restrictions as CFG_EN. 1419 */ 1420#define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */ 1421#define MAC_RX_CFG_EN 0x0001 /* enable RX MAC */ 1422#define MAC_RX_CFG_STRIP_PAD 0x0002 /* always program to 0. 1423 feature not supported */ 1424#define MAC_RX_CFG_STRIP_FCS 0x0004 /* RX MAC will strip the 1425 last 4 bytes of a 1426 received frame. */ 1427#define MAC_RX_CFG_PROMISC_EN 0x0008 /* promiscuous mode */ 1428#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010 /* accept all valid 1429 multicast frames (group 1430 bit in DA field set) */ 1431#define MAC_RX_CFG_HASH_FILTER_EN 0x0020 /* use hash table to filter 1432 multicast addresses */ 1433#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040 /* cause RX MAC to use 1434 address filtering regs 1435 to filter both unicast 1436 and multicast 1437 addresses */ 1438#define MAC_RX_CFG_DISABLE_DISCARD 0x0080 /* pass errored frames to 1439 RX DMA by setting BAD 1440 bit but not Abort bit 1441 in the status. CRC, 1442 framing, and length errs 1443 will not increment 1444 error counters. frames 1445 which don't match dest 1446 addr will be passed up 1447 w/ BAD bit set. */ 1448#define MAC_RX_CFG_CARRIER_EXTEND 0x0100 /* enable reception of 1449 packet bursts generated 1450 by carrier extension 1451 with packet bursting 1452 senders. only applies 1453 to half-duplex 1Gbps */ 1454 1455/* DEFAULT: 0x0 */ 1456#define REG_MAC_CTRL_CFG 0x6038 /* MAC control config reg */ 1457#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001 /* respond to requests for 1458 sending pause flow ctrl 1459 frames */ 1460#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002 /* respond to received 1461 pause flow ctrl frames */ 1462#define MAC_CTRL_CFG_PASS_CTRL 0x0004 /* pass valid MAC ctrl 1463 packets to RX DMA */ 1464 1465/* to ensure proper operation, a global initialization sequence should be 1466 * performed when a loopback config is entered or exited. if programmed after 1467 * a hw or global sw reset, RX/TX MAC software reset and initialization 1468 * should be done to ensure stable clocking. 1469 * DEFAULT: 0x0 1470 */ 1471#define REG_MAC_XIF_CFG 0x603C /* XIF config reg */ 1472#define MAC_XIF_TX_MII_OUTPUT_EN 0x0001 /* enable output drivers 1473 on MII xmit bus */ 1474#define MAC_XIF_MII_INT_LOOPBACK 0x0002 /* loopback GMII xmit data 1475 path to GMII recv data 1476 path. phy mode register 1477 clock selection must be 1478 set to GMII mode and 1479 GMII_MODE should be set 1480 to 1. in loopback mode, 1481 REFCLK will drive the 1482 entire mac core. 0 for 1483 normal operation. */ 1484#define MAC_XIF_DISABLE_ECHO 0x0004 /* disables receive data 1485 path during packet 1486 xmission. clear to 0 1487 in any full duplex mode, 1488 in any loopback mode, 1489 or in half-duplex SERDES 1490 or SLINK modes. set when 1491 in half-duplex when 1492 using external phy. */ 1493#define MAC_XIF_GMII_MODE 0x0008 /* MAC operates with GMII 1494 clocks and datapath */ 1495#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010 /* MII_BUF_EN pin. enable 1496 external tristate buffer 1497 on the MII receive 1498 bus. */ 1499#define MAC_XIF_LINK_LED 0x0020 /* LINKLED# active (low) */ 1500#define MAC_XIF_FDPLX_LED 0x0040 /* FDPLXLED# active (low) */ 1501 1502#define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg. 1503 recommended: 0x00 */ 1504#define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg 1505 recommended: 0x08 */ 1506#define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg 1507 recommended: 0x04 */ 1508#define REG_MAC_SLOT_TIME 0x604C /* slot time reg 1509 recommended: 0x40 */ 1510#define REG_MAC_FRAMESIZE_MIN 0x6050 /* min frame size reg 1511 recommended: 0x40 */ 1512 1513/* FRAMESIZE_MAX holds both the max frame size as well as the max burst size. 1514 * recommended value: 0x2000.05EE 1515 */ 1516#define REG_MAC_FRAMESIZE_MAX 0x6054 /* max frame size reg */ 1517#define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000 /* max burst size */ 1518#define MAC_FRAMESIZE_MAX_BURST_SHIFT 16 1519#define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF /* max frame size */ 1520#define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0 1521#define REG_MAC_PA_SIZE 0x6058 /* PA size reg. number of 1522 preamble bytes that the 1523 TX MAC will xmit at the 1524 beginning of each frame 1525 value should be 2 or 1526 greater. recommended 1527 value: 0x07 */ 1528#define REG_MAC_JAM_SIZE 0x605C /* jam size reg. duration 1529 of jam in units of media 1530 byte time. recommended 1531 value: 0x04 */ 1532#define REG_MAC_ATTEMPT_LIMIT 0x6060 /* attempt limit reg. # 1533 of attempts TX MAC will 1534 make to xmit a frame 1535 before it resets its 1536 attempts counter. after 1537 the limit has been 1538 reached, TX MAC may or 1539 may not drop the frame 1540 dependent upon value 1541 in TX_MAC_CFG. 1542 recommended 1543 value: 0x10 */ 1544#define REG_MAC_CTRL_TYPE 0x6064 /* MAC control type reg. 1545 type field of a MAC 1546 ctrl frame. recommended 1547 value: 0x8808 */ 1548 1549/* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes. 1550 * register contains comparison 1551 * 0 16 MSB of primary MAC addr [47:32] of DA field 1552 * 1 16 middle bits "" [31:16] of DA field 1553 * 2 16 LSB "" [15:0] of DA field 1554 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field 1555 * 4*x 16 middle bits "" [31:16] 1556 * 5*x 16 LSB "" [15:0] 1557 * 42 16 MSB of MAC CTRL addr [47:32] of DA. 1558 * 43 16 middle bits "" [31:16] 1559 * 44 16 LSB "" [15:0] 1560 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames. 1561 * if there is a match, MAC will set the bit for alternative address 1562 * filter pass [15] 1563 1564 * here is the map of registers given MAC address notation: a:b:c:d:e:f 1565 * ab cd ef 1566 * primary addr reg 2 reg 1 reg 0 1567 * alt addr 1 reg 5 reg 4 reg 3 1568 * alt addr x reg 5*x reg 4*x reg 3*x 1569 * ctrl addr reg 44 reg 43 reg 42 1570 */ 1571#define REG_MAC_ADDR0 0x6080 /* MAC address 0 reg */ 1572#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4) 1573#define REG_MAC_ADDR_FILTER0 0x614C /* address filter 0 reg 1574 [47:32] */ 1575#define REG_MAC_ADDR_FILTER1 0x6150 /* address filter 1 reg 1576 [31:16] */ 1577#define REG_MAC_ADDR_FILTER2 0x6154 /* address filter 2 reg 1578 [15:0] */ 1579#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158 /* address filter 2 and 1 1580 mask reg. 8-bit reg 1581 contains nibble mask for 1582 reg 2 and 1. */ 1583#define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask 1584 reg */ 1585 1586/* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes 1587 * 16-bit registers contain bits of the hash table. 1588 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)]. 1589 * e.g., 15 -> [15:0], 0 -> [255:240] 1590 */ 1591#define REG_MAC_HASH_TABLE0 0x6160 /* hash table 0 reg */ 1592#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4) 1593 1594/* statistics registers. these registers generate an interrupt on 1595 * overflow. recommended initialization: 0x0000. most are 16-bits except 1596 * for PEAK_ATTEMPTS register which is 8 bits. 1597 */ 1598#define REG_MAC_COLL_NORMAL 0x61A0 /* normal collision 1599 counter. */ 1600#define REG_MAC_COLL_FIRST 0x61A4 /* first attempt 1601 successful collision 1602 counter */ 1603#define REG_MAC_COLL_EXCESS 0x61A8 /* excessive collision 1604 counter */ 1605#define REG_MAC_COLL_LATE 0x61AC /* late collision counter */ 1606#define REG_MAC_TIMER_DEFER 0x61B0 /* defer timer. time base 1607 is the media byte 1608 clock/256 */ 1609#define REG_MAC_ATTEMPTS_PEAK 0x61B4 /* peak attempts reg */ 1610#define REG_MAC_RECV_FRAME 0x61B8 /* receive frame counter */ 1611#define REG_MAC_LEN_ERR 0x61BC /* length error counter */ 1612#define REG_MAC_ALIGN_ERR 0x61C0 /* alignment error counter */ 1613#define REG_MAC_FCS_ERR 0x61C4 /* FCS error counter */ 1614#define REG_MAC_RX_CODE_ERR 0x61C8 /* RX code violation 1615 error counter */ 1616 1617/* misc registers */ 1618#define REG_MAC_RANDOM_SEED 0x61CC /* random number seed reg. 1619 10-bit register used as a 1620 seed for the random number 1621 generator for the CSMA/CD 1622 backoff algorithm. only 1623 programmed after power-on 1624 reset and should be a 1625 random value which has a 1626 high likelihood of being 1627 unique for each MAC 1628 attached to a network 1629 segment (e.g., 10 LSB of 1630 MAC address) */ 1631 1632/* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address 1633 * map 1634 */ 1635 1636/* 27-bit register has the current state for key state machines in the MAC */ 1637#define REG_MAC_STATE_MACHINE 0x61D0 /* (ro) state machine reg */ 1638#define MAC_SM_RLM_MASK 0x07800000 1639#define MAC_SM_RLM_SHIFT 23 1640#define MAC_SM_RX_FC_MASK 0x00700000 1641#define MAC_SM_RX_FC_SHIFT 20 1642#define MAC_SM_TLM_MASK 0x000F0000 1643#define MAC_SM_TLM_SHIFT 16 1644#define MAC_SM_ENCAP_SM_MASK 0x0000F000 1645#define MAC_SM_ENCAP_SM_SHIFT 12 1646#define MAC_SM_TX_REQ_MASK 0x00000C00 1647#define MAC_SM_TX_REQ_SHIFT 10 1648#define MAC_SM_TX_FC_MASK 0x000003C0 1649#define MAC_SM_TX_FC_SHIFT 6 1650#define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038 1651#define MAC_SM_FIFO_WRITE_SEL_SHIFT 3 1652#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007 1653#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0 1654 1655/** MIF registers. the MIF can be programmed in either bit-bang or 1656 * frame mode. 1657 **/ 1658#define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock. 1659 1 -> 0 will generate a 1660 rising edge. 0 -> 1 will 1661 generate a falling edge. */ 1662#define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit 1663 register generates data */ 1664#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output 1665 enable. enable when 1666 xmitting data from MIF to 1667 transceiver. */ 1668 1669/* 32-bit register serves as an instruction register when the MIF is 1670 * programmed in frame mode. load this register w/ a valid instruction 1671 * (as per IEEE 802.3u MII spec). poll this register to check for instruction 1672 * execution completion. during a read operation, this register will also 1673 * contain the 16-bit data returned by the tranceiver. unless specified 1674 * otherwise, fields are considered "don't care" when polling for 1675 * completion. 1676 */ 1677#define REG_MIF_FRAME 0x620C /* MIF frame/output reg */ 1678#define MIF_FRAME_START_MASK 0xC0000000 /* start of frame. 1679 load w/ 01 when 1680 issuing an instr */ 1681#define MIF_FRAME_ST 0x40000000 /* STart of frame */ 1682#define MIF_FRAME_OPCODE_MASK 0x30000000 /* opcode. 01 for a 1683 write. 10 for a 1684 read */ 1685#define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */ 1686#define MIF_FRAME_OP_WRITE 0x10000000 /* write OPcode */ 1687#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000 /* phy address. when 1688 issuing an instr, 1689 this field should be 1690 loaded w/ the XCVR 1691 addr */ 1692#define MIF_FRAME_PHY_ADDR_SHIFT 23 1693#define MIF_FRAME_REG_ADDR_MASK 0x007C0000 /* register address. 1694 when issuing an instr, 1695 addr of register 1696 to be read/written */ 1697#define MIF_FRAME_REG_ADDR_SHIFT 18 1698#define MIF_FRAME_TURN_AROUND_MSB 0x00020000 /* turn around, MSB. 1699 when issuing an instr, 1700 set this bit to 1 */ 1701#define MIF_FRAME_TURN_AROUND_LSB 0x00010000 /* turn around, LSB. 1702 when issuing an instr, 1703 set this bit to 0. 1704 when polling for 1705 completion, 1 means 1706 that instr execution 1707 has been completed */ 1708#define MIF_FRAME_DATA_MASK 0x0000FFFF /* instruction payload 1709 load with 16-bit data 1710 to be written in 1711 transceiver reg for a 1712 write. doesn't matter 1713 in a read. when 1714 polling for 1715 completion, field is 1716 "don't care" for write 1717 and 16-bit data 1718 returned by the 1719 transceiver for a 1720 read (if valid bit 1721 is set) */ 1722#define REG_MIF_CFG 0x6210 /* MIF config reg */ 1723#define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1 1724 0 -> select MDIO_0 */ 1725#define MIF_CFG_POLL_EN 0x0002 /* enable polling 1726 mechanism. if set, 1727 BB_MODE should be 0 */ 1728#define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode 1729 0 -> frame mode */ 1730#define MIF_CFG_POLL_REG_MASK 0x00F8 /* register address to be 1731 used by polling mode. 1732 only meaningful if POLL_EN 1733 is set to 1 */ 1734#define MIF_CFG_POLL_REG_SHIFT 3 1735#define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose. 1736 when MDIO_0 is idle, 1737 1 -> tranceiver is 1738 connected to MDIO_0. 1739 when MIF is communicating 1740 w/ MDIO_0 in bit-bang 1741 mode, this bit indicates 1742 the incoming bit stream 1743 during a read op */ 1744#define MIF_CFG_MDIO_1 0x0200 /* (ro) dual purpose. 1745 when MDIO_1 is idle, 1746 1 -> transceiver is 1747 connected to MDIO_1. 1748 when MIF is communicating 1749 w/ MDIO_1 in bit-bang 1750 mode, this bit indicates 1751 the incoming bit stream 1752 during a read op */ 1753#define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to 1754 be polled */ 1755#define MIF_CFG_POLL_PHY_SHIFT 10 1756 1757/* 16-bit register used to determine which bits in the POLL_STATUS portion of 1758 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0, 1759 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when 1760 * set. DEFAULT: 0xFFFF 1761 */ 1762#define REG_MIF_MASK 0x6214 /* MIF mask reg */ 1763 1764/* 32-bit register used when in poll mode. auto-cleared after being read */ 1765#define REG_MIF_STATUS 0x6218 /* MIF status reg */ 1766#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000 /* poll data contains 1767 the "latest image" 1768 update of the XCVR 1769 reg being read */ 1770#define MIF_STATUS_POLL_DATA_SHIFT 16 1771#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF /* poll status indicates 1772 which bits in the 1773 POLL_DATA field have 1774 changed since the 1775 MIF_STATUS reg was 1776 last read */ 1777#define MIF_STATUS_POLL_STATUS_SHIFT 0 1778 1779/* 7-bit register has current state for all state machines in the MIF */ 1780#define REG_MIF_STATE_MACHINE 0x621C /* MIF state machine reg */ 1781#define MIF_SM_CONTROL_MASK 0x07 /* control state machine 1782 state */ 1783#define MIF_SM_EXECUTION_MASK 0x60 /* execution state machine 1784 state */ 1785 1786/** PCS/Serialink. the following registers are equivalent to the standard 1787 * MII management registers except that they're directly mapped in 1788 * Cassini's register space. 1789 **/ 1790 1791/* the auto-negotiation enable bit should be programmed the same at 1792 * the link partner as in the local device to enable auto-negotiation to 1793 * complete. when that bit is reprogrammed, auto-neg/manual config is 1794 * restarted automatically. 1795 * DEFAULT: 0x1040 1796 */ 1797#define REG_PCS_MII_CTRL 0x9000 /* PCS MII control reg */ 1798#define PCS_MII_CTRL_1000_SEL 0x0040 /* reads 1. ignored on 1799 writes */ 1800#define PCS_MII_CTRL_COLLISION_TEST 0x0080 /* COL signal at the PCS 1801 to MAC interface is 1802 activated regardless 1803 of activity */ 1804#define PCS_MII_CTRL_DUPLEX 0x0100 /* forced 0x0. PCS 1805 behaviour same for 1806 half and full dplx */ 1807#define PCS_MII_RESTART_AUTONEG 0x0200 /* self clearing. 1808 restart auto- 1809 negotiation */ 1810#define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored 1811 on writes */ 1812#define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored 1813 on writes */ 1814#define PCS_MII_AUTONEG_EN 0x1000 /* default 1. PCS goes 1815 through automatic 1816 link config before it 1817 can be used. when 0, 1818 link can be used 1819 w/out any link config 1820 phase */ 1821#define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on 1822 writes */ 1823#define PCS_MII_RESET 0x8000 /* reset PCS. self-clears 1824 when done */ 1825 1826/* DEFAULT: 0x0108 */ 1827#define REG_PCS_MII_STATUS 0x9004 /* PCS MII status reg */ 1828#define PCS_MII_STATUS_EXTEND_CAP 0x0001 /* reads 0 */ 1829#define PCS_MII_STATUS_JABBER_DETECT 0x0002 /* reads 0 */ 1830#define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up. 1831 0 -> link down. 0 is 1832 latched so that 0 is 1833 kept until read. read 1834 2x to determine if the 1835 link has gone up again */ 1836#define PCS_MII_STATUS_AUTONEG_ABLE 0x0008 /* reads 1 (able to perform 1837 auto-neg) */ 1838#define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected 1839 from received link code 1840 word. only valid after 1841 auto-neg completed */ 1842#define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation 1843 completed 1844 0 -> auto-negotiation not 1845 completed */ 1846#define PCS_MII_STATUS_EXTEND_STATUS 0x0100 /* reads as 1. used as an 1847 indication that this is 1848 a 1000 Base-X PHY. writes 1849 to it are ignored */ 1850 1851/* used during auto-negotiation. 1852 * DEFAULT: 0x00E0 1853 */ 1854#define REG_PCS_MII_ADVERT 0x9008 /* PCS MII advertisement 1855 reg */ 1856#define PCS_MII_ADVERT_FD 0x0020 /* advertise full duplex 1857 1000 Base-X */ 1858#define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex 1859 1000 Base-X */ 1860#define PCS_MII_ADVERT_SYM_PAUSE 0x0080 /* advertise PAUSE 1861 symmetric capability */ 1862#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100 /* advertises PAUSE 1863 asymmetric capability */ 1864#define PCS_MII_ADVERT_RF_MASK 0x3000 /* remote fault. write bit13 1865 to optionally indicate to 1866 link partner that chip is 1867 going off-line. bit12 will 1868 get set when signal 1869 detect == FAIL and will 1870 remain set until 1871 successful negotiation */ 1872#define PCS_MII_ADVERT_ACK 0x4000 /* (ro) */ 1873#define PCS_MII_ADVERT_NEXT_PAGE 0x8000 /* (ro) forced 0x0 */ 1874 1875/* contents updated as a result of autonegotiation. layout and definitions 1876 * identical to PCS_MII_ADVERT 1877 */ 1878#define REG_PCS_MII_LPA 0x900C /* PCS MII link partner 1879 ability reg */ 1880#define PCS_MII_LPA_FD PCS_MII_ADVERT_FD 1881#define PCS_MII_LPA_HD PCS_MII_ADVERT_HD 1882#define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE 1883#define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE 1884#define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK 1885#define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK 1886#define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE 1887 1888/* DEFAULT: 0x0 */ 1889#define REG_PCS_CFG 0x9010 /* PCS config reg */ 1890#define PCS_CFG_EN 0x01 /* enable PCS. must be 1891 0 when modifying 1892 PCS_MII_ADVERT */ 1893#define PCS_CFG_SD_OVERRIDE 0x02 /* sets signal detect to 1894 OK. bit is 1895 non-resettable */ 1896#define PCS_CFG_SD_ACTIVE_LOW 0x04 /* changes interpretation 1897 of optical signal to make 1898 signal detect okay when 1899 signal is low */ 1900#define PCS_CFG_JITTER_STUDY_MASK 0x18 /* used to make jitter 1901 measurements. a single 1902 code group is xmitted 1903 regularly. 1904 0x0 = normal operation 1905 0x1 = high freq test 1906 pattern, D21.5 1907 0x2 = low freq test 1908 pattern, K28.7 1909 0x3 = reserved */ 1910#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto- 1911 negotiation timer to 1912 a few cycles for test 1913 purposes */ 1914 1915/* used for diagnostic purposes. bits 20-22 autoclear on read */ 1916#define REG_PCS_STATE_MACHINE 0x9014 /* (ro) PCS state machine 1917 and diagnostic reg */ 1918#define PCS_SM_TX_STATE_MASK 0x0000000F /* 0 and 1 indicate 1919 xmission of idle. 1920 otherwise, xmission of 1921 a packet */ 1922#define PCS_SM_RX_STATE_MASK 0x000000F0 /* 0 indicates reception 1923 of idle. otherwise, 1924 reception of packet */ 1925#define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700 /* 0 indicates loss of 1926 sync */ 1927#define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3 1928 indicates reception of 1929 Config codes. cycling 1930 through 0-1 indicates 1931 reception of idles */ 1932#define PCS_SM_LINK_STATE_MASK 0x0001E000 1933#define SM_LINK_STATE_UP 0x00016000 /* link state is up */ 1934 1935#define PCS_SM_LOSS_LINK_C 0x00100000 /* loss of link due to 1936 recept of Config 1937 codes */ 1938#define PCS_SM_LOSS_LINK_SYNC 0x00200000 /* loss of link due to 1939 loss of sync */ 1940#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000 /* signal detect goes 1941 from OK to FAIL. bit29 1942 will also be set if 1943 this is set */ 1944#define PCS_SM_NO_LINK_BREAKLINK 0x01000000 /* link not up due to 1945 receipt of breaklink 1946 C codes from partner. 1947 C codes w/ 0 content 1948 received triggering 1949 start/restart of 1950 autonegotiation. 1951 should be sent for 1952 no longer than 20ms */ 1953#define PCS_SM_NO_LINK_SERDES 0x02000000 /* serdes being 1954 initialized. see serdes 1955 state reg */ 1956#define PCS_SM_NO_LINK_C 0x04000000 /* C codes not stable or 1957 not received */ 1958#define PCS_SM_NO_LINK_SYNC 0x08000000 /* word sync not 1959 achieved */ 1960#define PCS_SM_NO_LINK_WAIT_C 0x10000000 /* waiting for C codes 1961 w/ ack bit set */ 1962#define PCS_SM_NO_LINK_NO_IDLE 0x20000000 /* link partner continues 1963 to send C codes 1964 instead of idle 1965 symbols or pkt data */ 1966 1967/* this register indicates interrupt changes in specific PCS MII status bits. 1968 * PCS_INT may be masked at the ISR level. only a single bit is implemented 1969 * for link status change. 1970 */ 1971#define REG_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */ 1972#define PCS_INTR_STATUS_LINK_CHANGE 0x04 /* link status has changed 1973 since last read */ 1974 1975/* control which network interface is used. no more than one bit should 1976 * be set. 1977 * DEFAULT: none 1978 */ 1979#define REG_PCS_DATAPATH_MODE 0x9050 /* datapath mode reg */ 1980#define PCS_DATAPATH_MODE_MII 0x00 /* PCS is not used and 1981 MII/GMII is selected. 1982 selection between MII and 1983 GMII is controlled by 1984 XIF_CFG */ 1985#define PCS_DATAPATH_MODE_SERDES 0x02 /* PCS is used via the 1986 10-bit interface */ 1987 1988/* input to serdes chip or serialink block */ 1989#define REG_PCS_SERDES_CTRL 0x9054 /* serdes control reg */ 1990#define PCS_SERDES_CTRL_LOOPBACK 0x01 /* enable loopback on 1991 serdes interface */ 1992#define PCS_SERDES_CTRL_SYNCD_EN 0x02 /* enable sync carrier 1993 detection. should be 1994 0x0 for normal 1995 operation */ 1996#define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1] 1997 to REFCLK when set. 1998 when clear, receiver 1999 clock locks to incoming 2000 serial data */ 2001 2002/* multiplex test outputs into the PROM address (PA_3 through PA_0) pins. 2003 * should be 0x0 for normal operations. 2004 * 0b000 normal operation, PROM address[3:0] selected 2005 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read 2006 * 0b010 rxmac req, rx ack, rx tag, rx clk shared 2007 * 0b011 txmac req, tx ack, tx tag, tx retry req 2008 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0 2009 * 0b101 R period RX, R period TX, R period HP, R period BIM 2010 * DEFAULT: 0x0 2011 */ 2012#define REG_PCS_SHARED_OUTPUT_SEL 0x9058 /* shared output select */ 2013#define PCS_SOS_PROM_ADDR_MASK 0x0007 2014 2015/* used for diagnostics. this register indicates progress of the SERDES 2016 * boot up. 2017 * 0b00 undergoing reset 2018 * 0b01 waiting 500us while lockrefn is asserted 2019 * 0b10 waiting for comma detect 2020 * 0b11 receive data is synchronized 2021 * DEFAULT: 0x0 2022 */ 2023#define REG_PCS_SERDES_STATE 0x905C /* (ro) serdes state */ 2024#define PCS_SERDES_STATE_MASK 0x03 2025 2026/* used for diagnostics. indicates number of packets transmitted or received. 2027 * counters rollover w/out generating an interrupt. 2028 * DEFAULT: 0x0 2029 */ 2030#define REG_PCS_PACKET_COUNT 0x9060 /* (ro) PCS packet counter */ 2031#define PCS_PACKET_COUNT_TX 0x000007FF /* pkts xmitted by PCS */ 2032#define PCS_PACKET_COUNT_RX 0x07FF0000 /* pkts recvd by PCS 2033 whether they 2034 encountered an error 2035 or not */ 2036 2037/** LocalBus Devices. the following provides run-time access to the 2038 * Cassini's PROM 2039 ***/ 2040#define REG_EXPANSION_ROM_RUN_START 0x100000 /* expansion rom run time 2041 access */ 2042#define REG_EXPANSION_ROM_RUN_END 0x17FFFF 2043 2044#define REG_SECOND_LOCALBUS_START 0x180000 /* secondary local bus 2045 device */ 2046#define REG_SECOND_LOCALBUS_END 0x1FFFFF 2047 2048/* entropy device */ 2049#define REG_ENTROPY_START REG_SECOND_LOCALBUS_START 2050#define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00) 2051#define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04) 2052#define ENTROPY_STATUS_DRDY 0x01 2053#define ENTROPY_STATUS_BUSY 0x02 2054#define ENTROPY_STATUS_CIPHER 0x04 2055#define ENTROPY_STATUS_BYPASS_MASK 0x18 2056#define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05) 2057#define ENTROPY_MODE_KEY_MASK 0x07 2058#define ENTROPY_MODE_ENCRYPT 0x40 2059#define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06) 2060#define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07) 2061#define ENTROPY_RESET_DES_IO 0x01 2062#define ENTROPY_RESET_STC_MODE 0x02 2063#define ENTROPY_RESET_KEY_CACHE 0x04 2064#define ENTROPY_RESET_IV 0x08 2065#define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08) 2066#define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10) 2067#define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x)) 2068 2069/* phys of interest w/ their special mii registers */ 2070#define PHY_LUCENT_B0 0x00437421 2071#define LUCENT_MII_REG 0x1F 2072 2073#define PHY_NS_DP83065 0x20005c78 2074#define DP83065_MII_MEM 0x16 2075#define DP83065_MII_REGD 0x1D 2076#define DP83065_MII_REGE 0x1E 2077 2078#define PHY_BROADCOM_5411 0x00206071 2079#define PHY_BROADCOM_B0 0x00206050 2080#define BROADCOM_MII_REG4 0x14 2081#define BROADCOM_MII_REG5 0x15 2082#define BROADCOM_MII_REG7 0x17 2083#define BROADCOM_MII_REG8 0x18 2084 2085#define CAS_MII_ANNPTR 0x07 2086#define CAS_MII_ANNPRR 0x08 2087#define CAS_MII_1000_CTRL 0x09 2088#define CAS_MII_1000_STATUS 0x0A 2089#define CAS_MII_1000_EXTEND 0x0F 2090 2091#define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */ 2092/* 2093 * if autoneg is disabled, here's the table: 2094 * BMCR_SPEED100 = 100Mbps 2095 * BMCR_SPEED1000 = 1000Mbps 2096 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps 2097 */ 2098#define CAS_BMCR_SPEED1000 0x0040 /* Select 1000Mbps */ 2099 2100#define CAS_ADVERTISE_1000HALF 0x0100 2101#define CAS_ADVERTISE_1000FULL 0x0200 2102#define CAS_ADVERTISE_PAUSE 0x0400 2103#define CAS_ADVERTISE_ASYM_PAUSE 0x0800 2104 2105/* regular lpa register */ 2106#define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE 2107#define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE 2108 2109/* 1000_STATUS register */ 2110#define CAS_LPA_1000HALF 0x0400 2111#define CAS_LPA_1000FULL 0x0800 2112 2113#define CAS_EXTEND_1000XFULL 0x8000 2114#define CAS_EXTEND_1000XHALF 0x4000 2115#define CAS_EXTEND_1000TFULL 0x2000 2116#define CAS_EXTEND_1000THALF 0x1000 2117 2118/* cassini header parser firmware */ 2119typedef struct cas_hp_inst { 2120 const char *note; 2121 2122 u16 mask, val; 2123 2124 u8 op; 2125 u8 soff, snext; /* if match succeeds, new offset and match */ 2126 u8 foff, fnext; /* if match fails, new offset and match */ 2127 /* output info */ 2128 u8 outop; /* output opcode */ 2129 2130 u16 outarg; /* output argument */ 2131 u8 outenab; /* output enable: 0 = not, 1 = if match 2132 2 = if !match, 3 = always */ 2133 u8 outshift; /* barrel shift right, 4 bits */ 2134 u16 outmask; 2135} cas_hp_inst_t; 2136 2137/* comparison */ 2138#define OP_EQ 0 /* packet == value */ 2139#define OP_LT 1 /* packet < value */ 2140#define OP_GT 2 /* packet > value */ 2141#define OP_NP 3 /* new packet */ 2142 2143/* output opcodes */ 2144#define CL_REG 0 2145#define LD_FID 1 2146#define LD_SEQ 2 2147#define LD_CTL 3 2148#define LD_SAP 4 2149#define LD_R1 5 2150#define LD_L3 6 2151#define LD_SUM 7 2152#define LD_HDR 8 2153#define IM_FID 9 2154#define IM_SEQ 10 2155#define IM_SAP 11 2156#define IM_R1 12 2157#define IM_CTL 13 2158#define LD_LEN 14 2159#define ST_FLG 15 2160 2161/* match setp #s for IP4TCP4 */ 2162#define S1_PCKT 0 2163#define S1_VLAN 1 2164#define S1_CFI 2 2165#define S1_8023 3 2166#define S1_LLC 4 2167#define S1_LLCc 5 2168#define S1_IPV4 6 2169#define S1_IPV4c 7 2170#define S1_IPV4F 8 2171#define S1_TCP44 9 2172#define S1_IPV6 10 2173#define S1_IPV6L 11 2174#define S1_IPV6c 12 2175#define S1_TCP64 13 2176#define S1_TCPSQ 14 2177#define S1_TCPFG 15 2178#define S1_TCPHL 16 2179#define S1_TCPHc 17 2180#define S1_CLNP 18 2181#define S1_CLNP2 19 2182#define S1_DROP 20 2183#define S2_HTTP 21 2184#define S1_ESP4 22 2185#define S1_AH4 23 2186#define S1_ESP6 24 2187#define S1_AH6 25 2188 2189#define CAS_PROG_IP46TCP4_PREAMBLE \ 2190{ "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \ 2191 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \ 2192{ "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \ 2193 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \ 2194{ "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \ 2195 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2196{ "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \ 2197 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2198{ "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \ 2199 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2200{ "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \ 2201 CL_REG, 0x000, 0, 0x0, 0x0000}, \ 2202{ "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \ 2203 LD_SAP, 0x100, 3, 0x0, 0xffff}, \ 2204{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \ 2205 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \ 2206{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \ 2207 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \ 2208{ "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \ 2209 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ \ 2210{ "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \ 2211 LD_SUM, 0x015, 1, 0x0, 0x0000}, \ 2212{ "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \ 2213 IM_R1, 0x128, 1, 0x0, 0xffff}, \ 2214{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \ 2215 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ \ 2216{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \ 2217 LD_LEN, 0x03f, 1, 0x0, 0xffff} 2218 2219#ifdef USE_HP_IP46TCP4 2220static cas_hp_inst_t cas_prog_ip46tcp4tab[] = { 2221 CAS_PROG_IP46TCP4_PREAMBLE, 2222 { "TCP seq", /* DADDR should point to dest port */ 2223 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 2224 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2225 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2226 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2227 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, 2228 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, 2229 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2230 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2231 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2232 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2233 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2234 IM_CTL, 0x000, 0, 0x0, 0x0000}, 2235 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2236 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2237 { NULL }, 2238}; 2239#ifdef HP_IP46TCP4_DEFAULT 2240#define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab 2241#endif 2242#endif 2243 2244/* 2245 * Alternate table load which excludes HTTP server traffic from reassembly. 2246 * It is substantially similar to the basic table, with one extra state 2247 * and a few extra compares. */ 2248#ifdef USE_HP_IP46TCP4NOHTTP 2249static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = { 2250 CAS_PROG_IP46TCP4_PREAMBLE, 2251 { "TCP seq", /* DADDR should point to dest port */ 2252 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 2253 0x081, 3, 0x0, 0xffff} , /* Load TCP seq # */ 2254 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, 2255 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, }, /* Load TCP flags */ 2256 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2257 LD_R1, 0x205, 3, 0xB, 0xf000}, 2258 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2259 LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2260 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2261 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2262 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2263 CL_REG, 0x002, 3, 0x0, 0x0000}, 2264 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2265 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2266 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2267 IM_CTL, 0x044, 3, 0x0, 0xffff}, 2268 { NULL }, 2269}; 2270#ifdef HP_IP46TCP4NOHTTP_DEFAULT 2271#define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab 2272#endif 2273#endif 2274 2275/* match step #s for IP4FRAG */ 2276#define S3_IPV6c 11 2277#define S3_TCP64 12 2278#define S3_TCPSQ 13 2279#define S3_TCPFG 14 2280#define S3_TCPHL 15 2281#define S3_TCPHc 16 2282#define S3_FRAG 17 2283#define S3_FOFF 18 2284#define S3_CLNP 19 2285 2286#ifdef USE_HP_IP4FRAG 2287static cas_hp_inst_t cas_prog_ip4fragtab[] = { 2288 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, 2289 CL_REG, 0x3ff, 1, 0x0, 0x0000}, 2290 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2291 IM_CTL, 0x00a, 3, 0x0, 0xffff}, 2292 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023, 2293 CL_REG, 0x000, 0, 0x0, 0x0000}, 2294 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2295 CL_REG, 0x000, 0, 0x0, 0x0000}, 2296 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP, 2297 CL_REG, 0x000, 0, 0x0, 0x0000}, 2298 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP, 2299 CL_REG, 0x000, 0, 0x0, 0x0000}, 2300 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2301 LD_SAP, 0x100, 3, 0x0, 0xffff}, 2302 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP, 2303 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2304 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG, 2305 LD_LEN, 0x03e, 3, 0x0, 0xffff}, 2306 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP, 2307 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2308 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP, 2309 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2310 { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP, 2311 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2312 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP, 2313 LD_LEN, 0x03f, 1, 0x0, 0xffff}, 2314 { "TCP seq", /* DADDR should point to dest port */ 2315 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ, 2316 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2317 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0, 2318 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2319 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc, 2320 LD_R1, 0x205, 3, 0xB, 0xf000}, 2321 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2322 LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2323 { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, 2324 LD_FID, 0x103, 3, 0x0, 0xffff}, /* FID IP4 src+dst */ 2325 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF, 2326 LD_SEQ, 0x040, 1, 0xD, 0xfff8}, 2327 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2328 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2329 { NULL }, 2330}; 2331#ifdef HP_IP4FRAG_DEFAULT 2332#define CAS_HP_FIRMWARE cas_prog_ip4fragtab 2333#endif 2334#endif 2335 2336/* 2337 * Alternate table which does batching without reassembly 2338 */ 2339#ifdef USE_HP_IP46TCP4BATCH 2340static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = { 2341 CAS_PROG_IP46TCP4_PREAMBLE, 2342 { "TCP seq", /* DADDR should point to dest port */ 2343 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ, 2344 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2345 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2346 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000}, /* Load TCP flags */ 2347 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, 2348 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000}, 2349 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2350 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff}, /* set batch bit */ 2351 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2352 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2353 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2354 S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff}, 2355 { NULL }, 2356}; 2357#ifdef HP_IP46TCP4BATCH_DEFAULT 2358#define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab 2359#endif 2360#endif 2361 2362/* Workaround for Cassini rev2 descriptor corruption problem. 2363 * Does batching without reassembly, and sets the SAP to a known 2364 * data pattern for all packets. 2365 */ 2366#ifdef USE_HP_WORKAROUND 2367static cas_hp_inst_t cas_prog_workaroundtab[] = { 2368 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, 2369 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} , 2370 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2371 IM_CTL, 0x04a, 3, 0x0, 0xffff}, 2372 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, 2373 CL_REG, 0x000, 0, 0x0, 0x0000}, 2374 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2375 CL_REG, 0x000, 0, 0x0, 0x0000}, 2376 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, 2377 CL_REG, 0x000, 0, 0x0, 0x0000}, 2378 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, 2379 CL_REG, 0x000, 0, 0x0, 0x0000}, 2380 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2381 IM_SAP, 0x6AE, 3, 0x0, 0xffff}, 2382 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, 2383 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2384 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, 2385 LD_LEN, 0x03e, 1, 0x0, 0xffff}, 2386 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, 2387 LD_FID, 0x182, 3, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2388 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, 2389 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2390 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, 2391 IM_R1, 0x128, 1, 0x0, 0xffff}, 2392 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, 2393 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2394 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, 2395 LD_LEN, 0x03f, 1, 0x0, 0xffff}, 2396 { "TCP seq", /* DADDR should point to dest port */ 2397 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ, 2398 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2399 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0, 2400 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f}, /* Load TCP flags */ 2401 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2402 LD_R1, 0x205, 3, 0xB, 0xf000}, 2403 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2404 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2405 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2406 IM_SAP, 0x6AE, 3, 0x0, 0xffff} , 2407 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2408 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2409 { NULL }, 2410}; 2411#ifdef HP_WORKAROUND_DEFAULT 2412#define CAS_HP_FIRMWARE cas_prog_workaroundtab 2413#endif 2414#endif 2415 2416#ifdef USE_HP_ENCRYPT 2417static cas_hp_inst_t cas_prog_encryptiontab[] = { 2418 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, 2419 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000}, 2420 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, 2421 IM_CTL, 0x00a, 3, 0x0, 0xffff}, 2422#if 0 2423//"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */ 2424//0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00 2425 00, 2426#endif 2427 { "CFI?", /* FIND CFI and If FIND go to CleanUP1 (ignore and send to host) */ 2428 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023, 2429 CL_REG, 0x000, 0, 0x0, 0x0000}, 2430 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, 2431 CL_REG, 0x000, 0, 0x0, 0x0000}, 2432 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, 2433 CL_REG, 0x000, 0, 0x0, 0x0000}, 2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, 2435 CL_REG, 0x000, 0, 0x0, 0x0000}, 2436 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, 2437 LD_SAP, 0x100, 3, 0x0, 0xffff}, 2438 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, 2439 LD_SUM, 0x00a, 1, 0x0, 0x0000}, 2440 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, 2441 LD_LEN, 0x03e, 1, 0x0, 0xffff}, 2442 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4, 2443 LD_FID, 0x182, 1, 0x0, 0xffff}, /* FID IP4&TCP src+dst */ 2444 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, 2445 LD_SUM, 0x015, 1, 0x0, 0x0000}, 2446 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, 2447 IM_R1, 0x128, 1, 0x0, 0xffff}, 2448 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, 2449 LD_FID, 0x484, 1, 0x0, 0xffff}, /* FID IP6&TCP src+dst */ 2450 { "TCP64?", 2451#if 0 2452//@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff, 2453#endif 2454 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 2455 0x03f, 1, 0x0, 0xffff}, 2456 { "TCP seq", /* 14:DADDR should point to dest port */ 2457 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ, 2458 0x081, 3, 0x0, 0xffff}, /* Load TCP seq # */ 2459 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0, 2460 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f}, /* Load TCP flags */ 2461 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc, 2462 LD_R1, 0x205, 3, 0xB, 0xf000} , 2463 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, 2464 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff}, 2465 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2, 2466 IM_CTL, 0x001, 3, 0x0, 0x0001}, 2467 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2468 CL_REG, 0x002, 3, 0x0, 0x0000}, 2469 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2470 IM_CTL, 0x080, 3, 0x0, 0xffff}, 2471 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT, 2472 IM_CTL, 0x044, 3, 0x0, 0xffff}, 2473 { "IPV4 ESP encrypted?", /* S1_ESP4 */ 2474 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL, 2475 0x021, 1, 0x0, 0xffff}, 2476 { "IPV4 AH encrypted?", /* S1_AH4 */ 2477 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 2478 0x021, 1, 0x0, 0xffff}, 2479 { "IPV6 ESP encrypted?", /* S1_ESP6 */ 2480#if 0 2481//@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff, 2482#endif 2483 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 2484 0x021, 1, 0x0, 0xffff}, 2485 { "IPV6 AH encrypted?", /* S1_AH6 */ 2486#if 0 2487//@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff, 2488#endif 2489 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 2490 0x021, 1, 0x0, 0xffff}, 2491 { NULL }, 2492}; 2493#ifdef HP_ENCRYPT_DEFAULT 2494#define CAS_HP_FIRMWARE cas_prog_encryptiontab 2495#endif 2496#endif 2497 2498static cas_hp_inst_t cas_prog_null[] = { {NULL} }; 2499#ifdef HP_NULL_DEFAULT 2500#define CAS_HP_FIRMWARE cas_prog_null 2501#endif 2502 2503/* phy types */ 2504#define CAS_PHY_UNKNOWN 0x00 2505#define CAS_PHY_SERDES 0x01 2506#define CAS_PHY_MII_MDIO0 0x02 2507#define CAS_PHY_MII_MDIO1 0x04 2508#define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1)) 2509 2510/* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE 2511 * is the actual size. the default index for the various rings is 2512 * 8. NOTE: there a bunch of alignment constraints for the rings. to 2513 * deal with that, i just allocate rings to create the desired 2514 * alignment. here are the constraints: 2515 * RX DESC and COMP rings must be 8KB aligned 2516 * TX DESC must be 2KB aligned. 2517 * if you change the numbers, be cognizant of how the alignment will change 2518 * in INIT_BLOCK as well. 2519 */ 2520 2521#define DESC_RING_I_TO_S(x) (32*(1 << (x))) 2522#define COMP_RING_I_TO_S(x) (128*(1 << (x))) 2523#define TX_DESC_RING_INDEX 4 /* 512 = 8k */ 2524#define RX_DESC_RING_INDEX 4 /* 512 = 8k */ 2525#define RX_COMP_RING_INDEX 4 /* 2048 = 64k: should be 4x rx ring size */ 2526 2527#if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0) 2528#error TX_DESC_RING_INDEX must be between 0 and 8 2529#endif 2530 2531#if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0) 2532#error RX_DESC_RING_INDEX must be between 0 and 8 2533#endif 2534 2535#if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0) 2536#error RX_COMP_RING_INDEX must be between 0 and 8 2537#endif 2538 2539#define N_TX_RINGS MAX_TX_RINGS /* for QoS */ 2540#define N_TX_RINGS_MASK MAX_TX_RINGS_MASK 2541#define N_RX_DESC_RINGS MAX_RX_DESC_RINGS /* 1 for ipsec */ 2542#define N_RX_COMP_RINGS 0x1 /* for mult. PCI interrupts */ 2543 2544/* number of flows that can go through re-assembly */ 2545#define N_RX_FLOWS 64 2546 2547#define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX) 2548#define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX) 2549#define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX) 2550#define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX 2551#define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX 2552#define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX 2553#define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE 2554#define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE 2555#define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE 2556 2557/* convert values */ 2558#define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK)) 2559#define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT)) 2560#define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \ 2561 TX_CFG_DESC_RINGN_SHIFT(y)) & \ 2562 TX_CFG_DESC_RINGN_MASK(y)) 2563 2564/* min is 2k, but we can't do jumbo frames unless it's at least 8k */ 2565#define CAS_MIN_PAGE_SHIFT 11 /* 2048 */ 2566#define CAS_JUMBO_PAGE_SHIFT 13 /* 8192 */ 2567#define CAS_MAX_PAGE_SHIFT 14 /* 16384 */ 2568 2569#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL /* buffer length in 2570 bytes. 0 - 9256 */ 2571#define TX_DESC_BUFLEN_SHIFT 0 2572#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL /* checksum start. # 2573 of bytes to be 2574 skipped before 2575 csum calc begins. 2576 value must be 2577 even */ 2578#define TX_DESC_CSUM_START_SHIFT 15 2579#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL /* checksum stuff. 2580 byte offset w/in 2581 the pkt for the 2582 1st csum byte. 2583 must be > 8 */ 2584#define TX_DESC_CSUM_STUFF_SHIFT 21 2585#define TX_DESC_CSUM_EN 0x0000000020000000ULL /* enable checksum */ 2586#define TX_DESC_EOF 0x0000000040000000ULL /* end of frame */ 2587#define TX_DESC_SOF 0x0000000080000000ULL /* start of frame */ 2588#define TX_DESC_INTME 0x0000000100000000ULL /* interrupt me */ 2589#define TX_DESC_NO_CRC 0x0000000200000000ULL /* debugging only. 2590 CRC will not be 2591 inserted into 2592 outgoing frame. */ 2593struct cas_tx_desc { 2594 __le64 control; 2595 __le64 buffer; 2596}; 2597 2598/* descriptor ring for free buffers contains page-sized buffers. the index 2599 * value is not used by the hw in any way. it's just stored and returned in 2600 * the completion ring. 2601 */ 2602struct cas_rx_desc { 2603 __le64 index; 2604 __le64 buffer; 2605}; 2606 2607/* received packets are put on the completion ring. */ 2608/* word 1 */ 2609#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL 2610#define RX_COMP1_DATA_SIZE_SHIFT 13 2611#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL 2612#define RX_COMP1_DATA_OFF_SHIFT 27 2613#define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL 2614#define RX_COMP1_DATA_INDEX_SHIFT 41 2615#define RX_COMP1_SKIP_MASK 0x0180000000000000ULL 2616#define RX_COMP1_SKIP_SHIFT 55 2617#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL 2618#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL 2619#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL 2620#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL 2621#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL 2622#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL 2623#define RX_COMP1_TYPE_SHIFT 62 2624 2625/* word 2 */ 2626#define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL 2627#define RX_COMP2_NEXT_INDEX_SHIFT 21 2628#define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL 2629#define RX_COMP2_HDR_SIZE_SHIFT 35 2630#define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL 2631#define RX_COMP2_HDR_OFF_SHIFT 44 2632#define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL 2633#define RX_COMP2_HDR_INDEX_SHIFT 50 2634 2635/* word 3 */ 2636#define RX_COMP3_SMALL_PKT 0x0000000000000001ULL 2637#define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL 2638#define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL 2639#define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL 2640#define RX_COMP3_CSUM_START_SHIFT 12 2641#define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL 2642#define RX_COMP3_FLOWID_SHIFT 19 2643#define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL 2644#define RX_COMP3_OPCODE_SHIFT 25 2645#define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL 2646#define RX_COMP3_NO_ASSIST 0x0000000020000000ULL 2647#define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL 2648#define RX_COMP3_LOAD_BAL_SHIFT 35 2649#define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL /* cas+ */ 2650#define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL /* cas */ 2651#define RX_COMP3_L3_HEAD_OFF_SHIFT 41 2652#define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL /* cas+ */ 2653#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42 2654#define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL 2655#define RX_COMP3_SAP_SHIFT 48 2656 2657/* word 4 */ 2658#define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL 2659#define RX_COMP4_TCP_CSUM_SHIFT 0 2660#define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL 2661#define RX_COMP4_PKT_LEN_SHIFT 16 2662#define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL 2663#define RX_COMP4_PERFECT_MATCH_SHIFT 30 2664#define RX_COMP4_ZERO 0x0000080000000000ULL 2665#define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL 2666#define RX_COMP4_HASH_VAL_SHIFT 44 2667#define RX_COMP4_HASH_PASS 0x1000000000000000ULL 2668#define RX_COMP4_BAD 0x4000000000000000ULL 2669#define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL 2670 2671/* we encode the following: ring/index/release. only 14 bits 2672 * are usable. 2673 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and 2674 * MAX_RX_DESC_RINGS. */ 2675#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL 2676#define RX_INDEX_NUM_SHIFT 0 2677#define RX_INDEX_RING_MASK 0x0000000000001000ULL 2678#define RX_INDEX_RING_SHIFT 12 2679#define RX_INDEX_RELEASE 0x0000000000002000ULL 2680 2681struct cas_rx_comp { 2682 __le64 word1; 2683 __le64 word2; 2684 __le64 word3; 2685 __le64 word4; 2686}; 2687 2688enum link_state { 2689 link_down = 0, /* No link, will retry */ 2690 link_aneg, /* Autoneg in progress */ 2691 link_force_try, /* Try Forced link speed */ 2692 link_force_ret, /* Forced mode worked, retrying autoneg */ 2693 link_force_ok, /* Stay in forced mode */ 2694 link_up /* Link is up */ 2695}; 2696 2697typedef struct cas_page { 2698 struct list_head list; 2699 struct page *buffer; 2700 dma_addr_t dma_addr; 2701 int used; 2702} cas_page_t; 2703 2704 2705/* some alignment constraints: 2706 * TX DESC, RX DESC, and RX COMP must each be 8K aligned. 2707 * TX COMPWB must be 8-byte aligned. 2708 * to accomplish this, here's what we do: 2709 * 2710 * INIT_BLOCK_RX_COMP = 64k (already aligned) 2711 * INIT_BLOCK_RX_DESC = 8k 2712 * INIT_BLOCK_TX = 8k 2713 * INIT_BLOCK_RX1_DESC = 8k 2714 * TX COMPWB 2715 */ 2716#define INIT_BLOCK_TX (TX_DESC_RING_SIZE) 2717#define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE) 2718#define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE) 2719 2720struct cas_init_block { 2721 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP]; 2722 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC]; 2723 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX]; 2724 __le64 tx_compwb; 2725}; 2726 2727/* tiny buffers to deal with target abort issue. we allocate a bit 2728 * over so that we don't have target abort issues with these buffers 2729 * as well. 2730 */ 2731#define TX_TINY_BUF_LEN 0x100 2732#define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN) 2733 2734struct cas_tiny_count { 2735 int nbufs; 2736 int used; 2737}; 2738 2739struct cas { 2740 spinlock_t lock; /* for most bits */ 2741 spinlock_t tx_lock[N_TX_RINGS]; /* tx bits */ 2742 spinlock_t stat_lock[N_TX_RINGS + 1]; /* for stat gathering */ 2743 spinlock_t rx_inuse_lock; /* rx inuse list */ 2744 spinlock_t rx_spare_lock; /* rx spare list */ 2745 2746 void __iomem *regs; 2747 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS]; 2748 int rx_old[N_RX_DESC_RINGS]; 2749 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS]; 2750 int rx_last[N_RX_DESC_RINGS]; 2751 2752 struct napi_struct napi; 2753 2754 /* Set when chip is actually in operational state 2755 * (ie. not power managed) */ 2756 int hw_running; 2757 int opened; 2758 struct mutex pm_mutex; /* open/close/suspend/resume */ 2759 2760 struct cas_init_block *init_block; 2761 struct cas_tx_desc *init_txds[MAX_TX_RINGS]; 2762 struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS]; 2763 struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS]; 2764 2765 /* we use sk_buffs for tx and pages for rx. the rx skbuffs 2766 * are there for flow re-assembly. */ 2767 struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE]; 2768 struct sk_buff_head rx_flows[N_RX_FLOWS]; 2769 cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE]; 2770 struct list_head rx_spare_list, rx_inuse_list; 2771 int rx_spares_needed; 2772 2773 /* for small packets when copying would be quicker than 2774 mapping */ 2775 struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE]; 2776 u8 *tx_tiny_bufs[N_TX_RINGS]; 2777 2778 u32 msg_enable; 2779 2780 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */ 2781 struct net_device_stats net_stats[N_TX_RINGS + 1]; 2782 2783 u32 pci_cfg[64 >> 2]; 2784 u8 pci_revision; 2785 2786 int phy_type; 2787 int phy_addr; 2788 u32 phy_id; 2789#define CAS_FLAG_1000MB_CAP 0x00000001 2790#define CAS_FLAG_REG_PLUS 0x00000002 2791#define CAS_FLAG_TARGET_ABORT 0x00000004 2792#define CAS_FLAG_SATURN 0x00000008 2793#define CAS_FLAG_RXD_POST_MASK 0x000000F0 2794#define CAS_FLAG_RXD_POST_SHIFT 4 2795#define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \ 2796 CAS_FLAG_RXD_POST_MASK) 2797#define CAS_FLAG_ENTROPY_DEV 0x00000100 2798#define CAS_FLAG_NO_HW_CSUM 0x00000200 2799 u32 cas_flags; 2800 int packet_min; /* minimum packet size */ 2801 int tx_fifo_size; 2802 int rx_fifo_size; 2803 int rx_pause_off; 2804 int rx_pause_on; 2805 int crc_size; /* 4 if half-duplex */ 2806 2807 int pci_irq_INTC; 2808 int min_frame_size; /* for tx fifo workaround */ 2809 2810 /* page size allocation */ 2811 int page_size; 2812 int page_order; 2813 int mtu_stride; 2814 2815 u32 mac_rx_cfg; 2816 2817 /* Autoneg & PHY control */ 2818 int link_cntl; 2819 int link_fcntl; 2820 enum link_state lstate; 2821 struct timer_list link_timer; 2822 int timer_ticks; 2823 struct work_struct reset_task; 2824#if 0 2825 atomic_t reset_task_pending; 2826#else 2827 atomic_t reset_task_pending; 2828 atomic_t reset_task_pending_mtu; 2829 atomic_t reset_task_pending_spare; 2830 atomic_t reset_task_pending_all; 2831#endif 2832 2833 /* Link-down problem workaround */ 2834#define LINK_TRANSITION_UNKNOWN 0 2835#define LINK_TRANSITION_ON_FAILURE 1 2836#define LINK_TRANSITION_STILL_FAILED 2 2837#define LINK_TRANSITION_LINK_UP 3 2838#define LINK_TRANSITION_LINK_CONFIG 4 2839#define LINK_TRANSITION_LINK_DOWN 5 2840#define LINK_TRANSITION_REQUESTED_RESET 6 2841 int link_transition; 2842 int link_transition_jiffies_valid; 2843 unsigned long link_transition_jiffies; 2844 2845 /* Tuning */ 2846 u8 orig_cacheline_size; /* value when loaded */ 2847#define CAS_PREF_CACHELINE_SIZE 0x20 /* Minimum desired */ 2848 2849 /* Diagnostic counters and state. */ 2850 int casreg_len; /* reg-space size for dumping */ 2851 u64 pause_entered; 2852 u16 pause_last_time_recvd; 2853 2854 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS]; 2855 struct pci_dev *pdev; 2856 struct net_device *dev; 2857#if defined(CONFIG_OF) 2858 struct device_node *of_node; 2859#endif 2860 2861 /* Firmware Info */ 2862 u16 fw_load_addr; 2863 u32 fw_size; 2864 u8 *fw_data; 2865}; 2866 2867#define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1)) 2868#define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1)) 2869#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1)) 2870 2871#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \ 2872 (TX_DESC_RINGN_SIZE(r) - (x) + (y))) 2873 2874#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \ 2875 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \ 2876 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1) 2877 2878#define CAS_ALIGN(addr, align) \ 2879 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1)) 2880 2881#define RX_FIFO_SIZE 16384 2882#define EXPANSION_ROM_SIZE 65536 2883 2884#define CAS_MC_EXACT_MATCH_SIZE 15 2885#define CAS_MC_HASH_SIZE 256 2886#define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \ 2887 CAS_MC_HASH_SIZE) 2888 2889#define TX_TARGET_ABORT_LEN 0x20 2890#define RX_SWIVEL_OFF_VAL 0x2 2891#define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1) 2892#define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1) 2893#define RX_BLANK_INTR_PKT_VAL 0x05 2894#define RX_BLANK_INTR_TIME_VAL 0x0F 2895#define HP_TCP_THRESH_VAL 1530 /* reduce to enable reassembly */ 2896 2897#define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1) 2898#define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2) 2899 2900#endif /* _CASSINI_H */ 2901