1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3  MAC 10/100 Header File
4
5  Copyright (C) 2007-2009  STMicroelectronics Ltd
6
7
8  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#ifndef __DWMAC100_H__
12#define __DWMAC100_H__
13
14#include <linux/phy.h>
15#include "common.h"
16
17/*----------------------------------------------------------------------------
18 *	 			MAC BLOCK defines
19 *---------------------------------------------------------------------------*/
20/* MAC CSR offset */
21#define MAC_CONTROL	0x00000000	/* MAC Control */
22#define MAC_ADDR_HIGH	0x00000004	/* MAC Address High */
23#define MAC_ADDR_LOW	0x00000008	/* MAC Address Low */
24#define MAC_HASH_HIGH	0x0000000c	/* Multicast Hash Table High */
25#define MAC_HASH_LOW	0x00000010	/* Multicast Hash Table Low */
26#define MAC_MII_ADDR	0x00000014	/* MII Address */
27#define MAC_MII_DATA	0x00000018	/* MII Data */
28#define MAC_FLOW_CTRL	0x0000001c	/* Flow Control */
29#define MAC_VLAN1	0x00000020	/* VLAN1 Tag */
30#define MAC_VLAN2	0x00000024	/* VLAN2 Tag */
31
32/* MAC CTRL defines */
33#define MAC_CONTROL_RA	0x80000000	/* Receive All Mode */
34#define MAC_CONTROL_BLE	0x40000000	/* Endian Mode */
35#define MAC_CONTROL_HBD	0x10000000	/* Heartbeat Disable */
36#define MAC_CONTROL_PS	0x08000000	/* Port Select */
37#define MAC_CONTROL_DRO	0x00800000	/* Disable Receive Own */
38#define MAC_CONTROL_EXT_LOOPBACK 0x00400000	/* Reserved (ext loopback?) */
39#define MAC_CONTROL_OM	0x00200000	/* Loopback Operating Mode */
40#define MAC_CONTROL_F	0x00100000	/* Full Duplex Mode */
41#define MAC_CONTROL_PM	0x00080000	/* Pass All Multicast */
42#define MAC_CONTROL_PR	0x00040000	/* Promiscuous Mode */
43#define MAC_CONTROL_IF	0x00020000	/* Inverse Filtering */
44#define MAC_CONTROL_PB	0x00010000	/* Pass Bad Frames */
45#define MAC_CONTROL_HO	0x00008000	/* Hash Only Filtering Mode */
46#define MAC_CONTROL_HP	0x00002000	/* Hash/Perfect Filtering Mode */
47#define MAC_CONTROL_LCC	0x00001000	/* Late Collision Control */
48#define MAC_CONTROL_DBF	0x00000800	/* Disable Broadcast Frames */
49#define MAC_CONTROL_DRTY	0x00000400	/* Disable Retry */
50#define MAC_CONTROL_ASTP	0x00000100	/* Automatic Pad Stripping */
51#define MAC_CONTROL_BOLMT_10	0x00000000	/* Back Off Limit 10 */
52#define MAC_CONTROL_BOLMT_8	0x00000040	/* Back Off Limit 8 */
53#define MAC_CONTROL_BOLMT_4	0x00000080	/* Back Off Limit 4 */
54#define MAC_CONTROL_BOLMT_1	0x000000c0	/* Back Off Limit 1 */
55#define MAC_CONTROL_DC		0x00000020	/* Deferral Check */
56#define MAC_CONTROL_TE		0x00000008	/* Transmitter Enable */
57#define MAC_CONTROL_RE		0x00000004	/* Receiver Enable */
58
59#define MAC_CORE_INIT (MAC_CONTROL_HBD)
60
61/* MAC FLOW CTRL defines */
62#define MAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */
63#define MAC_FLOW_CTRL_PT_SHIFT	16
64#define MAC_FLOW_CTRL_PASS	0x00000004	/* Pass Control Frames */
65#define MAC_FLOW_CTRL_ENABLE	0x00000002	/* Flow Control Enable */
66#define MAC_FLOW_CTRL_PAUSE	0x00000001	/* Flow Control Busy ... */
67
68/* MII ADDR  defines */
69#define MAC_MII_ADDR_WRITE	0x00000002	/* MII Write */
70#define MAC_MII_ADDR_BUSY	0x00000001	/* MII Busy */
71
72/*----------------------------------------------------------------------------
73 * 				DMA BLOCK defines
74 *---------------------------------------------------------------------------*/
75
76/* DMA Bus Mode register defines */
77#define DMA_BUS_MODE_DBO	0x00100000	/* Descriptor Byte Ordering */
78#define DMA_BUS_MODE_BLE	0x00000080	/* Big Endian/Little Endian */
79#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */
80#define DMA_BUS_MODE_PBL_SHIFT	8
81#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */
82#define DMA_BUS_MODE_DSL_SHIFT	2	/*   (in DWORDS)      */
83#define DMA_BUS_MODE_BAR_BUS	0x00000002	/* Bar-Bus Arbitration */
84#define DMA_BUS_MODE_DEFAULT	0x00000000
85
86/* DMA Control register defines */
87#define DMA_CONTROL_SF		0x00200000	/* Store And Forward */
88
89/* Transmit Threshold Control */
90enum ttc_control {
91	DMA_CONTROL_TTC_DEFAULT = 0x00000000,	/* Threshold is 32 DWORDS */
92	DMA_CONTROL_TTC_64 = 0x00004000,	/* Threshold is 64 DWORDS */
93	DMA_CONTROL_TTC_128 = 0x00008000,	/* Threshold is 128 DWORDS */
94	DMA_CONTROL_TTC_256 = 0x0000c000,	/* Threshold is 256 DWORDS */
95	DMA_CONTROL_TTC_18 = 0x00400000,	/* Threshold is 18 DWORDS */
96	DMA_CONTROL_TTC_24 = 0x00404000,	/* Threshold is 24 DWORDS */
97	DMA_CONTROL_TTC_32 = 0x00408000,	/* Threshold is 32 DWORDS */
98	DMA_CONTROL_TTC_40 = 0x0040c000,	/* Threshold is 40 DWORDS */
99	DMA_CONTROL_SE = 0x00000008,	/* Stop On Empty */
100	DMA_CONTROL_OSF = 0x00000004,	/* Operate On 2nd Frame */
101};
102
103/* STMAC110 DMA Missed Frame Counter register defines */
104#define DMA_MISSED_FRAME_OVE	0x10000000	/* FIFO Overflow Overflow */
105#define DMA_MISSED_FRAME_OVE_CNTR 0x0ffe0000	/* Overflow Frame Counter */
106#define DMA_MISSED_FRAME_OVE_M	0x00010000	/* Missed Frame Overflow */
107#define DMA_MISSED_FRAME_M_CNTR	0x0000ffff	/* Missed Frame Couinter */
108
109extern const struct stmmac_dma_ops dwmac100_dma_ops;
110
111#endif /* __DWMAC100_H__ */
112